L296 L296P HIGH CURRENT SWITCHING REGULATORS .. .. .. .. .. .. . 4 A OUTPUT CURRENT 5.1 V TO 40 V OUTPUT VOLTAGE RANGE 0 TO 100 % DUTY CYCLE RANGE PRECISE (2 %) ON-CHIP REFERENCE SWITCHING FREQUENCY UP TO 200 KHz VERY HIGH EFFICIENCY (UP TO 90 %) VERY FEW EXTERNAL COMPONENTS SOFT START RESET OUTPUT EXTERNAL PROGRAMMABLE LIMITING CURRENT (L296P) CONTROL CIRCUIT FOR CROWBAR SCR INPUT FOR REMOTE INHIBIT AND SYNCHRONUS PWM THERMAL SHUTDOWN DESCRIPTION The L296 and L296P are stepdown power switching regulators delivering 4 A at a voltage variable from 5.1 V to 40 V. Features of the devices include soft start, remote inhibit, thermal protection, a reset output for microprocessors and a PWM comparator input for synchronization in multichip configurations. The L296P incudes external programmable limiting current. Mu ltiwatt (15 lead) ORDERING NUMBERS : L296 (Vertical) L296HT (Horizontal) L296P (Vertical) L296PHT (Horizontal) The L296 and L296P are mounted in a 15-lead Multiwatt plastic power packageand requires very few external components. Efficient operation at switching frequencies up to 200 KHz allows a reduction in the size and cost of external filter components. A voltage sense input and SCR drive output are provided for optional crowbar overvoltage protection with an external SCR. PIN CONNECTION (top view) April 1993 1/21 L296 - L296P PIN FUNCTIONS N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name CROWBAR INPUT Function Voltage Sense Input for Crowbar Overvoltage Protection. Normally connected to the feedback input thus triggering the SCR when V out exceeds nominal by 20 %. May also monitor the input and a voltage divider can be added to increase the threshold. Connected to ground when SCR not used. OUTPUT Regulator Output SUPPLY VOLTAGE Unrergulated Voltage Input. An internal Regulator Powers the L296s Internal Logic. CURRENT LIMIT A resistor connected between this terminal and ground sets the current limiter threshold. If this terminal is left unconnected the threshold is internally set (see electrical characteristics). SOFT START Soft Start Time Constant. A capacitor is connected between this terminal and ground to define the soft start time constant. This capacitor also determines the average short circuit output current. INHIBIT INPUT TTL - Level Remote Inhibit. A logic high level on this input disables the device. SYNC INPUT Multiple L296s are synchronized by connecting the pin 7 inputs together and omitting the oscillator RC network on all but one device. GROUND Common Ground Terminal FREQUENCY A series RC network connected between this terminal and ground determines the COMPENSATION regulation loop gain characteristics. FEEDBACK INPUT The Feedback Terminal on the Regulation Loop. The output is connected directly to this terminal for 5.1V operation ; it is connected via a divider for higher voltages. OSCILLATOR A parallel RC networki connected to this terminal determines the switching frequency. This pin must be connected to pin 7 input when the internal oscillator is used. RESET INPUT Input of the Reset Circuit. The threshold is roughly 5 V. It may be connected to the feedback point or via a divider to the input. RESET DELAY A capacitor connected between this terminal and ground determines the reset signal delay time. RESET OUTPUT Open collector reset signal output. This output is high when the supply is safe. CROWBAR OUTPUT SCR gate drive output of the crowbar circuit. BLOCK DIAGRAM 2/21 L296 - L296P CIRCUIT OPERATION (refer to the block diagram) The L296 and L296P are monolithic stepdown switching regulators providing output voltages from 5.1V to 40V and delivering 4A. The regulationloop consists of a sawtooth oscillator, error amplifier, comparator and the output stage. An error signal is produced by comparing the output voltage with a precise 5.1V on-chip reference (zener zap trimmed to 2 %). This error signal is thencompared with the sawtooth signal to generate the fixed frequencypulse width modulatedpulses which drive the output stage. The gain and frequency stability of the loop can be adjusted by an external RC network connectedto pin 9. Closing the loop directly gives an output voltage of 5.1V. Higher voltages are obtained by inserting a voltage divider. Output overcurrents at switch on are prevented by the soft start function. The error amplifier output is initially clamped by the external capacitor Css and allowed to rise, linearly, as this capacitor is charged by a constant current source. Output overload protection is provided in the form of a current limiter. The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold this comparator sets a flip flop which disables the output stage and discharges the soft start capacitor. A second comparator resets the flip flop when the voltage across the soft start capacitor has fallen to 0.4V. The output stage is thus re-enabled and the output voltage rises under control of the soft start network. If the overload condition is still present the limiter will trigger again when the threshold current is reached. The average short circuit current is limited to a safe value by the dead time introduced by the soft start network. The reset circuit generates an output signal when the supply voltage exceeds a threshold programmed by an external divider. The reset signal is generated with a delay time programmed by an external capacitor. When the supply falls below the threshold the reset output goes low immediately. The reset output is an open collector. The scrowbar circuit senses the output voltage and the crowbar output can provide a current of 100mA to switch on an external SCR. This SCR is triggered when the output voltage exceeds the nominal by 20%. There is no internal connection between the output and crowbar sense input therefore the crowbar can monitor either the input or the output. A TTL - level inhibit input is provided for applications such as remote on/offcontrol. This input is activated by high logic level and disables circuit operation. After an inhibit the L296 restarts under control of the soft start network. The thermal overload circuit disables circuit operation when the junction temperature reaches about 150 C and has hysteresis to prevent unstable conditions. Figure 1 : Reset Output Waveforms 3/21 L296 - L296P Figure 2 : Soft Start Waveforms Figure 3 : Current Limiter Waveforms ABSOLUTE MAXIMUM RATINGS Symbol Vi Vi - V2 Value Unit 50 V Input to Output Voltage Difference 50 V Output DC Voltage Output Peak Voltage at t = 0.1 sec f = 200KHz -1 -7 V V Voltage at Pins 1, 12 10 V Voltage at Pin 15 15 V Voltage at Pins 4, 5, 7, 9 and 13 5.5 V Voltage at Pins 10 and 6 7 V Voltage at Pin 14 (I14 1 mA) Vi I9 Pin 9 Sink Current 1 mA I11 Pin 11 Source Current 20 mA I14 Pin 14 Sink Current (V14 < 5 V) 50 mA Ptot Power Dissipation at Tcase 90 C 20 W Tj, Tstg Junction and Storage Temperature - 40 to 150 C V2 V1, V12 V15 V4, V5, V7, V9, V13 V10, V6 V14 4/21 Parameter Input Voltage (pin 3) L296 - L296P THERMAL DATA Symbol Parameter Value Unit Rth j-case Thermal Resistance Junction-case Max. 3 C/W Rth j-amb Thermal Resistance Junction-ambient Max. 35 C/W ELECTRICAL CHARACTERISTICS (refer to the test circuits T j = 25oC, Vi = 35V, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig. DYNAMIC CHARACTERISTICS (pin 6 to GND unless otherwise specified) Vo Output Voltage Range Vi = 46V, Io = 1A Vi Input Voltage Range Vo = Vref to 36V, Io 3A Vi Input Voltage Range Note (1), Vo = VREF to 36V Io = 4A Vo Line Regulation Vi =10V to 40V, Vo = Vref, Io = 2A Vo Load Regulation Vo = Vref Io = 2A to 4A Io = 0.5A to 4A Internal Reference Voltage (pin 10) Vi = 9V to 46V, Io = 2A Vref Vref T Vref 40 V 4 9 46 V 4 46 V 4 15 5 10 15 30 45 5.1 5.2 Average Temperature Coefficient of Reference Voltage Tj = 0C to 125C, Io = 2A 0.4 Vd Dropout Voltage Between Pin 2 and Pin 3 Io = 4A Io = 2A 2 1.3 I2L Current Limiting Threshold (pin 2) L296 - Pin 4 Open, Vi = 9V to 40V, Vo = Vref to 36V L296P - Vi = 9V to 40V, Vo = Vref Pin 4 Open R Iim = 22k ISH SVR f Input Average Current Vi = 46V, Output Short-circuited Efficiency Io = 3 A Vo = Vref Vo = 12V Supply Voltage Ripple Rejection Vi = 2 Vrms, fripple = 100Hz Vo = Vref, Io = 2A Switching Frequency 50 mV 4 mV 4 V 4 mV/C 3.2 2.1 V V 4 4 4.5 7.5 A 4 A 4 5 2.5 7 4.5 60 100 mA 4 % 4 dB 4 75 85 50 56 85 100 f Vi Voltage Stability of Switching Frequency Vi = 9V to 46V f Tj Temperature Stability of Switching Frequency Tj = 0C to 125C fmax Maximum Operating Switching Frequency Vo = Vref, Io = 1A 200 Tsd Thermal Shutdown Junction Temperature Note (2) 135 kHz 4 0.5 115 % 4 1 % 4 kHz - C - 145 DC CHARACTERISTICS I3Q - I2L Note Quiescent Drain Current Output Leakage Current Vi = 46V, V7 = 0V, S1 : B, S2 : B V6 = 0V V6 = 3V Vi = 46V, V6 = 3V, S1 : B, S2 : A, V7 = 0V mA 66 30 85 40 2 mA (1) : Using min. 7 A schottky diode. (2) : Guaranteed by design, not 100 % tested in production. 5/21 L296 - L296P ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig. SOFT START I5 so Source Current V6 = 0V, V 5 = 3V 80 130 150 A 6b I5 si Sink Current V6 = 3V, V 5 = 3V 50 70 120 A 6b Input Voltage Low Level High Level Vi = 9V to 46V, V7 = 0V, S1 : B, S2 : B V 6a V6L V6H Vi = 9V to 46V, V7 = 0V, S1 : B, S2 : B V6 = 0.8V V6 = 2V A 6a - I6L - I6H Input Current with Input Voltage Low Level High Level V 6c V 6c INHIBIT - 0.3 2 0.8 5.5 10 3 ERROR AMPLIFIER V9H High Level Output Voltage V10 = 4.7V, I9 = 100A, S1 : A, S2 : A V9L Low Level Output Voltage V10 = 5.3V, I9 = 100A, S1 : A, S2 : E I9 si Sink Output Current V10 = 5.3V, S1 : A, S2 : B 100 150 A 6c Source Output Current V10 = 4.7V, S1 : A, S2 : D 100 150 A 6c I10 Input Bias Current V10 = 5.2V, S1 : B V10 = 6.4V, S1 : B, L296P A A 6c 6c Gv DC Open Loop Gain V9 = 1V to 3V, S1 : A, S2 : C dB 6c A 6a - I9 so 3.5 0.5 2 2 46 10 10 55 OSCILLATOR AND PWM COMPARATOR - I7 Input Bias Current of PWM Comparator V7 = 0.5V to 3.5V - I11 Oscillator Source Current V11 = 2V, S1 : A, S2 : B 5 5 mA RESET V12 R Rising Threshold Voltage Vi = 9V to 46V, S1 : B, S2 : B V12 F Falling Threshold Voltage V13 D Delay Thershold Voltage V13 H Delay Threshold Voltage Hysteresis V14 S Output Saturation Voltage I14 = 16mA, V12 = 4.7V, S1, S2 : B Input Bias Current V12 = 0V to Vref, S1 : B, S2 : B Delay Source Current Delay Sink Current V13 = 3V, S1 : A, S2 : B V12 = 5.3V V12 = 4.7V Output Leakage Current Vi = 46V, V12 = 5.3V, S1 : B, S2 : A I12 - I13 so I13 si I14 Vref Vref -150mV -100mV 4.75 4.3 V12 = 5.3V, S1 : A, S2 : B Vref -50mV V 6d Vref Vref -150mV -100mV V 6d 4.5 4.7 100 70 10 V 6d mV 6d 0.4 V 6d 1 3 A 6d 110 140 A mA 100 A 6d 6 6.4 V 6b 0.2 0.4 V 6b A 6b mA 6b 6d CROWBAR V1 Input Threshold Voltage S1 : B V15 Output Saturation Voltage Vi = 9V to 46V, Vi = 5.4V, I15 = 5mA, S1 : A Input Bias Current V1 = 6V, S1 : B Output Source Current Vi = 9V to 46V, V1 = 6.5V, V15 = 2V, S1 : B I1 - I15 6/21 5.5 10 70 100 L296 - L296P Figure 4 : Dynamic Test Circuit C7, C8 : EKR (ROE) L1 : L = 300 H at 8 A Core type : MAGNETICS 58930 - A2 MPP N turns : 43 Wire Gauge : 1 mm (18 AWG) COGEMA 946044 (*) Minimum suggested value (10 F) to avoid oscillations. Ripple consideration leads to typical value of 1000 F or higher. Figure 5 : PC. Board and Component Layout of the Circuit of Figure 4 (1:1 scale) 7/21 L296 - L296P Figure 6 : DC Test Circuits. Figure 6a. Figure 6b. Figure 6c. 1 - Set V10 FOR V9 = 1 V 2 - Change V10 to obtain V9 = 3 V 3 - GV = DV9 V10 Figure 6d. 8/21 = 2V V10 L296 - L296P Figure 7 : Quienscent Drain Current vs. Supply Voltage (0 % Duty Cycle - see fig. 6a). Figure 8 : Quienscent Drain Current vs. Supply Voltage (100 % Duty Cycle see fig. 6a). Figure 9 : Quiescent Drain Current vs. Junction Temperature (0 % Duty Cycle see fig. 6a). Figure 10 : Quiescent Drain Current vs. Junction Temperature (100 % Duty Cycle see fig. 6a). Figure 11 : Reference Voltage (pin 10) vs. VI (see fig. 4). Figure 12 : Reference Voltage (pin 10) vs. Junction Temperature (see fig. 4). 9/21 L296 - L296P Figure 13 : Open Loop Frequency and Phase Response of Error Amplifier (see fig. 6c). Figure 14 : Switching Frequency vs. Input Voltage (see fig. 4). Figure 15 : Switching Frequency vs. Junction Temperature (see fig. 4). Figure 16 : Switching Frequency vs. R1 (see fig. 4). Figure 17 : Line Transient Response (see fig. 4). Figure 18 : Load Transient Response (see fig. 4). 10/21 L296 - L296P Figure 19 : Supply Voltage Ripple Rejection vs. Frequency (see fig. 4). Figure 20 : Dropout Voltage Between Pin 3 and Pin 2 vs. Current at Pin 2. Figure 21 : Dropout Voltage Between Pin 3 and Pin 2 vs. Junction Temperature. Figure 22 : Power Dissipation Derating Curve. Figure 23 : Power Dissipation (device only) vs. Input Voltage. Figure 24 : Power Dissipation (device only) vs. Input voltage. 11/21 L296 - L296P Figure 25 : Power Dissipation (device only) vs. Output Voltage (see fig. 4). Figure 26 : Power Dissipation (device only) vs. Output Voltage (see fig. 4). Figure 27 : Voltageand Current Waveforms at Pin 2 (see fig. 4). Figure 28 : Efficiency vs. Output Current. Figure 29 : Efficiency vs. Output Voltage. Figure 30 : Efficiency vs. Output Voltage. 12/21 L296 - L296P Figure 31 : Current Limiting Threshold vs. Rpin 4 (L296P only). Figure 32 : Current Limiting Threshold vs. Junction Temperature. Figure 33 : Current Limiting Threshold vs. Supply Voltage. 13/21 L296 - L296P APPLICATION INFORMATION Figure 34 : Typical Application Circuit. (*) Minimum value (10 F) to avoid oscillations ; ripple consideration leads to typical value of 1000 F or higher L1 : 58930 - MPP COGEMA 946044 ; GUP 20 COGEMA 946045 SUGGESTED INDUCTOR (L1) Core Type Magnetics 58930 - A2MPP Thomson GUP 20 x 16 x 7 Siemens EC 35/17/10 (B6633& - G0500 - X127) VOGT 250 H Toroidal Coil, Part Number 5730501800 V0 12 V 15 V 18 V 24 V 14/21 No Turns 43 65 40 Wire Gauge 1.0 mm 0.8 mm 2 x 0.8 mm Resistor Values for Standard Output Voltages R8 4.7 K 4.7 K 4.7 K 4.7 K Air Gap - 1 mm - R7 6.2 K 9.1 K 12 K 18 K L296 - L296P Figure 35 : P.C. Board and Component Layout of the Circuit of fig. 34 (1:1 scale) SELECTION OF COMPONENT VALUES (see fig. 34) Component Recommended Value R1 R2 - 100 k Set Input Voltage Threshold for Reset. R3 R4 4.3 k 10 k Sets Switching Frequency Pull-down Resistor R5 R6 15 k Frequency Compensation Collector Load For Reset Output R7 R8 - 4.7 k Divider to Set Output Voltage Riim - C1 C2 C3 C4 Purpose Allowed Rage Notes Min. Max. - Vi min -1 220k R1/R2 5 If output voltage is sensed R1 and R2 may be limited and pin 12 connected to pin 10. 1 k 100k 22k May be omitted and pin 6 grounded if inhibit not used. 10k VO Omitted if reset function not used. 0.05A - - - 1k Sets Current Limit Level 7.5k 10 F 2.2 F 2.2 nF 2.2 F Stability Sets Reset Delay Sets Switching Frequency Soft Start 2.2F - 1 nF 1 F - 3.3nF - C5 C6 33 nF 390 pF - - C7, C8 L1 Q1 100 F 300 H Frequency Compensation High Frequency Compensation Output Filter - 100H - D1 Crowbar Protection Recirculation Diode VO - VREF VREF If Riim is omitted and pin 4 left open the current limit is internally fixed. R7/R8 = Omitted if reset function not used. Also determines average short circuit current. Not required for 5 V operation. The SCR must be able to withstand the peak discharge current of the output capacitor and the short circuit current of the device. 7A Schottky or 35 ns trr Diode. 15/21 L296 - L296P Figure 36 : A Minimal 5.1 V Fixed Regulator. Very Few Components are Required. Figure 37 : 12 V/10 A Power Supply. 16/21 L296 - L296P Figure 38 : Programmable Power Supply. V o = 5.1 to 15 V I o = 4 A max. (min. load current = 100 mA) ripple 20 mV load regulation (1 A to 4 A) = 10 mV (V o = 5.1 V) line regulation (220 V 15 % and to I o = 3 A) = 15 mV (V o = 5.1 V) Figure 39 : Preregulator for Distributed Supplies. (*) L2 and C2 are necessary to reduce the switching frequency spikes. 17/21 L296 - L296P Figure 40 : In Multiple Supplies Several L296s can be Synchronized As Shown. Figure 41 : Voltage Sensing for Remote Load. Figure 42 : A 5.1 V/15 V/24 V Multiple Supply. Note the Synchronization of the Three L296s. 18/21 L296 - L296P Figure 43 : 5.1V/2A Power Supply using External Limiting Current Resistor and Crowbar Protection on the Supply Voltage (L296P only) SOFT-START AND REPETITIVE POWER-ON When the device is repetitivelypowered-on,the softstart capacitor, CSS, must be discharged rapidly to ensurethat each start is "soft". This can be achieved economicallyusing thereset circuit, as shownin Figure 44. In this circuit the divider R1, R2 connected to pin 12 determines the minimum supply voltage, below which the open collector transistor at the pin 14 output discharges CSS. Figure 44 sistor may be added, as shown in Figure 45 ; with this circuit discharge times of a few microseconds may be obtained. Figure 45 HOW TO OBTAIN BOTH RESET AND POWER FAIL Figure 46 illustrates how it is possibleto obtain at the same time both the power fail and reset functions simply by addingone diode (D) and one resistor (R). In this case the Reset delay time (pin 13) can only start when the output voltage is VO VREF - 100mV and the voltage accross R2 is higher than 4.5V. With the hysteresis resistor it is possible to fix the input pin 12 hysteresis in order to increase immunity to the 100Hz ripple present on the supply voltage. Moreover, the power fail and reset delay time are automatically locked to the soft-start. Soft-start and delayed reset are thus two sequential functions. The hysteresis resistor should be In the range of aboit 100k and the pull-up resistor of 1 to 2.2k. Figure 46 The approximate discharge times obtained with this circuit are : CSS (F) tDIS (s) 2.2 4.7 10 200 300 600 If these times are still too long, an external PNP tran- 19/21 L296 - L296P MULTIWATT15 VERTICAL PACKAGE MECHANICAL DATA Millimeters Typ. Max. 5 2.65 1.6 Min. 0.55 0.75 1.4 17.91 0.019 0.026 0.045 0.692 0.772 1 0.49 0.66 1.14 17.57 19.6 22.1 22 17.65 17.25 10.3 2.65 4.2 4.5 1.9 1.9 3.65 1.27 17.78 17.5 10.7 4.3 5.08 Inches Typ. Max. 0.197 0.104 0.063 0.039 20.2 22.6 22.5 18.1 17.75 10.9 2.9 4.6 5.3 2.6 2.6 3.85 0.870 0.866 0.695 0.679 0.406 0.104 0.165 0.177 0.075 0.075 0.144 0.050 0.700 0.689 0.421 0.169 0.200 0.022 0.030 0.055 0.705 0.795 0.890 0.886 0.713 0.699 0.429 0.114 0.181 0.209 0.102 0.102 0.152 PMMUL15V.EPS A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia. 1 Min. MUL15V.TBL Dimensions 20/21 L296 - L296P Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 21/21 L4960 2.5A POWER SWITCHING REGULATOR 2.5A OUTPUT CURRENT 5.1V TO 40V OPUTPUT VOLTAGE RANGE PRECISE ( 2%) ON-CHIP REFERENCE HIGH SWITCHING FREQUENCY VERY HIGH EFFICIENCY (UP TO 90%) VERY FEW EXTERNAL COMPONENTS SOFT START INTERNAL LIMITING CURRENT THERMAL SHUTDOWN DESCRIPTION The L4960 is a monolithic power switching regulator delivering 2.5A at a voltage variable from 5V to 40V in step down configuration. Features of the device include current limiting, soft start, thermal protection and 0 to 100% duty cycle for continuous operation mode. HEPTAWATT ORDERING NUMBERS: L4960 (Vertical) L4960H (Horizontal) The L4960is mounted in a Heptawatt plastic power package and requires very few external components. Efficient operation at switching frequencies up to 150KHz allows a reduction in the size and cost of external filter components. BLOCK DIAGRAM April 1995 1/15 L4960 PIN CONNECTION (Top view) ABSOLUTE MAXIMUM RATINGS Symbol V1 V1 - V7 V7 V3 , V6 V2 I3 I5 Ptot Tj, Tstg Parameter Input voltage Input to output voltage difference Negative output DC voltage Negative output peak voltage at t = 0.1s; f = 100KHz Voltage at pin 3 and 6 Voltage at pin 2 Pin 3 sink current Pin 5 source current Power dissipation at Tcase 90C Junction and storage temperature Value 50 50 -1 -5 5.5 7 1 20 15 -40 to 150 Unit V V V V V V mA mA W C PIN FUNCTIONS FUNCTION N NAME 1 SUPPLY VOLTAGE Unregulated voltage input. An internal regulator powers the internal logic. 2 FEEDBACK INPUT The feedback terminal of the regulation loop. The output is connected directly to this terminal for 5.1V operation; it is connected via a divider for higher voltages. 3 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 4 GROUND Common ground terminal. 5 OSCILLATOR A parallel RC network connected to this terminal determines the switching frequency. 6 SOFT START Soft start time constant. A capacitor is connected between this terminal and ground to define the soft start time constant. This capacitor also determines the average short circuit output current. 7 OUTPUT Regulator output. 2/15 L4960 THERMAL DATA Symbol Parameter Value Unit R th j-case Thermal resistance junction-case max 4 C/W R th j-amb Thermal resistance junction-ambient max 50 C/W ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T j = 25 C, Vi = 35V, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit Vref 40 V 9 46 V DYNAMIC CHARACTERISTICS Vo Output voltage range Vi = 46V Io = 1A Vi Input voltage range Vo = Vref to 36V Io = 2.5A Vo Line regulation Vi = 10V to 40V Vo Load regulation Vref Vref T Io = 1A 15 50 mV Vo = Vref Io = 0.5A to 2A 10 30 mV Internal reference voltage (pin 2) Vi = 9V to 46V Io = 1A 5.1 5.2 V Average temperature coefficient of refer voltage Tj = 0C to 125C Io = 1A 0.4 Vd Dropout voltage Io = 2A 1.4 Iom Maximum operating load current Vi = 9V to 46V Vo = Vref to 36V I7L Current limiting threshold (pin 7) Vi = 9V to 46V Vo = Vref to 36V ISH Input average current Vi = 46V; Efficiency SVR Supply voltage ripple rejection Vo = Vref 5 mV/C 3 2.5 V A 3 4.5 A 60 mA output short-circuit 30 f = 100KHz Vo = Vref 75 % Io = 2A Vo = 12V 85 % 50 56 dB 85 100 Vi = 2Vrms fripple = 100Hz Vo = Vref f Switching frequency f Vi Voltage stability of switching frequency Vi = 9V to 46V f Tj Temperature stability of switching frequency Tj = 0C to 125C fmax Maximum operating switching frequency Vo = Vref Tsd Thermal shutdown junction temperature Io = 1A Io = 2A 120 115 KHz 0.5 % 1 % 150 KHz 150 C 3/15 L4960 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 30 40 mA 15 20 mA 1 mA DC CHARACTERISTICS I1Q Quiescent drain current 100% duty cycle pins 5 and 7 open Vi = 46V 0% duty cycle -I7L Output leakage current 0% duty cycle SOFT START I6SO Source current 100 140 180 A I6SI Sink current 50 70 120 A ERROR AMPLIFIER 3.5 V V3H High level output voltage V2 = 4.7V I3 = 100A V3L Low level output voltage V2 = 5.3V I3 = 100A I3SI Sink output current V2 = 5.3V 100 150 A Source output current V2 = 4.7V 100 150 A I2 Input bias current V2 = 5.2V Gv DC open loop gain V3 = 1V to 3V -I3SO 0.5 2 46 55 10 V A dB OSCILLATOR -I5 4/15 Oscillator source current 5 mA L4960 CIRCUIT OPERATION (refer to the block diagram) The L4960 is a monolithic stepdown switching regulator providing output voltages from 5.1V to 40V and delivering 2.5A. The regulation loop consists of a sawtooth oscillator, error amplifier, comparator and the output stage. An error signal is produced by comparing the output voltage with a precise 5.1V on-chip reference (zener zap trimmed to 2%). This error signal isthen compared with the sawtooth signal to generate the fixed frequency pulse width modulated pulses which drive the output stage. The gain and frequency stability of the loop can be adjusted by an external RC network connected to pin 3. Closing the loop directly gives an output voltage of 5.1V. Higher voltages are obtained by inserting a voltage divider. Output overcurrents at switch on are prevented by the soft start function. The error amplifier output is initially clamped by the external capacitor Css and allowed to rise, linearly, as this capacitor is charged by a constant current source. Output overload protection is provided in the form of a current limiter. The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold this comparator sets a flip flop which disables the output stage and discharges the soft start capacitor. A second comparator resets the flip flop when the voltage across the soft start capacitor has fallen to 0.4V. The output stage is thus re-enabled and the output voltage rises under control of the soft start network. If the overload condition is still present the limiter will trigger again when the threshold current is reached. The average short circuit current is limited to a safe value by the dead time introduced by the soft start network. The thermal overload circuit disables circuit operation when the junction temperature reaches about 150C and has hysteresis to prevent unstable conditions. Figure 1. Soft start waveforms Figure 2. Current limiter waveforms 5/15 L4960 Figure 3. Test and application circuit C6, C7: EKR (ROE) L1 = 150H at 5A (COGEMA 946042) CORE TYPE: MAGNETICS 58206-A2 MPP N TURNS 45, WIRE GAUGE: 0.8mm (20 AWG) Figure 4. Quiescent drain current vs. supply voltage (0% duty cycle) 6/15 Figure 5. Quiescent drain current vs. supply voltage (100% duty cycle) Figure 6. Quiescent drain current vs. j unction temperature (0% duty cycle) L4960 Figure 7. Quiescent drain current vs . junction temperature (100% duty cycle) Figure 8. Reference voltage (pin 2) vs. Vi Figure 9. Reference voltage versus junction temperature (pin 2) Figure 10. Open loop frequency and phase responde of error amplifier Fig ure 11. Switc hing frequency vs. input voltage Figur e 12 . Sw itching frequency vs. j unc tion te mperature Fi gur e 13 . Switching frequency vs. R2 (see test circuit) Fig ure 1 4. Line transie nt response Fig ure 15. Load transient response 7/15 L4960 Figure 16. Supply voltage ripple rejection vs. frequency Figure 17. Dropout voltage between pin 1 and pin 7 vs. current at pin 7 Figure 18. Dropout voltage be twe e n pi n 1 a nd 7 vs . junction temperature Figure 19. Power dissipation derating curve Fi gur e 2 0. E ffi ci enc y vs. output current Fi gu re 2 1. E ffic ien cy vs . output current Fi gur e 2 2. Effi ci en cy vs. output current 8/15 Fi gur e 2 3 . Effi ci ency vs. output voltage L4960 APPLICATION INFORMATION Figure 24. Typical application circuit C1, C6, C7: EKR (ROE) D1: BYW80 OR 5A SCHOTTKY DIODE SUGGESTED INDUCTOR: L 1 = 150H at 5A CORE TYPE: MAGNETICS 58206 - A2 - MPP N TURNS: 45, WIRE GAUGE: 0.8mm (20 AWG), COGEMA 946042 U15/GUP15: N TURNS: 60, WIRE GAUGE: 0.8mm (20 AWG), AIR GAP: 1mm, COGEMA 969051. Figure 25. P.C. board and component layout of the Fig. 24 (1 : 1 scale) Resistor values for standard output voltages Vo R3 R4 12V 15V 18V 24V 4.7K 4.7K 4.7K 4.7K 6.2K 9.1K 12K 18K 9/15 L4960 APPLICATION INFORMATION Figure 26. A minimal 5.1V fixed regulator; Very few component are required * COGEMA 946042 969051 ** EKR (ROE) (TOROID CORE) (U15 CORE) Figure 27. Programmable power supply Vo = 5.1V to 15V Io = 2.5A max Load regulation (1A to 2A) = 10mV (Vo = 5.1V) 10/15 L4960 APPLICATION INFORMATION (continued) Figure 28. Microcomputer supply with + 5.1V, -5V, +12V and -12V outputs 11/15 L4960 APPLICATION INFORMATION (continued) Figure 29. DC-DC converter 5.1V/4A, 12V/2.5A; a suggestion how to synchronize a negative output L1, L3 = COGEMA 946042 (969051) L2 = COGEMA 946044 (946045) D1, D2, D3 = BYW80 Figure 30. - In multiple supplies several L4960s can be synchronized as shown 12/15 L4960 APPLICATION INFORMATION (continued) Figure 31. Regulator for distributed supplies MOUNTING INSTRUCTION The power dissipatedin the circuit must be removed by adding an external heatsink. Thanks to the Heptawatt package attaching the hetsink is very simple, a screw or a compression spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon grease, to optimize the thermal contact, no electrical isolation is needed between the two surfaces. Figure 32. Mounting example 13/15 L4960 HEPTAWATT PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 4.8 0.189 C 1.37 0.054 D 2.4 2.8 0.094 0.110 D1 1.2 1.35 0.047 0.053 E 0.35 0.55 0.014 0.022 F 0.6 0.8 0.024 F1 0.031 0.9 0.035 G 2.41 2.54 2.67 0.095 0.100 0.105 G1 4.91 5.08 5.21 0.193 0.200 0.205 G2 7.49 7.62 7.8 0.295 0.300 0.307 H2 H3 10.4 10.05 10.4 0.409 0.396 0.409 L 16.97 0.668 L1 14.92 0.587 L2 21.54 0.848 L3 22.62 0.891 L5 2.6 3 0.102 0.118 L6 15.1 15.8 0.594 0.622 L7 6 6.6 0.236 0.260 M 2.8 0.110 M1 5.08 0.200 Dia 14/15 inch 3.65 3.85 0.144 0.152 L4960 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 15/15 L4962 1.5A POWER SWITCHING REGULATOR 1.5A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE PRECISE ( 2%) ON-CHIP REFERENCE HIGH SWITCHING FREQUENCY VERY HIGH EFFICIENCY (UP TO 90%) VERY FEW EXTERNAL COMPONENTS SOFT START INTERNAL LIMITING CURRENT THERMAL SHUTDOWN DESCRIPTION The L4962 is a monolithic power switching regulator delivering 1.5A at a voltage variable from 5V to 40V in step down configuration. Features of the device include current limiting, soft start, thermal protection and 0 to 100% duty cycle for continuous operating mode. POWERDIP (12 + 2 + 2) HEPTAWATT ORDERING NUMBERS : L4962/A (12 + 2 + 2 Powerdip) L4962E/A (Heptawatt) L4962EH/A (Horizontal Heptawatt) The L4962is mountedin a 16-lead Powerdip plastic package and Heptawatt package and requires very few external components. Efficient operation at switching frequencies up to 150KHz allows a reduction in the size and cost of external filter components. BLOCK DIAGRAM Pin X = Powerdip Pin (X) = Heptawatt March 1996 1/15 L4962 ABSOLUTE MAXIMUM RATINGS Symbol V7 V7 - V2 V2 V11, V15 Parameter Value Unit Input voltage 50 V Input to output voltage difference 50 V Negative output DC voltage -1 V Output peak voltage at t = 0.1s; f = 100KHz -5 V Voltage at pin 11, 15 5.5 V V10 Voltage at pin 10 7 V I11 Pin 11 sink current 1 mA I14 Pin 14 source current 20 mA Ptot Power dissipation at Tpins 90C (Powerdip) Tcase 90C (Heptawatt) 4.3 15 W W -40 to 150 C Tj, Tstg Junction and storage temperature PIN CONNECTION (Top view) THERMAL DATA Symbol Rth j-case Rth j-pins Rth j-amb Parameter Thermal resistance junction-case Thermal resistance junction-pins Thermal resistance junction-ambient max max max Heptawatt Powerdip 4C/W 50C/W 14C/W 80C/W* * Obtained with the GND pins soldered to printed circuit with minimized copper area. PIN FUNCTIONS HEPTAWATT POWERDIP NAME FUNCTION 1 7 SUPPLY VOLTAGE Unregulated voltage input. An internal regulator powers the internal logic. 2 10 FEEDBACK INPUT The feedback terminal of the regulation loop. The output is connected directly to this terminal for 5.1V operation; it is connected via a divider for higher voltages. 3 11 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 2/15 L4962 PIN FUNCTIONS (cont'd) HEPTAWATT POWERDIP 4 4, 5, 12, 13 5 FUNCTION NAME GROUND Common ground terminal. 14 OSCILLATOR A parallel RC network connected to this terminal determines the switching frequency. This pin must be connected to pin 7 input when the internal oscillator is used. 6 15 SOFT START Soft start time constant. A capacitor is connected between this terminal and ground to define the soft start time constant. This capacitor also determines the average short circuit output current. 7 2 OUTPUT Regulator output. 1, 3, 6, 8, 9, 16 N.C. ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25 C, Vi = 35V, unless otherwise specified) Symbol Parameter Test Condition s Min. Typ. Max. Unit Vref 40 V 9 46 V 15 50 mV 8 20 mV 5.1 5.2 V DYNAMIC CHARACTERISTICS Vo Output voltage range Vi = 46V Io = 1A Vi Input voltage range Vo = Vref to 36V Io = 1.5A Vo Line regulation Vi = 10V to 40V Vo Load regulation Vo = Vref Io = 0.5A to 1.5A Vref Internal reference voltage (pin 10) Vi = 9V to 46V Io = 1A Vref T Average temperature coefficient of refer. voltage Tj = 0C to 125C Io = 1A 0.4 Vd Dropout voltage Io = 1.5A 1.5 Iom Maximum operating load current Vi = 9V to 46V Vo = Vref to 36V 1.5 I2L Current limiting threshold (pin 2) Vi = 9V to 46V Vo = Vref to 36V 2 ISH Input average current Vi = 46V; Efficiency SVR Supply voltage ripple rejection Vo = Vref Io = 1A 5 mV/C 2 V A 3.3 A 30 mA output short-circuit 15 f = 100KHz Vo = Vref 70 % Io = 1A Vo = 12V 80 % 56 dB Vi = 2Vrms fripple = 100Hz Vo = Vref 50 Io = 1A 3/15 L4962 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 85 100 115 KHz DYNAMIC CHARACTERISTICS (cont'd) f Switching frequency f Vi Voltage stability of switching frequency Vi = 9V to 46V f Tj Temperature stability of switching frequency Tj = 0C to 125C fmax Maximum operating switching frequency Vo = Vref Tsd Thermal shutdown junction temperature Io = 1A 120 0.5 % 1 % 150 KHz 150 C DC CHARACTERISTICS I7Q Quiescent drain current 100% duty cycle pins 2 and 14 open 30 40 mA 15 20 mA 1 mA Vi = 46V 0% duty cycle -I2L Output leakage current 0% duty cycle SOFT START I15SO Source current 100 140 180 A I15SI Sink current 50 70 120 A ERROR AMPLIFIER V11H High level output voltage V10 = 4.7V I11 = 100A V11L Low level output voltage V10 = 5.3V I11 = 100A I11SI Sink output current V10 = 5.3V 100 150 A Source output current V10 = 4.7V 100 150 A I10 Input bias current V10 = 5.2V Gv DC open loop gain V11 = 1V to 3V -I11SO 3.5 V 0.5 2 46 55 10 V A dB OSCILLATOR -I14 4/15 Oscillator source current 5 mA L4962 CIRCUIT OPERATION (refer to the block diagram) The L4962 isa monolithic stepdownswitching regulator providing output voltages from 5.1V to 40V and delivering 1.5A. The regulation loop consists of a sawtooth oscillator, error amplifier, comparator and the output stage. An error signal is producedby comparing the output voltage with a precise 5.1V on-chip reference (zener zap trimmed to 2%). This error signal is then comparedwith the sawtooth signal to generate the fixed frequency pulse width modulated pulses which drive the output stage. The gain and frequency stability of the loop can be adjusted by an external RC network connected to pin 11. Closing the loop directly gives an output voltage of 5.1V. Higher voltages are obtained by inserting a voltage divider. Output overcurrents at switch on are prevented by the soft start function. The error amplifier output is initially clamped by the external capacitor Css and allowed to rise, linearly, as this capacitor is charged by a constant current source. Output overload protection is provided in the form of a current limiter. The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold this comparator sets a flip flop which disables the output stage and discharges the soft start capacitor. A second comparator resets the flip flop when the voltage across the soft start capacitor has fallen to 0.4V. The output stage is thus re-enabled and the output voltage rises under control of the soft start network. If the overload condition is still present the limiter will trigger again when the threshold current is reached. The average short circuit current is limited to a safe value by the dead time introduced by the soft start network. The thermal overload circuit disables circuit operation when the junction temperature reaches about 150C and has hysteresis to prevent unstable conditions. Figure 1. Soft start waveforms Figure 2. Current limiter waveforms 5/15 L4962 Figure 3. Test and application circuit (Powerdip) 1) D 1: BYW98 or 3A Schottky diode, 45V of VRRM; 2) L1: CORE TYPE - MAGNETICS 58120 - A2 MPP N TURNS 45, WIRE GAUGE: 0.8mm (20 AWG) 3) C 6, C7: ROE, EKR 220F 40V Figure 4. Quiescent drain current vs. supply voltage (0% duty cycle) 6/15 Figure 5. Quiescent drain current vs. supply voltage (100% duty cycle) Figure 6. Quiescent drain curr ent vs . junction temperature (0% duty cycle) L4962 Figure 7. Quiescent drain cur rent vs. ju nc tion temperature (100% duty cycle) Figure 8. Reference voltage (pin 10) vs. Vi rdip) vs. Vi Figure 9. Reference voltage (pin 10 ) vs. junction temperature Figure 10. Open loop frequency and phase re- sponse of error amplifier Fi gure 11. Sw itchi ng frequency vs. input voltage Fi gure 1 2. Switchi ng freque nc y vs. ju ncti on temperature Figure 1 3. Switching frequency vs. R2 (see test circuit) Fi gure 1 4. L ine tr an si ent response Figure 15 . Load transient response 7/15 L4962 Figure 16. Supply voltage ripple rejection vs. frequency Figure 17. Dropout voltage between pin 7 and pin 2 vs. current at pin 2 Figure 18. Dropout voltage b etwe en pi n 7 a nd 2 v s. junction temperature Fi gu re 1 9. Effi c ien cy vs. output current Fi g ure 2 0. Effi ci ency v s. output current F ig ur e 2 1. Effic i en cy vs. output current Fi gur e 2 2 . Effi ci enc y vs. output voltage Fi g ure 2 3. Effi ci ency v s. output voltage Figure 24. Maximum allowable power dissipation vs. ambient temperature (Powerdip) 8/15 L4962 APPLICATION INFORMATION Figure 25. Typical application circuit C1, C6, C7: EKR (ROE) D1: BYW98 OR VISK340 (SCHOTTKY) SUGGESTED INDUCTORS: (L1) = MAGNETICS 58120 - A2MPP - 45 TURNS - WIRE GAUGE 0.8mm (20AWG) COGEMA 946043 OR U15, GUP15, 60 TURNS 1mm, AIR GAP 0.8mm (20 AWG) - COGEMA 969051. Figure 26. P.C. board and component layout of the circuit of Fig. 25 (1 : 1 scale) Resistor values for standard output 7 voltages Vo R3 R4 12V 15V 18V 24V 4.7K 4.7K 4.7K 4.7K 6.2K 9.1K 12K 18K 9/15 L4962 APPLICATION INFORMATION (continued) Figure 27. - A minimal 5.1V fixed regulator; Very few component are required * COGEMA 946043 969051 ** EKR (ROE) (TOROID CORE) (U15 CORE) Figure 28. Programmable power supply Vo = 5.1V to 15V Io = 1.5A max Load regulation (0.5A to 1.5A) = 10mV (Vo = 5.1V) Line regulation (220V 15% and to Io = 1A) = 15mV (Vo = 5.1V) 10/15 L4962 APPLICATION INFORMATION (continued) Figure 29. DC-DC converter 5.1V/4A, 12V/1A. A suggestion how to synchronize a negative output L1, L3 = COGEMA 946043 (969051) L2 = COGEMA 946044 (946045) Figure 30. In multiple supplies several L4962s can be synchronized as shown Figure 31. Preregulator for distributed supplies * L2 and C2 are necessary to reduce the switching frequency spikes when linear regulators are remote from L4962 11/15 L4962 MOUNTING INSTRUCTION The Rth-j-amb of the L4962 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 32). The diagram of figure 33 shows the Rth-j-amb as a function of the side "l" of two equal square copper areas having the thickness of 35 (1.4 mils). During soldering the pins temperature must not exceed 260C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper are must be connected to electrical ground. Figure 32. Example of P.C. board copper area which is used as heatsink 12/15 Figure 33. Maximum dissipable power and junction to ambient thermal resistance vs. side "l" L4962 POWERDIP PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.020 0.50 D 0.055 0.015 0.020 20.0 0.787 E 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 L Z 3.30 0.130 1.27 0.050 13/15 L4962 HEPTAWATT PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A TYP. MAX. 0.189 1.37 0.054 2.4 2.8 0.094 0.110 D1 1.2 1.35 0.047 0.053 E 0.35 0.55 0.014 0.022 F 0.6 0.8 0.024 0.031 F1 0.9 0.035 G 2.41 2.54 2.67 0.095 0.100 0.105 G1 4.91 5.08 5.21 0.193 0.200 0.205 G2 7.49 7.62 7.8 0.295 0.300 H2 H3 10.4 10.05 10.4 0.396 0.409 L 16.97 0.668 14.92 0.587 L2 21.54 0.848 22.62 0.891 L5 2.6 3 L6 15.1 L7 6 M 0.102 0.118 15.8 0.594 0.622 6.6 0.236 2.8 M1 Dia 0.260 0.110 5.08 3.65 0.307 0.409 L1 L3 14/15 MIN. 4.8 C D inch MAX. 0.200 3.85 0.144 0.152 L4962 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Swit zerland - Taiwan - Thaliand - United Kingdom - U.S.A. 15/15 L4963 L4963D 1.5A SWITCHING REGULATOR 1.5A OUTPUT LOAD CURRENT 5.1 TO 36V OUTPUT VOLTAGE RANGE DISCONTINUOUS VARIABLE FREQUENCY MODE PRECISE (+/-2%) ON CHIP REFERENCE VERY HIGH EFFICIENCY VERY FEW EXTERNAL COMPONENTS NO FREQ. COMPENSATION REQUIRED RESET AND POWER FAIL OUTPUT FOR MICROPROCESSOR INTERNAL CURRENT LIMITING THERMAL SHUTDOWN Powerdip12+3+3 SO20 ORDERING NUMBERS: DESCRIPTION The L4963 is a monolithic power switching regulator delivering 1.5A at 5.1V. The output voltage is adjustable from 5.1V to 36V, working in discontinuous variable frequency mode. Features of the device include remote inhibit, internal current limiting and thermal protection, reset and power fail outputs for microprocessor. L4963W L4963D The L4963 is mounted in a 12+3+3 lead Powerdip (L4963) and SO20 large (L4963D) plastic packages and requires very few external components. BLOCK DIAGRAM October 1991 This is advanced information on a new product now in development or underogin evaluation. Details are subject to change without notice. 1/17 L4963 - L4963D ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Input Voltage (pin 1 and pin 3 connected togheter) 47 V Input to Output Voltage Difference 47 V V2 Negative Output DC Voltage -1 V V2 Negative Output Peak Voltage at t=0.2 s, f=50kHz -5 V Power Fail Input 25 V Reset and Power Fail Output Vi Reset Delay Input 5.5 V 7 V SO20 Parameter Powerdip Vi V3-V2 V8 V7 V9, V11 V8, V10 V10 V9 V13, V18 V12, V16 Feedback and Inhibit Inputs V19, V20 V17, V18 Oscillator Inputs 5.5 V Total Power Dissipation Tpins 90C (Power DIP) (Tamb = 70C no copper area on PCB) 2 (Tamb = 70C, 4cm copper area on PCB) 5 1.3 2 W W W -40 to 150 1.45 C W 4 W Ptot Tstg, Tj Ptot Storage & Junction Temperature 2 (Tamb = 70C 6cm copper area on PCB) Total Power Dissipation Tpins 90C (SO20L) PIN CONNECTION (top view) Powerdip18 SO20 2/17 L4963 - L4963D PIN FUNCTIONS SO20L Power DIP Name Description 1 1 SIGNAL SUPPLY VOLTAGE Must be Connected to pin 3 2 2 OUTPUT Regulator output 3 3 SUPPLY VOLTAGE Unregulated voltage input. An internal regulator powers the internal logic. 4, 5, 6, 7 14, 15, 16, 17 4, 5, 6 13, 14, 15 GROUND Common ground terminal 8 7 POWER FAIL INPUT Input of the power fail circuit. The threshold can be modified introducing an external voltage divider between the Supply Voltage and GND. 9 8 POWER FAIL OUTPUT Open collector power fail signal output. This output is high when the supply voltage is safe. 10 9 RESET DELAY A capacitor connected between this terminal and ground determines the reset signal delay time. 11 10 RESET OUTPUT Open collector reset signal output. This output is high when the output voltage value is correct. 12 11 REFERENCE VOLTAGE Reference voltage output. 13 12 FEEDBACK INPUT Feedback terminal of the regulation loop. The output is connected directly to this terminal for 5.1V operation; it is connected via a divider for higher voltages. 18 16 INHIBIT INPUT TTL level remote inhibit. A logic low level on this input disables the device. 19 17 C OSCILLATOR Oscillator waveform. A capacitor connected between this terminal and ground modifies the maximum oscillator frequency. 20 18 R OSCILLATOR FREQ. A resistor connected between this terminal and ground defines the maximum switching frequency. THERMAL DATA Symbol Parameter SO20 Powerdip Unit Rth j-pins Thermal Resistance Junction to Pins max. 15 12 C/W Rth j-amb Thermal Resistance Junction to Ambient (*) max. 85 80 C/W (*) See Fig. 28 3/17 L4963 - L4963D CIRCUIT DESCRIPTION (Refer to Block Diagram) The L4963 is a monolithic stepdown regulator providing 1.5A at 5.1V working in discontinuous variable frequency mode. In normal operation the device resonates at a frequency depending primarily on the inductance value, the input and output voltage and the load current. The maximum switching however can be limited by an internal oscillator, which can be programmed by only one external resistor. The fondamental regulation loop consists of two comparators, a precision 5.1V on-chip reference and a drive latch. Briefly the operation is as follows: when the choke ends its discharge the catch freewheeling recirculation filter diode begins to come out of forward conduction so the output voltage of the device approaches ground. When the output voltage reaches -0.1V the internal comparator sets the latch and the power stage is turned on. Then the inductor current rises linearly until the voltage sensed at the feedback input reaches the 5.1V reference. The second comparator then resets the latch and the output stage is turned off. The current in the choke falls linearly until it is fully discharged, then the cycle repeats. Closing the loop directly gives an output voltage of 5.1V. Higher output voltages are Figure 1: Reset and Power Fail Function 4/17 obtained by inserting a voltage divider and this method of control requires no frequency compensation network. At output voltages greater than 5.1V the available output current must be derated due to the increased power dissipation of the device. Output overload protection is provided by an internal current limiter. The load current is sensed by a on-chip metal resistor connected to a comparator which resets the latch and turns off the power stage in overload condition. The reset circuits (see fig. 1) generates an output high signal when the output voltage value is correct. It has an open collector output and the output signal delay time can be programmed with an external capacitor. A powerfail circuit is also available and is used to monitor the supply voltage. Its output goes high when the supply voltage reaches a pre-programmed treshold set by a voltage divider to its input from the supply to ground. With the input left open the threshold is approximately equal to 5.1V. The output of the power fail is an open collector. A TTL level inhibit is provided for applications such as remote on/off control. This input is activated by a low logic level and disables circuits operation. The thermal overload circuit disables the device when the junction temperature is about 150C and has hysteresis to prevent unstable conditions. L4963 - L4963D ELECTRICAL CHARACTERISTIC (Refer to the test circuit Vi = 30V Tj = 25C unless otherwise specified ) Symbol Parameter Test Condition s Min. Typ. Max. Unit Fig. Vref 36 V 2 46 V 2 5.1 5.2 V 2 5 20 A 3a 5 10 mV 3a DYNAMIC CHARACTERISTICS Vo Output Voltage Range Vi = 46V Io = 0.5A Vi Input Voltage Range Vo = Vref to 36V Io = 0.5A 9 V12 Feedback Voltage Vi = 9 to 46V Io = 0.5A 5 I12 Input Bias Current Vi = 15V V12 = 6V V17f = 5V VOS12 Input Offset Voltage Vo Line Regulation Vi = 9 to 46V Vo = Vref Io = 0.5A 15 50 mV 2 Vo Load Regulation Vo = Vref Io = 0.5 to 1.5A 15 45 mV 2 Vd Dropout Voltage Between pin 3 and pin 2 I2 = 3A Vi = 20V 1.5 2 V 2 I2L Current Limiting Vi = 9 to 46V Vo = Vref to 28V 3.5 6.5 A 2 Io Maximum Operating Load Current Vi = 9 to 46V Vo = Vref 1.5 A 2 Supply Voltage Ripple Rejection Vi = 2Vrms Vo = Vref fripple = 100Hz Io = 1.5A 50 56 dB 2 Reference Voltage Vi = 9 to 46V O < I11 < 5mA 5 5.1 V 3a Average Temperature Coefficient of Ref. Volt. Tj = 0 to 125 C 0.4 mV/C - V11 Vref Line Regulation Vi = 9 to 46V 10 20 mV 3a V11 Vref Line Regulation Iref = 0 to 5mA Vi = 46V Rosc = 51K 65 69 7 15 mV 3a Efficiency Io = 1.5A V o = Vref 65 75 % 2 145 150 C - 30 C - SVR V11 Tsd Thermal Shutdown Junction Temperature Hysteresis 5.2 DC CHARACTERISTICS Iq Quescent Drain Current Vi = 46V Io = 0mA V16 = V12 = 0 14 20 mA 3a V16 = Vref V12 = 5.3V 11 16 mA 3a INHIBIT V16L Low Input Voltage Vi = 9 to 46V 0.3 0.8 V 2 V16H High Input Voltage Vi = 9 to 46V 2 5.5 V 2 I16L Input Current with Low Input Voltage V16 = 0.8V 50 100 A 2 I16L Input Current with High Input Voltage V16 = 2V 10 20 A 2 5/17 L4963 - L4963D ELECTRICAL CHARACTERISTIC (Continued) Symbol Parameter Test Condition s Min. Typ. Max. Unit Fig. RESET V12 Rising Threshold Voltage Vi = 9 to 46V Vref -150 Vref -100 Vref -50 mV 3b V12 Falling Threshold Voltage Vi = 9 to 46V Vref -150 Vref -200 Vref -250 mV 3b V9D Delay Rising Thereshold Voltage V7 = OPEN 4.3 4.5 4.7 V 3b V9F Delay Falling Thereshold Voltage 1 1.5 2 V 3b 110 140 A 3b Delay Source Current V9 = 4.7V V12 = 5.3V 70 I9SI Delay Sink Current V9 = 4.7V V12 = 4.7V 10 mA 3b I10 Output Leakage Current Vi = 46V V7 = 8.5V 50 A 3b V10 Output Saturation Volt. I10 = 15mA; VI = 3 to 46V 0.4 V 3b -I9SO POWER FAIL VR Rising Threshold Voltage Pin7 = open 17.5 19 20.5 V 3C VF Falling Threshold Voltage Pin7 = open 14.25 15 15.75 V 3c V7 Rising Threshold Voltage Vi = 20V 4.14 4.5 4.86 V - V7 Falling Threshold Voltage Vi = 20V 3.325 3.5 3.675 V - Vs Output Saturation Volt. Ia = 5mA 0.4 V 3c Is Output Leakage Current Vi = 46V 50 A 3c 79 kHz - 83 kHz - OSCILLATOR 6/17 f Oscillator Frequency RT = 51K 46 f Oscillator Frequency VI = 9 to 46V Tj = 0 to 125C RT = 51K 42 60 L4963 - L4963D Figure 2: Test Circuit Figure 3: DC Test Circuit Figure 3a Figure 3b 7/17 L4963 - L4963D Figure 3c Figure 4: Quiescent Drain Current vs. Supply Voltage (0% Duty Cycle) Figure 5: Quiescent Drain Current vs. Supply Voltage (100% Duty Cycle) Figure 6: Quiescent Drain Current vs. Junction Temperature (0% Duty Cycle) Figure 7: Quiescent Drain Current vs. Junction Temperature (100% Duty Cycle) 8/17 L4963 - L4963D Figure 8: Reference Voltage vs. Vi Figure 9: Reference Voltage vs. Tj Figure 10: Line Transient Response Figure 11: Load Transient Figure 12: Supply Voltage Ripple Rejection vs. Frequency Figure 13: Dropout Voltage Between pi3 and 2 vs. Current at pin2 9/17 L4963 - L4963D Figure 14: Dropout Voltage Between pin3 and 2 vs. Junction Temperature Figure 15: Maximum Allowable PowerDissipation vs. Ambient Temperature (Powerdip Package Only) Figure 16: Power Dissipation (device only) vs. Input Voltage (Powerdip Package Only) Figure 17: Power Dissipation (device only) vs. Output Voltage (Powerdip Package Only) Figure 18: Voltage and Current Waveform at pin2 Figure 19: Efficiency vs. Output Current (Powerdip Package Only) 10/17 L4963 - L4963D Figure 20: Efficiency vs. Output Voltage (Powerdip Package Only) Figure 21: Current Limit vs. Junction Temperature Vi = 30V Figure 22: Current Limit vs. Input Voltage Figure 23: Oscillator Frequency vs. R2 (see fig. 26) Figure 24: Oscillator Frequency vs. Junction Temperature Figure 25: Oscillator Frequency vs. Input Voltage 11/17 L4963 - L4963D Figure 26: Evaluation Board Circuit PART LIST CAPACITOR Resistor Values for Standard Output Voltages C1 1000F 50V EKR (*) VO R6 R5 C2 2.2mF 16V 12 4.7K 6.2K C3 1000F 40V with low ESR 15 4.7K 9.1KW C4 1F 50V film 18 4.7K 12KW 24 4.7K 18KW RESISTOR R1 1K R2 51K R3 1K R4 1K R5, R6 Diode: BYW98 Core: L = 40H Magnetics58121-A2MPP34 Turns 0.9mm (20AWG) see table (*) Minimum 100F if Vi is a preregulated offline SMPS output or 1000F if a 50Hz transformer plus rectifiers is used. 12/17 L4963 - L4963D Figure 27: P.C. Board and Component Layout of the Circuit of fig. 26 (Powerdip Package) (1:1 scale). Figure 28: Thermal Characteristics Figure 29: Junction to Ambient Thermal Resistance vs. Area on Board Heatsink (SO20) 13/17 L4963 - L4963D Figure 30: A Minimal 5.1 Fixed Regulator -- Very Few Components are Required Figure 31: A Minimal Components count for VO = 12V 14/17 L4963 - L4963D POWERDIP18 PACKAGE MECHANICAL DATA mm inch DIM. MIN. a1 0.51 B 0.85 b b1 TYP. MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.020 0.50 D 0.055 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 20.32 0.800 F 7.10 0.280 I 5.10 0.201 L Z 3.30 0.130 2.54 0.100 15/17 L4963 - L4963D SO20 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. TYP. 2.65 0.1 MAX. 0.104 0.3 a2 0.004 0.012 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 (typ.) D 12.6 13.0 0.496 0.512 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M S 16/17 MIN. 0.75 0.030 8 (max.) L4963 - L4963D Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 17/17 L4970A 10A SWITCHING REGULATOR 10A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULATION INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS SOFT START INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 500KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4970A is a stepdown monolithic power switching regulator delivering 10A at a voltage variable from 5.1 to 40V. MULTIPOWER BCD TECHNOLOGY Multiwatt15V ORDERING NUMBER: L4970A Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of the L4970A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a 15-lead multiwatt plastic power package and requires few external components. Efficient operation at switching frequencies up to 500KHz allows reduction in the size and cost of external filter components. BLOCK DIAGRAM November 1991 1/21 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4970A ABSOLUTE MAXIMUM RATINGS Symbol Value Unit V9 Input Voltage Parameter 55 V V9 Input Operating Voltage 50 V V7 Output DC Voltage Output Peak Voltage at t = 0.1s f = 200KHz -1 -7 V V I7 Maximum Output Current V6 Bootstrap Voltage Bootstrap Operating Voltage V3, V12 Internally Limited 65 V9 + 15 V V V Input Voltage at Pins 3, 12 12 V4 Reset Output Voltage 50 V I4 Reset Output Sink Current 50 mA Input Voltage at Pin 5, 10, 11, 13 7 V mA V5, V10, V11, V13 I5 Reset Delay Sink Current 30 I10 Error Amplifier Output Sink Current 1 A I12 Soft Start Sink Current 30 mA Ptot Total Power Dissipation at Tcase < 120C Tj, Tstg Junction and Storage Temperature 30 W -40 to 150 C PIN CONNECTION (Top view) THERMAL DATA Symbol Rth j-case R th j-amb 2/21 Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient max max Value Unit 1 35 C/W C/W L4970A PIN FUNCTIONS o N Name Function 1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current of C osc. 2 OSCILLATOR Cosc. External capacitor connected to ground determines (with R osc) the switching frequency. 3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. 4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. 5 RESET DELAY A C d capacitor connected between this terminal and ground determines the reset signal delay time. 6 BOOTSTR AP A C boot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 7 OUTPUT Regulator Output. 8 GROUND Common Ground Terminal 9 SUPPLY VOLTAGE Unregulated Input Voltage. 10 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. 12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. 13 SYNC INPUT Multiple L4970A are synchronized by connecting pin 13 inputs together or via an external syncr. pulse. 14 Vref 5.1V Vref Device Reference Voltage. 15 Vstart Internal Start-up Circuit to Drive the Power Stage. CIRCUIT OPERATION (refer to the block diagram) The L4970A is a 10A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 10A at an output voltage adjustable from 5.1V to 40V, and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistor and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysteresis, this threshold provides a correct voltage for the driving stage of the DMOS gate and the hysteresis prevents instabilities. An external bootstrap capacitor charged to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 500kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator, in order to generate a fixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and 3/21 L4970A Figure 1: Feedforward Waveform Figure 2: Soft Start Function Figure 3: Limiting Current Function 4/21 L4970A stability of the loop can be adjusted by an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output voltage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on output overcurrents are prevented by the soft start function (fig. 2). The error amplifier is initially clamped by an external capacitor Css and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit (fig. 3). The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuitry (fig 4) generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by an external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V the reset output goes low immediately. The reset output is an open collector-drain. Fig 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig 4B shows the case when the output is 5.1V but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has an hysterysis to prevent unstable conditions. Figure 4: Reset and Power Fail Functions. A B 5/21 L4970A ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25C, Vi = 35V, R4 = 16K, C9 = 2.2nF, fSW = 200KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Test Condition Min. Vi input Voltage Range (pin 9) Vo = Vref to 40V Io = 10A 15 Vo Output Votage Vi = 15V to 50V Io = 5A; Vo = Vref 5 Vo Line Regulation Vi = 15V to 50V Io = 5A; Vo = Vref Vo Load Regulation Vo = Vref Io = 3A to 6A Io = 2A to 10A Typ. Max. Unit Fig. 50 V 5 5.1 5.2 V 5 12 30 mV 5 10 20 30 50 mV mV 0.55 1.1 0.8 1.6 V V 5 15 A 5 5 Vd Dropout Voltage Between Pin 9 and 7 Io = 5A Io = 10A I7L Max. Limiting Current Vi = 15 to 50V 11 13 Efficiency Io = 5A Vo = Vref Vo = 12V 80 85 92 % % Io = 10A Vo = Vref Vo = 12V 75 80 87 % % 56 60 dB 5 180 200 220 KHz 5 6 % 5 % 5 KHz 5 Unit Fig. SVR Supply Voltage Ripple Reject. f f Vi f Tj Switching Frequency fmax Vi = 2VRMS; Io = 5A f = 100Hz; Vo = Vref 5 5 Voltage Stability of Swiching Frequency Vi = 15V to 45V 2 Temperature Stability of Swiching Frequency T j = 0 to 125C 1 Maximum Operating Switching Frequency Vo = Vref; R4 = 10K Io = 10A; C9 = 1nF 500 Test Condition Min. Typ. Max. 5 5.1 5.2 V 7 10 25 mV 7 40 Vref SECTION (pin 14) Symbol Parameter V14 Reference Voltage V14 Line Regulation V14 V14 T I14 sho rt Vi = 15V to 50V Load Regulation I14 = 0 to 1mA 20 mV 7 Average Temperature Coefficient Reference Voltage T j = 0C to 125C 0.4 mV/C 7 Short Circuit Current Limit V14 = 0 70 mA 7 VSTART SECTION (pin 15) Symbol Parameter Test Condition Min. Typ. Max. Unit Fig. 11.4 12 12.6 V 7 1.4 V 7 200 mV 7 mA 7 V15 Reference Voltage V15 Line Regulation Vi = 15 to 50V 0.6 V15 Load Regulation I15 = 0 to 1mA 50 Short Circuit Current Limit V15 = 0V 80 I15 sho rt 6/21 L4970A ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS Symbol Parameter V9on Turn-on Threshold V9 Hyst Turn-off Hysteresys Test Condition Min. Typ. Max. Unit Fig. 10 11 12 V 7A V 7A I9Q Quiescent Current V12 = 0; S1 = D 13 19 mA 7A I9OQ Operating Supply Current V12 = 0; S1 = C; S2 = B 16 23 mA 7A Out Leak Current Vi = 55V; S3 = A; V12 = 0 2 mA 7A Fig. I7L 1 SOFT START Symbol Parameter Test Condition I12 Soft Start Source Current V12 = 3V; V11 = 0V V12 Output Saturation Voltage I12 = 20mA; V9 = 10V I12 = 200A; V9 = 10V Min. Typ. Max. Unit 70 100 130 A 7B 1 0.7 V V 7B 7B Max. Unit Fig. V 7C V 7C ERROR AMPLIFIER Symbol Parameter Test Condition Min. Typ. V10H High Level Out Voltage I10 = -100A; S1 = C V11 = 4.7V V10L Low Level Out Voltage I10 = +100A; S1 = C V11 = 5.3V; I10H Source Output Current V10 = 1V; S1 = E V11 = 4.7V 100 150 A 7C I10L Sink Output Current V10 = 6V; S1 = D V11 = 5.3V 100 150 A 7C I11 Input Bias Current R S = 10K GV DC Open Loop Gain VVCM = 4V; R S = 10 60 SVR Supply Voltage Rejection 15 < Vi < 50V; R S = 10 60 VOS Input Offset Voltage R S = 50 6 1.2 0.4 3 80 A - dB - dB - 2 10 mV - Min. Typ. Max. Unit Fig. 1.2 1.5 V 7A 2.5 5.5 V V 7A 7A RAMP GENERATOR (pin 2) Symbol Parameter Test Condition V2 Ramp Valley S1 = C; S2 = B V2 Ramp Peak S1 = C; S2 = B; I2 Min. Ramp Current S1 = A; I1 = 100A I2 Max. Ramp Current S1 = A; I1 = 1mA Vi = 15V Vi = 45V 270 2.4 2.7 Min. Typ. 300 A 7A mA 7A SYNC FUNCTION (pin 13) Symbol Max. Unit Fig. V13 Low Input Voltage Parameter Vi = 15V to 50V; V12 = 0; S1 = C; S2 = B; S4 = B Test Condition -0.3 0.9 V 7A V13 High Input voltage V12 = 0; S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A I13L Sync Input Current with Low Input Voltage V13 = V2 = 0.9V; S4 = A; S1 = C; S2 = B 0.4 mA 7A I13H Input Current with High Input Voltage V13 = 3.5V; S4 = A; S1 = C; S2 = B 1.5 mA 7A V13 Output Amplitude V - tW Output Pulse Width 0.8 s - Vthr = 2.5V 4 5 0.3 0.5 7/21 L4970A ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS Symbol Parameter Min. Typ. Max. Unit Fig. V11R Rising Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V Test Condition Vref -120 Vref -100 Vref -80 V mV 7D V11F Falling Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V 4.77 Vref -200 Vref -160 V mV 7D V5H Delay High Threshold Voltage Vi = 15 to 50V V14 = V11 V3 = 5.3V 4.95 5.1 5.25 V 7D V5L Delay Low Threshold Voltage Vi = 15 to 50V V14 = V11 V3 = 5.3V 1 1.1 1.2 V 7D -I5SO 60 80 Delay Source Current V3 = 5.3V; V5 = 3V 40 I5SI Delay Sink Current V3 = 4.7V; V5 = 3V 10 V4S Out Saturation Voltage I4 = 15mA; S1 = B V3 = 4.7V Output Leak Current V4 = 50V; S1 = A V3 = 5.3V V3R Rising Threshold Voltage V11 = V14 V3H Hysteresys I4 I3 7D 7D 0.4 V 7D 100 A 7D 4.95 5.1 5.25 V 7D 0.4 0.5 0.6 V 7D 1 3 A 7D Input Bias Current Figure 5: Test and Evaluation Board Circuit TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 10A ; fSW = 200KHz) Vo RIPPLE = 30mV (at 10A) with output filter capacitor ESR 60m Line regulation = 5mV (Vi = 15 to 50V) Load regulation = 15mV (Io = 2 to 10A) For component values, refer to test circuit part list. 8/21 A mA L4970A Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale). PARTS LIST Table A R1 = 30K C 1, C2 = 3300F 63VL EYF (ROE R2 = 10K C 3, C4, C5, C6 = 2.2F R3 = 15K C 7 = 390pF Film R4 = 16K C 8 = 22nF MKT 1817 (ERO) R5 = 22 0,5W R6 = 4K7 C 9 = 2.2nF KP1830 R7 = 10 C 10 = 220nF MKT R8 = see tab. A C 11 = 2.2nF MP1830 R9 = OPTION **C12 , C13, C14 = 220F 40VL EKR R10 = 4K7 C 15 = 1F Film V0 R9 R7 12V 15V 18V 24V 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k 12k 18k Table B SUGGESTED BOOTSTRAP CAPACITORS Operating Frequency Bootstrap Cap.c10 D1 = MBR 1560CT (or 16A/60V or equivalent) f = 20KHz 680nF L1 = 40H f = 50KHz 470nF f = 100KHz 330nF f = 200KHz 220nF f = 500KHz 100nF R11 = 10 core 58071 MAGNETICS 27 TURNS O 1,3mm (AWG 16) COGEMA 949178 * 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR 9/21 L4970A Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale) Figure 7: DC Test Circuits 10/21 L4970A Figure 7A Figure 7B 11/21 L4970A Figure 7D Figure 7C 12/21 L4970A Figure 8: Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9: Quiescent Drain Current vs. Junction Temperature (0% duty cycle). Figure 10: Quiescent Drain Current vs. Duty Cycle Figure 11: Reference Voltage (pin14) vs. Vi (see fig. 7) Figure 12: Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7) Figure 13: Reference Voltage (pin15) vs. Vi (see fig. 7) 13/21 L4970A Figure 14: Reference Voltage (pin 15) vs. Junction Temperature (see fig. 7) Figure 15: Reference Voltage 5.1V (pin 14) Supply Voltage Ripple Rejection vs. Frequency Figure 16: Switching Frequency vs. Input Voltage (see fig. 5) Figure 17: Switching Frequency vs. Junction Temperature (see fig 5) Figure 18: Switching Frequency vs. R4 (see fig. 5) Figure 19: Max. Duty Cycle vs. Frequency 14/21 L4970A Figure 20: Supply Voltage Ripple Rejection vs. Frequency (see fig. 5) Figure 21: Line Transient Response (see fig. 5) Figure 22: Load Transient Response (see fig. 5) Figure 23: Dropout Voltage Between Pin 9 and Pin 7 vs. Current at Pin 7 Figure 24: Dropout Voltage Between Pin 9 and Pin 7 vs. Junction Temperature Figure 25: Power Dissipation (device only) vs. Input Voltage 15/21 L4970A Figure 26: Power Dissipation (device only) vs. Output Voltage Figure 27: Heatsink Used to Derive the Device's Power Dissipation Tcase - Tamb Rth - Heatsink = Pd Figure 28: Efficiency vs. Output Current Figure 29: Efficiency vs. Output Voltage Figure 30: Efficiency vs. Output Voltage 16/21 Figure 31: Open Loop Frequency and Phase Response of Error Amplifier (see fig.7C) L4970A Figure 32: Power Dissipation Derating Curve Figure 33: A5.1V/12V Multiple Supply. Note the Synchronization between the L4970A and the L4974A 17/21 L4970A Figure 34: 5.1V / 10A Low Cost Application Figure 35: 10A Switching Regulator, Adjustable from 0V to 25V. 18/21 L4970A Figure 36: L4970A'sSync. Example 19/21 L4970A MULTIWATT15 PACKAGE MECHANICAL DATA DIM. mm MIN. TYP. MAX. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 0.063 D 1 0.039 E 0.49 0.55 0.019 F 0.66 0.75 0.026 G 1.14 1.27 1.4 0.045 0.050 0.055 G1 17.57 17.78 17.91 0.692 0.700 0.705 H1 19.6 L 0.022 0.030 0.772 H2 20/21 inch 20.2 0.795 22.1 22.6 0.870 0.890 L1 22 22.5 0.866 0.886 L2 17.65 18.1 0.695 L3 17.25 17.5 17.75 0.679 0.689 L4 10.3 10.7 10.9 0.406 0.421 L7 2.65 2.9 0.104 0.713 0.699 0.429 0.114 M 4.2 4.3 4.6 0.165 0.169 0.181 M1 4.5 5.08 5.3 0.177 0.200 0.209 S 1.9 2.6 0.075 S1 1.9 2.6 0.075 0.102 0.102 Dia1 3.65 3.85 0.144 0.152 L4970A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved MULTIWATT is a Registered Trademark of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 21/21 L4972A L4972AD 2A SWITCHING REGULATOR .. .. .. .. . . .. .. 2A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 200KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4972A is a stepdown monolithicpower switching regulator delivering 2A at a voltagevariable from 5.1 to 40V. Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of MULTIPOWER BCD TECHNOLOGY POW ERDIP (16 + 2 + 2) SO20 ORDERING NUMBERS : L4972A (Powerdip) L4972AD (SO20) the L4972A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a Powerdip 16 + 2 + 2 and SO20 large plastic packages and requires few external components. Efficient operation at switching frequencies up to 200KHz allows reduction in the size and cost of external filter component. BLOCK DIAGRAM January 1995 1/23 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4972A-L4972AD ABSOLUTE MAXIMUM RATINGS Symbol Value Unit V11 Input Voltage Parameter 55 V V11 Input Operating Voltage 50 V V20 Output DC Voltage Output Peak Voltage at t = 0.1s f = 200khz -1 -5 V V I20 Maximum Output Current VI Boostrap Voltage Boostrap Operating Voltage 65 V11 + 15 V V V4, V8 V Internally Limited Input Voltage at Pins 4, 12 12 V3 Reset Output Voltage 50 V I3 Reset Output Sink Current 50 mA V2, V7, V9, V10 Input Voltage at Pin 2, 7, 9, 10 7 V I2 Reset Delay Sink Current 30 mA I7 Error Amplifier Output Sink Current 1 A I8 Soft Start Sink Current Ptot TJ, Tstg 30 mA Total Power Dissipation at TPINS 90C at Tamb = 70C (No copper area on PCB) 5 / 3.75(*) 1.3/1 (*) W W Junction and Storage Temperature -40 to 150 C (*) SO-20 PIN CONNECTION (top view) THERMAL DATA Symb ol R th j-pins Rth j-amb 2/23 Parameter Thermal Resistance Junction-Pins Thermal Resistance Junction-ambient max max Pow erdip SO -20 12C/W 60C/W 16C/W 80C/W L4972A-L4972AD PIN FUNCTIONS N o Name Fun ction 1 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 2 RESET DELAY A Cd capacitor connected between this terminal and ground determines the reset signal delay time. 3 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. 4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. GROUND Common Ground Terminal 7 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 8 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. 9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. 10 SYNC INPUT Multiple L4972A's are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. 11 SUPPLY VOLTAGE Unregulated Input Voltage. 5, 6 15, 16 12, 19 N.C. Not Connected. 13 Vref 5.1V Vref Device Reference Voltage. 14 Vstart Internal Start-up Circuit to Drive the Power Stage. 17 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current of Cosc. 18 OSCILLATOR Cosc. External capacitor connected to ground determines (with Rosc) the switching frequency. 20 OUTPUT Regulator Output. 3/23 L4972A-L4972AD CIRCUIT OPERATION The L4972A is a 2A monolithic stepdown switching regulatorworking in continuousmode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 2A at an output voltage adjustable from 5.1V to 40V and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltagelockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysterysis, this thresholdporvides a correct voltage for the driving stage of the DMOS gate and the hysterysis prevents instabilities. An external bootstrap capacitor charge to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 200kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator in order to generate frixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and stability of the loop can be adjusted by 4/23 an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output vol-tage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on, output overcurrents are preventedby the soft start function (fig. 2). The error amplifier is initially clamped by an externalcapacitor, Css, and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit. The load current is sensed by a internal metal resistor connectedto a comparator.When the load current exceeds a preset threshold, the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHzoscillator, will reset the flip flop and the power DMOS will again conduct. This current protection method, ensuresa constant current output when the system is overloadedor short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuit (fig. 4), generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by a external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V, the reset output goes low immediately. The reset output is an open drain. Fig. 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig. 4B shows the case when the output is 5.1V, but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has a hysterysis to prevent unstable conditions. L4972A-L4972AD Figure 1 : Feedforward Waveform. Figure 2 : Soft Start Function. Figure 3 : Limiting Current Function. 5/23 L4972A-L4972AD Figure 4 : Reset and Power Fail Functions. A B 6/23 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Vi Input Volt. Range (pin 11) Vo = Vref to 40V Io = 2A (**) 15 Max. Un it F ig. 50 V 5 Vo Output Voltage Vi =15V to 50V Io = 1A; V o = Vref 5 5.1 5.2 V 5 Vo Line Regulation Vi = 15V to 50V Io = 0.5A; Vo = Vref 12 30 mV Vo Load Regulation Vo = Vref Io = 0.5A to 2A 7 20 mV Vd Dropout Voltage between Pin 11 and 20 Io = 2A 0.25 0.4 V I20L Max Limiting Current Vi = 15V to 50V Vo = Vref to 40V 2.5 2.8 3.5 A Efficiency (*) Io = 2A, f = 100KHz Vo = Vref Vo = 12V 75 85 90 % % 56 60 dB 5 90 100 110 KHz 5 2 6 % 5 % 5 KHz 5 F ig. SVR Supply Voltage Ripple Rejection f Switching Frequency f/Vi Voltage Stability Switching Frequency Test Co nditions Vi = 2VRMS; Io = 1A f = 100Hz; Vo = Vref of Vi = 15V to 45V f/Tj Temperature Stability of Switching Frequency Tj = 0 to 125C fmax Maximum Operating Switching Frequency Vo = Vref R4 = 15K Io = 2A C9 = 2.2nF (*) Only for DIP version Min. Typ. 1 200 (**) Pulse testing with a low duty cycle Vref SECTION (pin 13) Symbol V13 Parameter Test Cond ition Reference Voltage Min. Typ. Max. Un it 5 5.1 5.2 V 7 V13 Line Regulation Vi = 15V to 50V 10 25 mV 7 V13 Load Regulation I13 = 0 to 1mA 20 40 mV 7 Tj = 0C to 125C 0.4 mV/C 7 V13 = 0 70 mA 7 V13 T I13 short Average Temperature Coefficient Reference Voltage Short Circuit Current Limit VSTART SECTION (pin 15) Symbol V14 Parameter Test Cond ition Reference Voltage Min. Typ. Max. Un it F ig. 11.4 12 12.6 V 7 V14 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7 V14 Load Regulation I14 = 0 to 1mA 50 200 mV 7 Short Circuit Current Limit V15 = 0V 80 mA 7 I14 short 7/23 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS Symbol Parameter V11on Turn-on Threshold V11 Hyst Turn-off Hysteresys I11Q Quiescent Current I11OQ I20L Test Cond ition Min. T yp. Max. Unit Fig . 10 11 12 V 7A 1 V 7A V8 = 0; S1 = D 13 19 mA 7A Operating Supply Current V8 = 0; S1 = B; S2 = B 16 23 mA 7A Out Leak Current Vi = 55V; S3 = A; V8 = 0 2 mA 7A Fig . SOFT START (pin 8) Symbol Parameter I8 Soft Start Source Current V8 = 3V; V9 = 0V Test Cond ition V8 Output Saturation Voltage I8 = 20mA; V11 = 10V I8 = 200A; V11 = 10V Min. T yp. Max. Unit 80 115 150 A 7B 1 0.7 V V 7B 7B Max. Unit Fig . V 7C V 7C 7C ERROR AMPLIFIER Symbol Parameter Test Cond ition Min. T yp. V7H High Level Out Voltage I7 = 100A; S1 = C V9 = 4.7V V7L Low Level Out Voltage I7 = 100A; S1 = C V9 = 5.3V; I7H Source Output Current V7 = 1V; V 7 = 4.7V 100 150 A -I7L Sink Output Current V7 = 6V; V 9 = 5.3V 100 150 A 7C I9 Input Bias Current S1 = B; RS = 10K A 7C GV 6 1.2 0.4 DC Open Loop Gain S1 = A; RS = 10 60 SVR Supply Voltage Rejection 15 < Vi < 50V 60 VOS Input Offset Voltage RS = 50 S1 = A 3 80 dB 7C dB 7C 2 10 mV 7C Min. T yp. Max. Unit Fig . 1.2 1.5 V 7A 2.5 5.5 V V 7A 7A A 7A mA 7A RAMP GENERATOR (pin 18) Symbol Parameter Test Cond ition V18 Ramp Valley S1 = B; S2 = B V18 Ramp Peak S1 = B S2 = B I18 Min. Ramp Current S1 = A; I17 = 100A I18 Max. Ramp Current S1 = A; I17 = 1mA Vi = 15V Vi = 45V 270 2.4 2.7 Min. T yp. 300 SYNC FUNCTION (pin 10) Symbol 8/23 Max. Unit Fig . V10 Low Input Voltage Parameter Vi = 15V to 50V; V8 = 0; S1 = B; S2 = B; S4 = B Test Cond ition -0.3 0.9 V 7A V10 High Input voltage V8 = 0; S1 = B; S2 = B; S4 = B 2.5 5.5 V 7A I10L Sync Input Current with Low V10 = V18 = 0.9V; S4 = B; Input Voltage S1 = B; S2 = B 0.4 mA 7A I10H Input Current with High V10 = 2.5V Input Voltage 1.5 mA 7A V10 Output Amplitude V - tW Output Pulse Width 0.8 s - Vthr = 2.5V 4 5 0.3 0.5 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS Symbol Min. Typ. Max. Un it F ig. V9R Rising Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V Vref -130 Vref -100 Vref -80 V mV 7D V9F Falling Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V 4.77 Vref -200 Vref -160 V mV 7D V2H Delay High Threshold Volt. Vi = 15 to 50V V4 = 5.3V V9 = V13 4.95 5.1 5.25 V 7D V2L Delay Low Threshold Volt. Vi = 15 to 50V V4 = 4.7V V9 = V13 1 1.1 1.2 V 7D I2SO Delay Source Current V4 = 5.3V; 30 60 80 A 7D I2SI Delay Source Sink Current V4 = 4.7V; V2 = 3V mA 7D V3S Output Saturation Voltage I3 = 15mA; S1 = B V4 = 4.7V 0.4 V 7D Output Leak Current V3 = 50V; S1 = A 100 A 7D V4R Rising Threshold Voltage V9 = V13 V4H Hysteresis I3 I4 Parameter Test Co nditions V2 = 3V Input Bias Current 10 4.95 5.1 5.25 V 7D 0.4 0.5 0.6 V 7D 1 3 A 7D F TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 2A ; fsw = 100KHz) Vo RIPPLE = 30mV (at 1A) Line regulation = 12mV (Vi = 15 to 50V) Load regulation = 7mV (Io = 0.5 to 2A) for component values Refer to the fig. 5 (Part list). 9/23 L4972A-L4972AD Figure 6a : Component Layout of fig.5 (1 : 1 scale). Evaluation Board Available (only for DIP version) PART LIST R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4.7K R7 = see table A R8 = OPTION R9 = 4.7K * C1 = C2 = 1000F 63V EYF (ROE) C3 = C4 = C 5 = C 6 = 2,2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP 1830 (ERO) C10 = 0.33F Film C11 = 1nF ** C12 = C13 = C14 = 100F 40V EKR (ROE) C15 = 1F Film D1 = SB 560 (OR EQUIVALENT) L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 19) COGEMA 949181 * 2 capacitors in parallel to increase input RMS current capability. * * 3 capacitors in parallel to reduce total output ESR. 10/23 Table A V0 R9 R7 12V 15V 18V 24V 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k 12 18 Note: In the Test and Application Circuit for L4972D are not mounted C2, C14 and R8. Table B SUGGESTED BOOSTRAP CAPACITORS O perating F requency Bo ostrap Cap.c10 f = 20KHz 680nF f = 50KHz 470nF f = 100KHz 330nF f = 200KHz 220nF f = 500KHz 100nF L4972A-L4972AD Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale) Figure 7 : DC Test Circuits. 11/23 L4972A-L4972AD Figure 7A. Figure 7B. Figure 7C. 12/23 L4972A-L4972AD Figure 7D. Figure 8 : Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9 : Quiescent Drain Current vs. Junction Temperature (0% duty cycle). 13/23 L4972A-L4972AD Figure 10 : Quiescent Drain Current vs. Duty Cycle. Figure 11 : Reference Voltage (pin 13) vs. Vi (see fig. 7). Figure 12 : Reference Voltage (pin 13) vs. Junction Temperature (see fig. 7). Figure 13 : Reference Voltage (pin 14) vs. Vi (see fig. 7). Figure 14 : Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7). Figure 15 : Reference Voltage 5.1V (pin 13) Supply Voltage Ripple Rejection vs. FreSVR (dB) 14/23 L4972A-L4972AD Figure 16 : Switching Frequency vs. Input Voltage (see fig. 5). Figure 17 : Switching Frequency vs. Junction Temperature (see fig. 5). Figure 18 : Switching Frequency vs. R4 (see fig.5). Figure 19 : Maximum Duty Cycle vs. Frequency. Figure 20 : Supply Voltage Ripple Rejection vs. Frequency (see fig. 5). Figure 21 : Efficiency vs. Output Voltage. 15/23 L4972A-L4972AD Figure 22 : Line Transient Response (see fig. 5). Figure 23 : Load Transient Response (see fig. 5). Figure 24 : Dropout Voltage between Pin 11 and Pin 20 vs. Current at Pin 20. Figure 25 : .Dropout Voltage between Pin 11 and Pin 20 vs. Junction Temperature. Figure 26 : Power Dissipation (device only) vs. Input Voltage. Figure 27 : Power Dissipation (device only) vs. Input Voltage. 16/23 L4972A-L4972AD Figure 28 : Power Dissipation (device only) vs. Output Voltage. Figure 29 : Power Dissipation (device only) vs. Output Voltage. Figure 30 : Power Dissipation (device only) vs. Output Current. Figure 31 : Power Dissipation (device only) vs. Output Current. Figure 32 : Efficiency vs. Output Current. Figure 33 : Test PCB Thermal Characteristic. 17/23 L4972A-L4972AD Figure 34 : Junction to Ambient Thermal Resistance vs. Area on Board Heatsink (DIP 16+2+2) Figure 35: Junction to Ambient Thermal Resistance vs. Area on Board Heatsink (SO20) Figure 36: Maximum Allowable Power Dissipation vs. Ambient Temperature (Powerdip) Figure 37: Maximum Allowable Power Dissipation vs. Ambient Temperature (SO20) Figure 38: Open Loop Frequency and Phase of Error Amplifier (see fig. 7C). 18/23 L4972A-L4972AD Figure 39 : 2A - 5.1V Low Cost Application Circuit. Figure 40 : A 5.1V/12V Multiple Supply. Note the Synchronization between the L4972A and L4970A. 19/23 L4972A-L4972AD Figure 41 : L4972A's Sync. Example. Figure 42: 1A/24V Multiple Supply. Note the synchronization between the L4972A and L4962 20/23 L4972A-L4972AD POWERDIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.020 0.50 D 0.055 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L Z 3.30 0.130 1.27 0.050 21/23 L4972A-L4972AD SO20 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. TYP. 2.65 0.1 MAX. 0.104 0.3 a2 0.004 0.012 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 (typ.) D 12.6 13.0 0.496 0.512 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M S 22/23 MIN. 0.75 0.030 8 (max.) L4972A-L4972AD Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 23/23 L4974A 3.5A SWITCHING REGULATOR .. .. .. .. . . .. .. 3.5A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 200KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4974A is a stepdown monolithicpower switching regulator delivering 3.5A at a voltage variable from 5.1 to 40V. Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of MULTIPOWER BCD TECHNOLOGY PO WERDIP (16 + 2 + 2) ORDERING NUMBER : L4974A the L4974A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mountedin a Powerdip 16 + 2 + 2 plastic package and requires few external components. Efficient operation at switching frequenciesup to 200KHz allows reduction in the size and cost of external filter component. BLOCK DIAGRAM January 1995 1/22 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4974A ABSOLUTE MAXIMUM RATINGS Symbol Value Unit V11 Input Voltage Parameter 55 V V11 Input Operating Voltage 50 V V20 Output DC Voltage Output Peak Voltage at t = 0.1s f = 200khz -1 -5 V V I20 Maximum Output Current VI Boostrap Voltage Boostrap Operating Voltage 65 V11 + 15 V V V4, V8 V Internally Limited Input Voltage at Pins 4, 12 12 V3 Reset Output Voltage 50 V I3 Reset Output Sink Current 50 mA V2, V7, V9, V10 Input Voltage at Pin 2, 7, 9, 10 7 V I2 Reset Delay Sink Current 30 mA I7 Error Amplifier Output Sink Current 1 A I8 Soft Start Sink Current 30 mA Total Power Dissipation at TPINS 90C at Tamb = 70C (No copper area on PCB) 5 1.3 W W -40 to 150 C Ptot TJ, Tstg Junction and Storage Temperature PIN CONNECTION (top view) THERMAL DATA Symb ol R th j-pins Rth j-amb 2/22 Parameter Thermal Resistance Junction-Pins Thermal Resistance Junction-ambient max max Value Un it 12 60 C/W C/W L4974A PIN FUNCTIONS N o Name Fun ction 1 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 2 RESET DELAY A Cd capacitor connected between this terminal and ground determines the reset signal delay time. 3 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. 4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. GROUND Common Ground Terminal 7 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 8 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. 9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. 10 SYNC INPUT Multiple L4974A's are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. 11 SUPPLY VOLTAGE Unregulated Input Voltage. 5, 6 15, 16 12, 19 N.C. Not Connected. 13 Vref 5.1V Vref Device Reference Voltage. 14 Vstart Internal Start-up Circuit to Drive the Power Stage. 17 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current of Cosc. 18 OSCILLATOR Cosc. External capacitor connected to ground determines (with Rosc) the switching frequency. 20 OUTPUT Regulator Output. 3/22 L4974A CIRCUIT OPERATION The L4974A is a 3.5A monolithic stepdown switching regulatorworking in continuousmode realized in the new BCD Technology. This technologyallows the integrationof isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 3.5A at an output voltage adjustable from 5.1V to 40V and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltagelockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysterysis, this thresholdporvides a correct voltage for the driving stage of the DMOS gate and the hysterysis prevents instabilities. An external bootstrap capacitor charge to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 200kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator in order to generate frixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and stability of the loop can be adjusted by 4/22 an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output vol-tage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on, output overcurrents are preventedby the soft start function (fig. 2). The error amplifier is initially clamped by an externalcapacitor, Css, and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit. The load current is sensed by a internal metal resistor connectedto a comparator.When the load current exceeds a preset threshold, the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHzoscillator, will reset the flip flop and the power DMOS will again conduct. This current protection method, ensuresa constant current output when the system is overloadedor short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuit (fig. 4), generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by a external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V, the reset output goes low immediately. The reset output is an open drain. Fig. 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig. 4B shows the case when the output is 5.1V, but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has a hysterysis to prevent unstable conditions. L4974A Figure 1 : Feedforward Waveform. Figure 2 : Soft Start Function. Figure 3 : Limiting Current Function. 5/22 L4974A Figure 4 : Reset and Power Fail Functions. A B 6/22 L4974A ELECTRICAL CHARACTERISTICS (refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Vi Input Volt. Range (pin 11) Vo = Vref to 40V Io = 3.5A (*) 15 Max. Un it F ig. 50 V 5 Vo Output Voltage Vi =15V to 50V Io = 2A; V o = Vref 5 5.1 5.2 V 5 Vo Line Regulation VI = 15V to 50V Io = 1A; Vo = Vref 12 30 mV Vo Load Regulation VO = Vref Io = 1A to 3.5A Io = 2A to 3A 8 25 mV Vd Dropout Voltage between Pin 11 and 20 Io = 2A Io = 3.5A I20L Max Limiting Current Vi = 15V to 50V Vo = Vref to 40V Efficiency Io = 3.5A, f = 100KHz Vo = Vref Vo = 12V SVR Test Co nditions Vi = 2VRMS; Io = 5A f = 100Hz; Vo = Vref Supply Voltage Ripple Rejection f Switching Frequency f/Vi Voltage Stability Switching Frequency Min. 4 10 mV 0.25 0.45 0.4 0.7 V 4 4.75 5.5 A 80 85 90 % % 56 60 dB 90 100 110 KHz 5 2 6 % 5 % 5 KHz 5 F ig. of Vi = 15V to 45V f/Tj Temperature Stability of Switching Frequency Tj = 0 to 125C fmax Maximum Operating Switching Frequency Vo = Vref R4 = 15K Io = 3.5A C9 = 2.2nF Typ. 1 200 5 (*) Pulse testing with a low duty cycle Vref SECTION (pin 13) Symbol V13 Parameter Test Cond ition Reference Voltage Min. Typ. Max. Un it 5 5.1 5.2 V 7 V13 Line Regulation Vi = 15V to 50V 10 25 mV 7 V13 Load Regulation I13 = 0 to 1mA 20 40 mV 7 V13 T Average Coefficient Voltage 0.4 mV/C 7 I13 short Short Circuit Current Limit 70 mA 7 Temperature Tj = 0C to 125C Reference V13 = 0 VSTART SECTION (pin 15) Symbol V14 Parameter Test Cond ition Reference Voltage Min. Typ. Max. Un it F ig. 11.4 12 12.6 V 7 V14 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7 V14 Load Regulation I14 = 0 to 1mA 50 200 mV 7 Short Circuit Current Limit V15 = 0V 80 mA 7 I14 short 7/22 L4974A ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS Symbol Parameter V11on Turn-on Threshold V11 Hyst Turn-off Hysteresys I11Q Quiescent Current I11OQ I20L Test Cond ition Min. T yp. Max. Unit Fig . 10 11 12 V 7A 1 V 7A V8 = 0; S1 = D 13 19 mA 7A Operating Supply Current V8 = 0; S1 = B; S2 = B 16 23 mA 7A Out Leak Current Vi = 55V; S3 = A; V8 = 0 2 mA 7A Fig . SOFT START (pin 8) Symbol Parameter I8 Soft Start Source Current V8 = 3V; V9 = 0V Test Cond ition V8 Output Saturation Voltage I8 = 20mA; V11 = 10V I8 = 200A; V11 = 10V Min. T yp. Max. Unit 80 115 150 A 7B 1 0.7 V V 7B 7B Max. Unit Fig . V 7C V 7C 7C ERROR AMPLIFIER Symbol Parameter Test Cond ition Min. T yp. V7H High Level Out Voltage I7 = -100A; S1 = C V9 = 4.7V V7L Low Level Out Voltage I7 = 100A; S1 = C V9 = 5.3V; I7H Source Output Current V7 = 1V; V 7 = 4.7V 100 150 A -I7L Sink Output Current V7 = 6V; V 9 = 5.3V 100 150 A 7C I9 Input Bias Current S1 = B; RS = 10K A 7C GV 6 1.2 0.4 DC Open Loop Gain S1 = A; RS = 10 60 SVR Supply Voltage Rejection 15 < Vi < 50V 60 VOS Input Offset Voltage RS = 50 S1 = A 3 80 dB 7C dB 7C 2 10 mV 7C Min. T yp. Max. Unit Fig . 1.2 1.5 V 7A 2.5 5.5 V V 7A 7A A 7A mA 7A RAMP GENERATOR (pin 18) Symbol Parameter Test Cond ition V18 Ramp Valley S1 = B; S2 = B V18 Ramp Peak S1 = B S2 = B I18 Min. Ramp Current S1 = A; I17 = 100A I18 Max. Ramp Current S1 = A; I17 = 1mA Vi = 15V Vi = 45V 270 2.4 2.7 Min. T yp. 300 SYNC FUNCTION (pin 10) Symbol Max. Unit Fig . V10 Low Input Voltage Parameter Vi = 15V to 50V; V8 = 0; S1 = B; S2 = B; S4 = B Test Cond ition -0.3 0.9 V 7A V10 High Input voltage V8 = 0; S1 = B; S2 = B; S4 = B 2.5 5.5 V 7A +I10L Sync Input Current with Low V10 = V18 = 0.9V; S4 = B; Input Voltage S1 = B; S2 = B 0.4 mA 7A +I10H Input Current with High V10 = 2.5V Input Voltage 1.5 mA 7A V - 0.8 s - 8/22 V10 Output Amplitude tW Output Pulse Width Vthr = 2.5V 4 5 0.3 0.5 L4974A ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS Symbol Min. Typ. Max. Un it F ig. V9R Rising Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V Vref -130 Vref -100 Vref -80 V mV 7D V9F Falling Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V 4.77 Vref -200 Vref -160 V mV 7D V2H Delay High Threshold Volt. Vi = 15 to 50V V4 = 5.3V V9 = V13 4.95 5.1 5.25 V 7D V2L Delay Low Threshold Volt. Vi = 15 to 50V V4 = 4.7V V9 = V13 1 1.1 1.2 V 7D I2SO Delay Source Current V4 = 5.3V; 30 60 80 A 7D I2SI Delay Source Sink Current V4 = 4.7V; V2 = 3V mA 7D V3S Output Saturation Voltage I3 = 15mA; S1 = B V4 = 4.7V 0.4 V 7D Output Leak Current V3 = 50V; S1 = A 100 A 7D V4R Rising Threshold Voltage V9 = V13 V4H Hysteresis I3 I4 Parameter Test Co nditions V2 = 3V Input Bias Current 10 4.955 5.1 5.25 V 7D 0.4 0.5 0.6 V 7D 1 3 A 7D Figure 5 : Test and Evaluation Board Circuit. TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 3.5A ; fsw = 100KHz) Vo RIPPLE = 30mV (at 1A) Line regulation = 12mV (Vi = 15 to 50V) Load regulation = 8mV (Io = 1 to 3.5A) for component values Refer to the fig. 5 (Part list). 9/22 L4974A Figure 6a : Component Layout of fig.5 (1 : 1 scale). Evaluation Board Available PART LIST R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4.7K R7 = see table A R8 = OPTION R9 = 4.7K * C1 = C2 = 1000F 63V EYF (ROE) C3 = C4 = C 5 = C 6 = 2,2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP 1830 (ERO) C10 = 0.33F Film C11 = 1nF ** C12 = C13 = C14 = 100F 40V EKR (ROE) C15 = 1F Film D1 = SB 560 (OR EQUIVALENT) L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 19) COGEMA 949181 * 2 capacitors in parallel to increase input RMS current capability. * * 3 capacitors in parallel to reduce total output ESR. 10/22 Table A V0 R9 R7 12V 15V 18V 24V 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k 12 18 Table B SUGGESTED BOOSTRAP CAPACITORS O perating F requency Bo ostrap Cap.c10 f = 20KHz 680nF f = 50KHz 470nF f = 100KHz 330nF f = 200KHz 220nF f = 500KHz 100nF L4974A Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale) Figure 7 : DC Test Circuits. 11/22 L4974A Figure 7A. Figure 7B. Figure 7C. 12/22 L4974A Figure 7D. Figure 8 : Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9 : Quiescent Drain Current vs. Junction Temperature (0% duty cycle). 13/22 L4974A Figure 10 : Quiescent Drain Current vs. Duty Cycle. Figure 11 : Reference Voltage (pin 13) vs. Vi (see fig. 7). Figure 12 : Reference Voltage (pin 13) vs. Junction Temperature (see fig. 7). Figure 13 : Reference Voltage (pin 14) vs. Vi (see fig. 7). Figure 14 : Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7). Figure 15 : Reference Voltage 5.1V (pin 13) Supply Voltage Ripple Rejection vs. FreSVR (dB) 14/22 L4974A Figure 16 : Switching Frequency vs. Input Voltage (see fig. 5). Figure 17 : Switching Frequency vs. Junction Temperature (see fig. 5). Figure 18 : Switching Frequency vs. R4 (see fig.5). Figure 19 : Maximum Duty Cycle vs. Frequency. Figure 20 : Supply Voltage Ripple Rejection vs. Frequency (see fig. 5). Figure 21 : Efficiency vs. Output Voltage. 15/22 L4974A Figure 22 : Line Transient Response (see fig. 5). Figure 23 : Load Transient Response (see fig. 5). Figure 24 : Dropout Voltage between Pin 11 and Pin 20 vs. Current at Pin 20. Figure 25 : .Dropout Voltage between Pin 11 and Pin 20 vs. Junction Temperature. Figure 26 : Power Dissipation (device only) vs. Input Voltage. Figure 27 : Power Dissipation (device only) vs. Input Voltage. 16/22 L4974A Figure 28 : Power Dissipation (device only) vs. Output Voltage. Figure 29 : Power Dissipation (device only) vs. Output Voltage. Figure 30 : Power Dissipation (device only) vs. Output Current. Figure 31 : Power Dissipation (device only) vs. Output Current. Figure 32 : Efficiency vs. Output Current. Figure 33 : Test PCB Thermal Characteristic. 17/22 L4974A Figure 34 : Junction to Ambient Thermal Resistance vs. Area on Board Heatsink (DIP 16+2+2) Figure 36: Open Loop Frequency and Phase of Error Amplifier (see fig. 7C). 18/22 Figure 35: Maximum Allowable Power Dissipation vs. Ambient Temperature (Powerdip) L4974A Figure 37 : 3.5A - 5.1V Low Cost Application Circuit. Figure 38 : A 5.1V/12V Multiple Supply. Note the Synchronization between the L4974A and L4970A. 19/22 L4974A Figure 39 : L4974A's Sync. Example. Figure 40: 1A/24V Multiple Supply. Note the synchronization between the L4974A and L4962 20/22 L4974A POWERDIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.020 0.50 D 0.055 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L Z 3.30 0.130 1.27 0.050 21/22 L4974A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 22/22 L4975A 5A SWITCHING REGULATOR 5A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULATION INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS SOFT START INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 500KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4975A is a stepdown monolithic power switching regulator delivering 5A at a voltage variable from 5.1 to 40V. MULTIPOWER BCD TECHNOLOGY Multiwatt15V ORDERING NUMBER: L4975A Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of the L4975A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a 15-lead multiwatt plastic power package and requires few external components. Efficient operation at switching frequencies up to 500KHz allows reduction in the size and cost of external filter components. BLOCK DIAGRAM November 1991 1/21 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4975A ABSOLUTE MAXIMUM RATINGS Symbol Value Unit V9 Input Voltage Parameter 55 V V9 Input Operating Voltage 50 V V7 Output DC Voltage Output Peak Voltage at t = 0.1s f = 200KHz -1 -7 V V I7 Maximum Output Current V6 Bootstrap Voltage Bootstrap Operating Voltage V3, V12 Internally Limited 65 V9 + 15 V V V Input Voltage at Pins 3, 12 12 V4 Reset Output Voltage 50 V I4 Reset Output Sink Current 50 mA Input Voltage at Pin 5, 10, 11, 13 7 V mA V5, V10, V11, V13 I5 Reset Delay Sink Current 30 I10 Error Amplifier Output Sink Current 1 A I12 Soft Start Sink Current 30 mA Ptot Total Power Dissipation at Tcase < 120C Tj, Tstg Junction and Storage Temperature 30 W -40 to 150 C PIN CONNECTION (Top view) THERMAL DATA Symbol Rth j-case R th j-amb 2/21 Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient max max Value Unit 1 35 C/W C/W L4975A PIN FUNCTIONS o N Name Function 1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current of C osc. 2 OSCILLATOR Cosc. External capacitor connected to ground determines (with R osc) the switching frequency. 3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. 4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. 5 RESET DELAY A C d capacitor connected between this terminal and ground determines the reset signal delay time. 6 BOOTSTR AP A C boot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 7 OUTPUT Regulator Output. 8 GROUND Common Ground Terminal 9 SUPPLY VOLTAGE Unregulated Input Voltage. 10 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. 12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. 13 SYNC INPUT Multiple L4975A are synchronized by connecting pin 13 inputs together or via an external syncr. pulse. 14 Vref 5.1V Vref Device Reference Voltage. 15 Vstart Internal Start-up Circuit to Drive the Power Stage. CIRCUIT OPERATION (refer to the block diagram) The L4975A is a 5A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 5A at an output voltage adjustable from 5.1V to 40V, and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistor and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysteresis, this threshold provides a correct voltage for the driving stage of the DMOS gate and the hysteresis prevents instabilities. An external bootstrap capacitor charged to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 500kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator, in order to generate a fixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and 3/21 L4975A Figure 1: Feedforward Waveform Figure 2: Soft Start Function Figure 3: Limiting Current Function 4/21 L4975A stability of the loop can be adjusted by an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output voltage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on output overcurrents are prevented by the soft start function (fig. 2). The error amplifier is initially clamped by an external capacitor Css and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit (fig. 3). The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuitry (fig 4) generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by an external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V the reset output goes low immediately. The reset output is an open collector-drain. Fig 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig 4B shows the case when the output is 5.1V but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has an hysterysis to prevent unstable conditions. Figure 4: Reset and Power Fail Functions. A B 5/21 L4975A ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25C, Vi = 35V, R4 = 16K, C9 = 2.2nF, fSW = 200KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Test Condition Min. Vi input Voltage Range (pin 9) Vo = Vref to 40V Io = 5A 15 Vo Output Votage Vi = 15V to 50V Io = 3A; Vo = Vref 5 Vo Line Regulation Vi = 15V to 50V Io = 2A; Vo = Vref Vo Load Regulation Vo = Vref Io = 2A to 4A Io = 1A to 5A Typ. Max. Unit Fig. 50 V 5 5.1 5.2 V 5 12 30 mV 5 10 20 30 50 mV mV 0.4 0.55 0.6 0.8 V V 5 5.5 6.5 7.5 A 5 5 Vd Dropout Voltage Between Pin 9 and 7 Io = 3A Io = 5A I7L Max. Limiting Current Vi = 15 to 50V Vo = Vref to 40V Efficiency Io = 3A Vo = Vref Vo = 12V 70 75 80 % % Io = 5A Vo = Vref Vo = 12V 80 85 92 % % 56 60 dB 180 SVR f f Vi f Tj fmax Supply Voltage Ripple Reject. Vi = 2VRMS; Io = 3A f = 100Hz; Vo = Vref Switching Frequency 5 5 5 200 220 KHz 5 Voltage Stability of Swiching Frequency Vi = 15V to 45V 2 6 % 5 Temperature Stability of Swiching Frequency T j = 0 to 125C 1 % 5 Maximum Operating Switching Frequency Vo = Vref; R4 = 10K Io = 5A; C9 = 1nF 500 KHz 5 Test Condition Min. Typ. Max. Unit Fig. 5 5.1 5.2 V 7 Vref SECTION (pin 14) Symbol Parameter V14 Reference Voltage V14 Line Regulation Vi = 15V to 50V 10 25 mV 7 V14 V14 T Load Regulation I14 = 0 to 1mA 20 40 mV 7 Average Temperature Coefficient Reference Voltage T j = 0C to 125C 0.4 mV/C 7 Short Circuit Current Limit V14 = 0 70 mA 7 Unit Fig. I14 sho rt VSTART SECTION (pin 15) Symbol Parameter Test Condition Min. Max. V15 Reference Voltage 12 12.6 V 7 V15 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7 V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7 Short Circuit Current Limit V15 = 0V 80 mA 7 I15 sho rt 6/21 11.4 Typ. L4975A ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS Symbol Parameter V9on Turn-on Threshold V9 Hyst Turn-off Hysteresys Test Condition Min. Typ. Max. Unit Fig. 10 11 12 V 7A V 7A I9Q Quiescent Current V12 = 0; S1 = D 13 19 mA 7A I9OQ Operating Supply Current V12 = 0; S1 = C; S2 = B 16 23 mA 7A Out Leak Current Vi = 55V; S3 = A; V12 = 0 2 mA 7A Fig. I7L 1 SOFT START Symbol Parameter Test Condition I12 Soft Start Source Current V12 = 3V; V11 = 0V V12 Output Saturation Voltage I12 = 20mA; V9 = 10V I12 = 200A; V9 = 10V Min. Typ. Max. Unit 70 100 130 A 7B 1 0.7 V V 7B 7B Max. Unit Fig. V 7C V 7C ERROR AMPLIFIER Symbol Parameter Test Condition Min. Typ. V10H High Level Out Voltage I10 = -100A; S1 = C V11 = 4.7V V10L Low Level Out Voltage I10 = +100A; S1 = C V11 = 5.3V; I10H Source Output Current V10 = 1V; S1 = E V11 = 4.7V 100 150 A 7C I10L Sink Output Current V10 = 6V; S1 = D V11 = 5.3V 100 150 A 7C I11 Input Bias Current R S = 10K GV DC Open Loop Gain VVCM = 4V; R S = 10 60 SVR Supply Voltage Rejection 15 < Vi < 50V; R S = 10 60 VOS Input Offset Voltage R S = 50 6 1.2 0.4 3 80 A - dB - dB - 2 10 mV - Min. Typ. Max. Unit Fig. 1.2 1.5 V 7A 2.5 5.5 V V 7A 7A RAMP GENERATOR (pin 2) Symbol Parameter Test Condition V2 Ramp Valley S1 = C; S2 = B V2 Ramp Peak S1 = C S2 = B I2 Min. Ramp Current S1 = A; I1 = 100A I2 Max. Ramp Current S1 = A; I1 = 1mA Vi = 15V Vi = 45V 270 2.4 2.7 Min. Typ. 300 A 7A mA 7A SYNC FUNCTION (pin 13) Symbol Max. Unit Fig. V13 Low Input Voltage Parameter Vi = 15V to 50V; V12 = 0; S1 = C; S2 = B; S4 = B Test Condition -0.3 0.9 V 7A V13 High Input voltage V12 = 0; S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A I13L Sync Input Current with Low Input Voltage V2 = V13 = 0.9V; S4 = A; S1 = C; S2 = B 0.4 mA 7A I13H Input Current with High Input Voltage V13 = 3.5V; S4 = A; S1 = C; S2 = B 1.5 mA 7A V13 Output Amplitude V - tW Output Pulse Width 0.8 s - Vthr = 2.5V 4 5 0.3 0.5 7/21 L4975A ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS Symbol Parameter Min. Typ. Max. Unit Fig. V11R Rising Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V Test Condition Vref -120 Vref -100 Vref -80 V mV 7D V11F Falling Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V 4.77 Vref -200 Vref -160 V mV 7D V5H Delay High Threshold Voltage Vi = 15 to 50V V11 = V14 4.95 5.1 5.25 V 7D V5L Delay Low Threshold Voltage Vi = 15 to 50V V11 = V14 V3 = 5.3V 1 1.1 1.2 V 7D -I5SO 60 80 Delay Source Current V3 = 5.3V; V5 = 3V 40 I5SI Delay Sink Current V3 = 4.7V; V5 = 3V 10 V4S Out Saturation Voltage I4 = 15mA; S1 = B V3 = 4.7V Output Leak Current V4 = 50V; S1 = A V3 = 5.3V V3R Rising Threshold Voltage V11 = V14 V3H Hysteresys I4 I3 7D 7D 0.4 V 7D 100 A 7D 4.95 5.1 5.25 V 7D 0.4 0.5 0.6 V 7D 1 3 A 7D Input Bias Current Figure 5: Test and Evaluation Board Circuit TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 5A ; fSW = 200KHz) Vo RIPPLE = 30mV (at 5A) with output filter capacitor ESR 60m Line regulation = 5mV (Vi = 15 to 50V) Load regulation = 15mV (Io = 2 to 5A) For component values, refer to test circuit part list. 8/21 A mA L4975A Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale). PARTS LIST Table A R1 = 30K C 1, C2 = 3300F 63VL EYF (ROE R2 = 10K C 3, C4, C5, C6 = 2.2F R3 = 15K C 7 = 390pF Film R4 = 16K C 8 = 22nF MKT 1817 (ERO) R5 = 22 0,5W R6 = 4K7 C 9 = 2.2nF KP1830 R7 = 10 C 10 = 220nF MKT R8 = see tab. A C 11 = 2.2nF MP1830 R9 = OPTION **C12 , C13, C14 = 220F 40VL EKR R10 = 4K7 C 15 = 1F Film V0 R9 R7 12V 15V 18V 24V 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k 12k 18k Table B SUGGESTED BOOTSTRAP CAPACITORS Operating Frequency Bootstrap Cap.c10 D1 = MBR 760CT (or 7.5A/60V or equivalent) f = 20KHz 680nF L1 = 80H f = 50KHz 470nF f = 100KHz 330nF f = 200KHz 220nF f = 500KHz 100nF R11 = 10 core 58930 MAGNETICS 24 TURNS O 1.1mm (AWG 17) COGEMA 949178 * 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR 9/21 L4975A Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale) Figure 7: DC Test Circuits 10/21 L4975A Figure 7A Figure 7B 11/21 L4975A Figure 7D Figure 7C 12/21 L4975A Figure 8: Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9: Quiescent Drain Current vs. Junction Temperature (0% duty cycle). Figure 10: Quiescent Drain Current vs. Duty Cycle Figure 11: Reference Voltage (pin14) vs. Vi (see fig. 7) Figure 12: Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7) Figure 13: Reference Voltage (pin15) vs. Vi (see fig. 7) 13/21 L4975A Figure 14: Reference Voltage (pin 15) vs. Junction Temperature (see fig. 7) Figure 15: Reference Voltage 5.1V (pin 14) Supply Voltage Ripple Rejection vs. Frequency Figure 16: Switching Frequency vs. Input Voltage (see fig. 5) Figure 17: Switching Frequency vs. Junction Temperature (see fig 5) Figure 18: Switching Frequency vs. R4 (see fig. 5) Figure 19: Max. Duty Cycle vs. Frequency 14/21 L4975A Figure 20: Supply Voltage Ripple Rejection vs. Frequency (see fig. 5) Figure 21: Line Transient Response (see fig. 5) Figure 22: Load Transient Response (see fig. 5) Figure 23: Dropout Voltage Between Pin 9 and Pin 7 vs. Current at Pin 7 Figure 24: Dropout Voltage Between Pin 9 and Pin 7 vs. Junction Temperature Figure 25: Power Dissipation (device only) vs. Input Voltage 15/21 L4975A Figure 26: Power Dissipation (device only) vs. Output Voltage Figure 27: Heatsink Used to Derive the Device's Power Dissipation Tcase - Tamb Rth - Heatsink = Pd Figure 28: Efficiency vs. Output Current Figure 29: Efficiency vs. Output Voltage Figure 30: Efficiency vs. Output Voltage 16/21 Figure 31: Open Loop Frequency and Phase Response of Error Amplifier (see fig.7C) L4975A Figure 32: Power Dissipation Derating Curve Figure 33: 5.1V/12V Multiple Supply. Note the Synchronization between the L4975A and the L4974A 17/21 L4975A Figure 34: 5.1V / 5A Low Cost Application Figure 35: 5A Switching Regulator, Adjustable from 0V to 25V. 18/21 L4975A Figure 36: L4975A'sSync. Example 19/21 L4975A MULTIWATT15 PACKAGE MECHANICAL DATA DIM. mm MIN. TYP. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 D 0.063 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.14 1.27 1.4 0.045 0.050 0.055 G1 17.57 17.78 17.91 0.692 0.700 0.705 H1 19.6 0.772 H2 20/21 inch MAX. 20.2 0.795 L 22.1 22.6 0.870 0.890 L1 22 22.5 0.866 0.886 L2 17.65 18.1 0.695 0.713 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L7 2.65 2.9 0.104 M 4.2 4.3 4.6 0.165 0.169 M1 4.5 5.08 5.3 0.177 0.200 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 0.114 0.181 0.209 L4975A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved MULTIWATT is a Registered Trademark of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 21/21 L4977A 7A SWITCHING REGULATOR 7A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULATION INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS SOFT START INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 500KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4977A is a stepdown monolithic power switching regulator delivering 7A at a voltage variable from 5.1 to 40V. MULTIPOWER BCD TECHNOLOGY Multiwatt15V ORDERING NUMBER: L4977A Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of the L4977A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a 15-lead multiwatt plastic power package and requires few external components. Efficient operation at switching frequencies up to 500KHz allows reduction in the size and cost of external filter components. BLOCK DIAGRAM November 1991 1/21 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4977A ABSOLUTE MAXIMUM RATINGS Symbol Value Unit V9 Input Voltage Parameter 55 V V9 Input Operating Voltage 50 V V7 Output DC Voltage Output Peak Voltage at t = 0.1s f = 200KHz -1 -7 V V I7 Maximum Output Current V6 Bootstrap Voltage Bootstrap Operating Voltage V3, V12 Internally Limited 65 V9 + 15 V V V Input Voltage at Pins 3, 12 12 V4 Reset Output Voltage 50 V I4 Reset Output Sink Current 50 mA Input Voltage at Pin 5, 10, 11, 13 7 V mA V5, V10, V11, V13 I5 Reset Delay Sink Current 30 I10 Error Amplifier Output Sink Current 1 A I12 Soft Start Sink Current 30 mA Ptot Total Power Dissipation at Tcase < 120C Tj, Tstg Junction and Storage Temperature 30 W -40 to 150 C PIN CONNECTION (Top view) THERMAL DATA Symbol Rth j-case R th j-amb 2/21 Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient max max Value Unit 1 35 C/W C/W L4977A PIN FUNCTIONS o N Name Function 1 OSCILLATOR Rosc. External resistor connected to ground determines the constant charging current of C osc. 2 OSCILLATOR Cosc. External capacitor connected to ground determines (with R osc) the switching frequency. 3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. 4 RESET OUT Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. 5 RESET DELAY A C d capacitor connected between this terminal and ground determines the reset signal delay time. 6 BOOTSTR AP A C boot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 7 OUTPUT Regulator Output. 8 GROUND Common Ground Terminal 9 SUPPLY VOLTAGE Unregulated Input Voltage. 10 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. 12 SOFT START Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. 13 SYNC INPUT Multiple L4977A are synchronized by connecting pin 13 inputs together or via an external syncr. pulse. 14 Vref 5.1V Vref Device Reference Voltage. 15 Vstart Internal Start-up Circuit to Drive the Power Stage. CIRCUIT OPERATION (refer to the block diagram) The L4977A is a 7A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 7A at an output voltage adjustable from 5.1V to 40V, and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistor and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysteresis, this threshold provides a correct voltage for the driving stage of the DMOS gate and the hysteresis prevents instabilities. An external bootstrap capacitor charged to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 500kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator, in order to generate a fixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and 3/21 L4977A Figure 1: Feedforward Waveform Figure 2: Soft Start Function Figure 3: Limiting Current Function 4/21 L4977A stability of the loop can be adjusted by an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output voltage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on output overcurrents are prevented by the soft start function (fig. 2). The error amplifier is initially clamped by an external capacitor Css and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit (fig. 3). The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuitry (fig 4) generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by an external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V the reset output goes low immediately. The reset output is an open collector-drain. Fig 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig 4B shows the case when the output is 5.1V but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has an hysterysis to prevent unstable conditions. Figure 4: Reset and Power Fail Functions. A B 5/21 L4977A ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25C, Vi = 35V, R4 = 16K, C9 = 2.2nF, fSW = 200KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Test Condition Min. Vi input Voltage Range (pin 9) Vo = Vref to 40V Io = 7A 15 Vo Output Votage Vi = 15V to 50V Io = 3A; Vo = Vref 5 Vo Line Regulation Vi = 15V to 50V Io = 2A; Vo = Vref Vo Load Regulation Typ. Max. Unit Fig. 50 V 5 5.1 5.2 V 5 12 30 mV 5 Vo = Vref Io = 3A to 5A Io = 2A to 7A 10 20 25 40 mV mV 0.4 0.8 0.6 1.1 V V 5 8 9.5 11 A 5 5 Vd Dropout Voltage Between Pin 9 and 7 Io = 5A Io = 7A I7L Max. Limiting Current Vo = Vref to 40V Vi = 15 to 50V Efficiency Io = 3A Vo = Vref Vo = 12V 70 75 80 % % Io = 7A Vo = Vref Vo = 12V 75 80 87 % % 56 60 dB 180 SVR f f Vi f Tj fmax Supply Voltage Ripple Reject. Vi = 2VRMS; Io = 3A f = 100Hz; Vo = Vref Switching Frequency 5 5 5 200 220 KHz 5 Voltage Stability of Swiching Frequency Vi = 15V to 45V 2 6 % 5 Temperature Stability of Swiching Frequency T j = 0 to 125C 1 % 5 Maximum Operating Switching Frequency Vo = Vref; R4 = 10K Io = 7A; C9 = 1nF 500 KHz 5 Test Condition Min. Typ. Max. Unit Fig. 5 5.1 5.2 V 7 Vref SECTION (pin 14) Symbol Parameter V14 Reference Voltage V14 Line Regulation Vi = 15V to 50V 10 25 mV 7 V14 V14 T Load Regulation I14 = 0 to 1mA 20 40 mV 7 Average Temperature Coefficient Reference Voltage T j = 0C to 125C 0.4 mV/C 7 Short Circuit Current Limit V14 = 0 70 mA 7 Unit Fig. I14 sho rt VSTART SECTION (pin 15) Symbol Parameter Test Condition Min. Max. V15 Reference Voltage 12 12.6 V 7 V15 Line Regulation Vi = 15 to 50V 0.6 1.4 V 7 V15 Load Regulation I15 = 0 to 1mA 50 200 mV 7 Short Circuit Current Limit V15 = 0V 80 mA 7 I15 sho rt 6/21 11.4 Typ. L4977A ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS Symbol Parameter V9on Turn-on Threshold V9 Hyst Turn-off Hysteresys Test Condition Min. Typ. Max. Unit Fig. 10 11 12 V 7A V 7A I9Q Quiescent Current V12 = 0; S1 = D 13 19 mA 7A I9OQ Operating Supply Current V12 = 0; S1 = C; S2 = B 16 23 mA 7A Out Leak Current Vi = 55V; S3 = A; V12 = 0 2 mA 7A Fig. I7L 1 SOFT START Symbol Parameter Test Condition I12 Soft Start Source Current V12 = 3V; V11 = 0V V12 Output Saturation Voltage I12 = 20mA; V9 = 10V I12 = 200A; V9 = 10V Min. Typ. Max. Unit 70 100 130 A 7B 1 0.7 V V 7B 7B Max. Unit Fig. V 7C V 7C ERROR AMPLIFIER Symbol Parameter Test Condition Min. Typ. V10H High Level Out Voltage I10 = -100A; S1 = C V11 = 4.7V V10L Low Level Out Voltage I10 = +100A; S1 = C V11 = 5.3V; I10H Source Output Current V10 = 1V; S1 = E V11 = 4.7V 100 150 A 7C I10L Sink Output Current V10 = 6V; S1 = D V11 = 5.3V 100 150 A 7C I11 Input Bias Current R S = 10K GV DC Open Loop Gain VVCM = 4V; R S = 10 60 SVR Supply Voltage Rejection 15 < Vi < 50V; R S = 10 60 VOS Input Offset Voltage R S = 50 6 1.2 0.4 3 80 A - dB - dB - 2 10 mV - Min. Typ. Max. Unit Fig. 1.2 1.5 V 7A 2.5 5.5 V V 7A 7A RAMP GENERATOR (pin 2) Symbol Parameter Test Condition V2 Ramp Valley S1 = C; S2 = B V2 Ramp Peak S1 = C S2 = B I2 Min. Ramp Current S1 = A; I1 = 100A I2 Max. Ramp Current S1 = A; I1 = 1mA Vi = 15V Vi = 45V 270 2.4 2.7 Min. Typ. 300 A 7A mA 7A SYNC FUNCTION (pin 13) Symbol Max. Unit Fig. V13 Low Input Voltage Parameter Vi = 15V to 50V; V12 = 0; S1 = C; S2 = B; S4 = B Test Condition -0.3 0.9 V 7A V13 High Input voltage V12 = 0; S1 = C; S2 = B; S4 = B 3.5 5.5 V 7A I13L Sync Input Current with Low Input Voltage V13 = V2 = 0.9V; S4 = A; S1 = C; S2 = B 0.4 mA 7A I13H Input Current with High Input Voltage V13 = 3.5V; S4 = A; S1 = C; S2 = B 1.5 mA 7A V13 Output Amplitude V - tW Output Pulse Width 0.8 s - Vthr = 2.5V 4 5 0.3 0.5 7/21 L4977A ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS Symbol Parameter Min. Typ. Max. Unit Fig. V11R Rising Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V Test Condition Vref -120 Vref -100 Vref -80 V mV 7D V11F Falling Threshold Voltage (pin 11) Vi = 15 to 50V V3 = 5.3V 4.77 Vref -200 Vref -160 V mV 7D V5H Delay High Threshold Voltage Vi = 15 to 50V V11 = V14 V3 = 5.3V 4.95 5.1 5.25 V 7D V5L Delay Low Threshold Voltage Vi = 15 to 50V V11 = V14 V3 = 5.3V 1 1.1 1.2 V 7D -I5SO 60 80 Delay Source Current V3 = 5.3V; V5 = 3V 40 I5SI Delay Sink Current V3 = 4.7V; V5 = 3V 10 V4S Out Saturation Voltage I4 = 15mA; S1 = B V3 = 4.7V Output Leak Current V4 = 50V; S1 = A V3 = 5.3V V3R Rising Threshold Voltage V11 = V14 V3H Hysteresys I4 I3 7D 7D 0.4 V 7D 100 A 7D 4.95 5.1 5.25 V 7D 0.4 0.5 0.6 V 7D 1 3 A 7D Input Bias Current Figure 5: Test and Evaluation Board Circuit TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 7A ; fSW = 200KHz) Vo RIPPLE = 30mV (at 7A) with output filter capacitor ESR 60m Line regulation = 5mV (Vi = 15 to 50V) Load regulation = 15mV (Io = 2 to 7A) For component values, refer to test circuit part list. 8/21 A mA L4977A Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale). PARTS LIST Table A R1 = 30K C 1, C2 = 3300F 63VL EYF (ROE R2 = 10K C 3, C4, C5, C6 = 2.2F R3 = 15K C 7 = 390pF Film R4 = 16K C 8 = 22nF MKT 1817 (ERO) R5 = 22 0,5W R6 = 4K7 C 9 = 2.2nF KP1830 R7 = 10 C 10 = 220nF MKT R8 = see tab. A C 11 = 2.2nF MP1830 R9 = OPTION **C12 , C13, C14 = 220F 40VL EKR R10 = 4K7 C 15 = 1F Film V0 R9 R7 12V 15V 18V 24V 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k 12k 18k Table B SUGGESTED BOOTSTRAP CAPACITORS Operating Frequency Bootstrap Cap.c10 D1 = MBR 1560CT (or 16A/60V or equivalent) f = 20KHz 680nF L1 = 40H f = 50KHz 470nF f = 100KHz 330nF f = 200KHz 220nF f = 500KHz 100nF R11 = 10 core 58071 MAGNETICS 27 TURNS O 1,3mm (AWG 16) COGEMA 949178 * 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR 9/21 L4977A Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale) Figure 7: DC Test Circuits 10/21 L4977A Figure 7A Figure 7B 11/21 L4977A Figure 7D Figure 7C 12/21 L4977A Figure 8: Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9: Quiescent Drain Current vs. Junction Temperature (0% duty cycle). Figure 10: Quiescent Drain Current vs. Duty Cycle Figure 11: Reference Voltage (pin14) vs. Vi (see fig. 7) Figure 12: Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7) Figure 13: Reference Voltage (pin15) vs. Vi (see fig. 7) 13/21 L4977A Figure 14: Reference Voltage (pin 15) vs. Junction Temperature (see fig. 7) Figure 15: Reference Voltage 5.1V (pin 14) Supply Voltage Ripple Rejection vs. Frequency Figure 16: Switching Frequency vs. Input Voltage (see fig. 5) Figure 17: Switching Frequency vs. Junction Temperature (see fig 5) Figure 18: Switching Frequency vs. R4 (see fig. 5) Figure 19: Max. Duty Cycle vs. Frequency 14/21 L4977A Figure 20: Supply Voltage Ripple Rejection vs. Frequency (see fig. 5) Figure 21: Line Transient Response (see fig. 5) Figure 22: Load Transient Response (see fig. 5) Figure 23: Dropout Voltage Between Pin 9 and Pin 7 vs. Current at Pin 7 Figure 24: Dropout Voltage Between Pin 9 and Pin 7 vs. Junction Temperature Figure 25: Power Dissipation (device only) vs. Input Voltage 15/21 L4977A Figure 26: Power Dissipation (device only) vs. Output Voltage Figure 27: Heatsink Used to Derive the Device's Power Dissipation Tcase - Tamb Rth - Heatsink = Pd Figure 28: Efficiency vs. Output Current Figure 29: Efficiency vs. Output Voltage Figure 30: Efficiency vs. Output Voltage 16/21 Figure 31: Open Loop Frequency and Phase Response of Error Amplifier (see fig.7C) L4977A Figure 32: Power Dissipation Derating Curve Figure 33: A5.1V/12V Multiple Supply. Note the Synchronization between the L4977A and the L4974A 17/21 L4977A Figure 34: 5.1V / 7A Low Cost Application Figure 35: 7A Switching Regulator, Adjustable from 0V to 25V. 18/21 L4977A Figure 36: L4977A'sSync. Example 19/21 L4977A MULTIWATT15 PACKAGE MECHANICAL DATA DIM. mm MIN. TYP. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 D 0.063 1 E 0.49 0.039 0.55 0.019 0.022 F 0.66 0.75 0.026 G 1.14 1.27 1.4 0.045 0.050 0.055 G1 17.57 17.78 17.91 0.692 0.700 0.705 H1 19.6 0.030 0.772 H2 20/21 inch MAX. 20.2 0.795 L 22.1 22.6 0.870 0.890 L1 22 22.5 0.866 0.886 L2 17.65 18.1 0.695 0.713 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L7 2.65 2.9 0.104 M 4.2 4.3 4.6 0.165 0.169 M1 4.5 5.08 5.3 0.177 0.200 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 0.114 0.181 0.209 L4977A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved MULTIWATT is a Registered Trademark of SGS-THOMSON Microlectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 21/21 SG2525A/2527A SG3525A/3527A REGULATING PULSE WIDTH MODULATORS .. .. .. .. . . 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE PULSES DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The SG3525A/3527Aseries of pulse width modulator integratedcircuits are designed to offerimproved performanceand lowered externalparts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT andthe discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shut- DIP16 16(Narrow) down, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltagelockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525Aoutput stage features NOR logic, giving a LOW outputfor an OFF state. The SG3527Autilizes OR logic which results in a HIGH output level when OFF. PIN CONNECTIONS AND ORDERING NUMBERS (top view) December 1995 Type Plastic DIP SO16 SG2525A SG2525AN SG2525AP SG2527A SG2527AN SG2527AP SG3525A SG3525AN SG3525AP SG3527A SG3527AN SG3527AP 1/12 SG2525A/27A-SG3525A/27A ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vi Supply Voltage 40 V VC Collector Supply Voltage 40 V Oscillator Charging Current 5 mA IOSC Parameter Io Output Current, Source or Sink 500 mA IR Reference Output Current 50 mA IT Current through CT Terminal Logic Inputs Analog Inputs 5 - 0.3 to + 5.5 - 0.3 to Vi mA V V Total Power Dissipation at Tamb = 70 C 1000 mW Tj Junction Temperature Range - 55 to 150 C Tstg Storage Temperature Range - 65 to 150 C Top Operating Ambient Temperature : SG2525A/27A SG3525A/27A -- 25 to 85 0 to 70 C C Ptot THERMAL DATA Symbol Rth j-pins Rth j-amb Rth j-alumina Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) SO16 Max Max Max 50 DIP16 Unit 50 80 C/W C/W C/W * Thermal resistance junction-alumina with thedevice soldered on the middle of an alumina supporting substrate measuring 15x 20 mm ; 0.65 mm thickness with infinite heatsink. BLOCK DIAGRAM 2/12 SG2525A/27A-SG3525A/27A ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified) Symbol Parameter SG2525A SG2527A Test Conditions SG3525A SG3527A Unit Min. Typ. Max. Min. Typ. Max. 5.05 5.1 5.15 5 5.1 5.2 V 10 20 10 20 mV REFERENCE SECTION VREF Output Voltage Tj = 25 C VREF Line Regulation Vi = 8 to 35 V VREF Load Regulation VREF/T* Temp. Stability IL = 0 to 20 mA 20 50 20 50 mV Over Operating Range 20 50 20 50 mV 5.25 V * Total Output Variation Short Circuit Current VREF = 0 Tj = 25 C 80 100 80 100 mA * Output Noise Voltage 10 Hz f 10 kHz, Tj = 25 C 40 200 40 200 Vrms Long Term Stability Tj = 125 C, 1000 hrs 20 50 20 50 mV Tj = 25 C 2 6 2 6 % 0.3 1 1 2 % 3 6 3 6 % VREF* Line, Load and Temperature 5 5.2 4.95 OSCILLATOR SECTION * * *, * *, * Initial Accuracy Voltage Stability Vi = 8 to 35 V f/T* Temperature Stability Over Operating Range fMIN Minimum Frequency RT = 200 K CT = 0.1 F fMAX Maximum Frequency R T = 2 K CT = 470 pF 400 Current Mirror IRT = 2 mA 1.7 2 3 3.5 0.3 0.5 *, * Clock Amplitude *, * Clock Width Tj = 25 C Sync Threshold Sync Input Current 120 1.2 Sync Voltage = 3.5 V 120 400 2.2 Hz KHz 1.7 2 3 3.5 1 0.3 0.5 1.2 2.2 mA V 1 s 2 2.8 2 2.8 V 1 2.5 1 2.5 mA 0.5 5 2 10 mV 1 10 1 10 A 1 A ERROR AMPLIFIER SECTION (VCM = 5.1 V) VOS Input Offset Voltage Ib Input Bias Current Ios Input Offset Current * *, 1 DC Open Loop Gain R L 10 M Gain Bandwidth Product Gv = 0 dB DC Transconduct. 30 K R L 1 M Tj = 25 C Tj = 25 C 60 75 60 75 dB 1 2 1 2 MHz 1.1 1.5 1.1 1.5 ms 3.8 5.6 3.8 5.6 V Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB 3/12 SG2525A/27A-SG3525A/27A ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter SG2525A SG2527A Test Conditions Min. Typ. 45 49 SG3525A SG3527A Max. Min. Typ. 45 49 Unit Max. PWM COMPARATOR Minimum Duty-cycle 0 Maximum Duty-cycle * Input Threshold Zero Duty-cycle 0.7 Maximum Duty-cycle * Input Bias Current 0.9 0 0.7 % % 0.9 V 3.3 3.6 3.3 3.6 V 0.05 1 0.05 1 A SHUTDOWN SECTION 50 80 A 0.4 0.7 V 0.8 1 V 1 0.4 1 mA 0.2 0.5 0.2 0.5 s Isink = 20 mA 0.2 0.4 0.2 0.4 V Isink = 100 mA 1 2 1 2 V Soft Start Current VSD = 0 V, VSS = 0 V Soft Start Low Level VSD = 2.5 V Shutdown Threshold To outputs, VSS = 5.1 V Tj = 25 C 25 0.6 Shutdown Input Current VSD = 2.5 V * Shutdown Delay VSD = 2.5 V Tj = 25 C 50 80 0.4 0.7 0.8 1 0.4 25 0.6 OUTPUT DRIVERS (each output) (VC = 20 V) Output Low Level Output High Level Isource = 20 mA 18 19 18 19 V Isource = 100 mA 17 18 17 18 V 6 7 6 7 Under-Voltage Lockout Vcomp and Vss = High IC Collector Leakage VC = 35 V 8 t r* Rise Time CL = 1 nF, Tj = 25 C 100 600 tf* Fall Time CL = 1 nF, Tj = 25 C 50 300 14 20 8 V 200 A 100 600 ns 50 300 ns 14 20 mA 200 TOTAL STANDBY CURRENT Is Supply Current Vi = 35 V * These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production. * Tested at fosc = 40 KHz (RT = 3.6 K, CT = 0.1 F, RD = 0 ). Approximate oscillator frequency is defined by : f= 1 CT (0.7 RT + 3 RD) . DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded. 4/12 SG2525A/27A-SG3525A/27A TEST CIRCUIT 5/12 SG2525A/27A-SG3525A/27A RECOMMENDED OPERATING CONDITIONS (*) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (VC) 4.5 to 35 V Sink/Source Load Current (steady state) 0 to 100 mA Sink/Source Load Current (peak) 0 to 400 mA Reference Load Current 0 to 20 mA Oscillator Frequency Range 100 Hz to 400 KHz Oscillator Timing Resistor * 2 K to 150 K Oscillator Timing Capacitor 0.001 F to 0.1 F Dead Time Resistor Range 0 to 500 ( ) Range over which the device is functional and parameter limits are guaranteed. Figure 1 : Oscillator Charge Time vs. RT and CT . Figure 2 : Oscillator Discharge Time vs. RD and CT . Figure 3 : SG1525A Output Saturation Characteristics. Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency. 6/12 SG2525A/27A-SG3525A/27A Figure 5 : SG1525A Error Amplifier. PRINCIPLES OF OPERATION SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 A to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. Analternateapproach isthe use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immedi- ately set providing the fastest turn-off signal to the outputs ; and a 150 A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. 7/12 SG2525A/27A-SG3525A/27A Figure 6 : SG1525A Oscillator Schematic. Figure 7 : SG1525A Output Circuit (1/2 circuit shown). 8/12 SG2525A/27A-SG3525A/27A Figure 8. Figure 9. For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. Figure 10. Figure 11. The low source impedance of the outputdrivers provides rapid charging of Power Mos input capacitance while minimizing external components. Low power transformers can be driven directly by the SG1525A. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. 9/12 SG2525A/27A-SG3525A/27A DIP16 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 10/12 inch 3.3 0.130 1.27 0.050 SG2525A/27A-SG3525A/27A SO16 NARROW PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.069 0.25 a2 MAX. 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45 (typ.) D 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.150 0.157 L 0.4 1.27 0.150 0.050 M S 0.62 0.024 8 (max.) 11/12 SG2525A/27A-SG3525A/27A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 12/12 UC2842/3/4/5 UC3842/3/4/5 CURRENT MODE PWM CONTROLLER . .. .. . .. . .. OPTIMIZED FOR OFF-LINE AND DC TO DC CONVERTERS LOW START-UP CURRENT (< 1 mA) AUTOMATIC FEED FORWARD COMPENSATION PULSE-BY-PULSE CURRENT LIMITING ENHANCED LOAD RESPONSE CHARACTERISTICS UNDER-VOLTAGE LOCKOUT WITH HYSTERESIS DOUBLE PULSE SUPPRESSION HIGH CURRENT TOTEM POLE OUTPUT INTERNALLY TRIMMED BANDGAP REFERENCE 500 KHz OPERATION LOW RO ERROR AMP DESCRIPTION The UC3842/3/4/5family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internallyimplemented circuits include undervoltagelockout featuring start-up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, Minid ip SO14 logic to insure latched operation, a PWM comparator which also providescurrent limit control,and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843 and UC3845 are 8.5 V and 7.9 V. The UC3842 and UC3843 can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844 and UC3845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGRAM (toggle flip flop used only in U3844 and UC3845) May 1995 1/11 UC2842/3/4/5-UC3842/3/4/5 ABSOLUTE MAXIMUM RATINGS Symbo l Parameter Vi Supply Voltage (low impedance source) Valu e Unit 30 V Vi Supply Voltage (Ii < 30mA) IO Output Current Self Limiting 1 A EO Output Energy (capacitive load) 5 J Analog Inputs (pins 2, 3) - 0.3 to 6.3 V 10 mA Error Amplifier Output Sink Current Ptot Power Dissipation at Tamb 50 C (minidip, DIP-14) Ptot Power Dissipation at Tamb 25 C (SO14) Tstg Storage Temperature Range TL Lead Temperature (soldering 10s) 1 W 725 mW - 65 to 150 C 300 C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. PIN CONNECTIONS (top views) SO14 Minidip ORDERING NUMBERS T ype Minidip SO14 UC2842 UC3843 UC2844 UC2845 UC2842N UC2843N UC2844N UC2845N UC2842D UC2843D UC2844D UC2845D UC3842 UC3843 UC3844 UC3845 UC3842N UC3843N UC3844N UC3845N UC3842D UC3843D UC3844D UC3845D THERMAL DATA Symbol R th j-amb 2/11 Descrip ti on Thermal Resistance Junction-ambient. max. Minidip SO 14 Un it 100 165 C UC2842/3/4/5-UC3842/3/4/5 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC2824X; 0 < Tamb < 70C for UC384X; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Test Co nditions UC284X UC384X Min. Typ. Max. Min . T yp. Max. Unit 4.95 5.00 5.05 4.90 5.00 5.10 V Symbo l Parameter VREF Output Voltage Tj = 25C Io = 1mA VREF Line Regulation 12V Vi 25V VREF Load Regulation 1 Io 20mA 6 25 6 25 mV VREF/T Temperature Stability (Note 2) 0.2 0.4 0.2 0.4 mV/C Total Output Variant Line, Load, Temperature (2) 5.18 V eN Output Noise Voltage 10Hz f 10KHz Tj = 25C (2) Long Term Stability Tamb = 125C, 1000Hrs (2) ISC Output Short Circuit REFERENCE SECTION 6 4.9 20 5.1 6 4.82 50 5 -30 20 V 50 25 -100 -180 5 -30 mV 25 -100 -180 mV mA OSCILLATOR SECTION fs V4 Initial Accuracy Tj = 25C (6) 52 57 Voltage Stability 12 Vi 25V 0.2 1 Temperature Stability TMIN Tamb TMAX (2) 5 5 % VPIN4 Peak to Peak 1.7 1.7 V Amplitude 47 47 52 57 KHz 0.2 1 % ERROR AMP SECTION V2 Input Voltage Ib Input Bias Current AVOL VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 -0.3 2 Vo 4V 65 -1 -0.3 90 65 -2 V A 90 dB B Unity Gain Bandwidth (2) 0.7 1 0.7 1 MHz SVR Supply Voltage Rejection 12V Vi 25V 60 70 60 70 dB Io Output Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 6 2 6 V Io Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -0.8 -0.5 -0.8 mA VOUT High VPIN2 = 2.3V; R L = 15K to Ground 5 6 5 6 V VOUT Low VPIN2 = 2.7V; R L = 15K to Pin 8 0.7 1.1 3 3.15 2.8 1 1.1 0.9 0.7 1.1 V 3 3.2 V/V 1 1.1 CURRENT SENSE SECTION GV Gain (3 & 4) 2.85 0.9 V3 Maximum Input Signal VPIN1 = 5V (3) SVR Supply Voltage Rejection 12 Vi 25V (3) Ib Input Bias Current 70 Delay to Output 70 V dB -2 -10 -2 -10 A 150 300 150 300 ns 0.1 0.4 0.1 0.4 V 1.5 2.2 1.5 2.2 OUTPUT SECTION IOL Output Low Level ISINK = 20mA IOH Output High Level ISOURCE = 20mA 13 13.5 ISOURCE = 200mA 12 13.5 tr Rise Time Tj = 25C CL = 1nF (2) 50 150 50 150 ns tf Fall Time Tj = 25C CL = 1nF (2) 50 150 50 150 ns ISINK = 200mA 13 13.5 12 13.5 V V V 3/11 UC2842/3/4/5-UC3842/3/4/5 ELECTRICAL CHARACTERISTICS (continued) Symbo l Parameter Test Co nditi ons UC284X UC384X Min. Typ . Max. Min . Typ. Max. Unit UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on X842/4 15 16 17 14.5 16 17.5 V X843/5 7.8 8.4 9.0 7.8 8.4 9 V X842/4 9 10 11 8.5 10 11.5 V X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V X842/3 93 97 100 93 97 100 % X844/5 46 48 50 47 48 50 % 0 % PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0 TOTAL STANDBY CURRENT Ist Start-up Current Ii Operating Supply Current Viz Zener Voltage 0.5 1 0.5 1 mA VPIN2 = VPIN3 = 0V 11 20 11 20 mA Ii = 25mA 34 Notes : 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : VPIN1 A= ; 0 VPIN3 0.8 V VPIN3 5. Adjust Vi above the start threshold before setting at 15 V. 6. Output frequency equals oscillator frequency for the UC3842 and UC3843. Output frequency is one half oscillator frequency for the UC3844 and UC3845. 4/11 34 V UC2842/3/4/5-UC3842/3/4/5 Figure 1 : Error Amp Configuration. Error amp can source or sink up to 0.5mA Figure 2 : Under Voltage Lockout. During Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents. Figure 3 : Current Sense Circuit . Peak current (is) is determined by the formula 1.0 V IS max RS A small RC filter may be required to suppress switch transients. 5/11 UC2842/3/4/5-UC3842/3/4/5 Figure 4. Figure 5 : Deadtime vs. CT (RT > 5K). for RT > 5K f = 1.72 RTCT Figure 6 : Timing Resistance vs. Frequency. Figure 8 : Error Amplifier Open-loop Frequency Response. 6/11 Figure 7 : Output Saturation Characteristics. UC2842/3/4/5-UC3842/3/4/5 Figure 9 : Open Loop Test Circuit. High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K potentiometerare used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 10 : Shutdown Techniques. Shutdown of the UC2842 can be accomplished by two methods ; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method cause the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shut- down conditionat pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling Vi below the lower UVLO threshold.At this point the reference turns off, allowing the SCR to reset. 7/11 UC2842/3/4/5-UC3842/3/4/5 Figure 11 : Off-line Flyback Regulator. Power Supply Specifications 1. Input Voltage : 95 VAC to 130 VAC (50 Hz/60 Hz) 2. Line Isolation : 3750 V 3. Switching Frequency : 40 KHz 4. Efficiency @ Full Load : 70 % 5. Output Voltage : A. + 5 V, 5 % : 1 A to 4 A load Ripple voltage : 50 mV P-P Max. B. + 12 V, 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max. C. - 12 V, 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max. Figure 12 : Slope Compensation. A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50 %. 8/11 Note that capacitor, C, forms a filter with R2 to supress the leading edge switch spikes. UC2842/3/4/5-UC3842/3/4/5 SO14 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.069 0.25 a2 MAX. 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S 0.68 0.027 8 (max.) 9/11 UC2842/3/4/5-UC3842/3/4/5 DIP14 PACKAGE MECHANICAL DATA mm DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 10/11 inch 3.18 3.81 0.125 0.150 UC2842/3/4/5-UC3842/3/4/5 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 11/11