© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 1
1Publication Order Number:
NB7L585/D
NB7L585
2.5V / 3.3V Differential 2:1
Mux Input to 1:6 LVPECL
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585 produces six identical output copies of Clock or Data
operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The NB7L585 is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585 is a member of the GigaComm™ family of high
performance clock products.
Features
•Maximum Input Data Rate > 8 Gb/s
•Data Dependent Jitter < 15 ps
•Maximum Input Clock Frequency > 5 GHz
•Random Clock Jitter < 0.8 ps RMS
•Low Skew 1:6 LVPECL Outputs, 20 ps max
•2:1 Multi−Level Mux Inputs
•175 ps Typical Propagation Delay
•55 ps Typical Rise and Fall Times
•Differential LVPECL Outputs, 800 mV peak−to−peak, typical
•Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
•Internal 50 W Input Termination Resistors
•VREFAC Reference Output
•QFN−32 Package, 5mm x 5mm
•−40ºC to +85ºC Ambient Operating Temperature
•These Devices are Pb−Free and are RoHS Compliant
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
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32
1NB7L
585
AWLYYWWG
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
50 W
50 W
IN1
VT1
IN1
50 W
50 W
IN0
VT0
IN0
Figure 1. Simplified Block Diagram
0
1
VREFAC1
VREFAC0
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
VCC
GND
+
SEL
NB7L585
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1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
910111213 161514
32 31 30 29 28 252627
IN0
VT0
VREFAC0
IN0
IN1
VT1
VREFAC1
IN1
GND
VCC
Q2
Q3
VCC
GND
Q2
GND
VCC
Q5
Q4
VCC
Q5
SEL
VCC
Q0
Q1
VCC
Q0
Exposed
Pad (EP)
GND
Q1
Q3
Q4
NC
Figure 2. Pinout: QFN−32 (Top View)
NB7L585
Table 1. INPUT SELECT FUNCTION TABLE
SEL* CLK Input Selected
0 IN0
1 IN1
*Defaults HIGH when left open.
Table 2. PIN DESCRIPTION
Pin Number Pin Name I/O Pin Description
1,4
5,8
IN0, IN0
IN1, IN1
LVPECL, CML,
LVDS Input
Non−inverted, Inverted, Differential Data Inputs internally biased to VCC/2
2,6 VT0, VT1 Internal 100 W Center−tapped Termination Pin for IN0 / IN0 and IN1 / IN1
31 SEL LVTTL/LVCMOS
Input
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left
open
10 NC −No Connect
11, 16, 18
23, 25, 30
VCC −Positive Supply Voltage. All VCC pins must be connected to the positive power supply
for correct DC and AC operation.
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
Q0, Q0
Q1, Q1
Q2,Q2
Q3, Q3
Q4, Q4
Q5, Q5
LVPECL Output Non−inverted, Inverted Differential Outputs Note 1.
9, 17, 24, 32 GND Negative Supply Voltage, connected to Ground
3
7
VREFAC0
VREFAC1
−Output Voltage Reference for Capacitor−Coupled Inputs
−EP −The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
NB7L585
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Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200 V
RPU − SEL Input Pullup Resistor 75 kW
Moisture Sensitivity (Note 3) QFN−32 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 288
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V +4.0 V
VIO Input/Output Voltage GND = 0 V −0.5 to VCC +0.5 V
VINPP Differential Input Voltage |IN − IN| 1.89 V
IIN Input Current Through RT (50 W Resistor) $40 mA
Iout Output Current Continuous
Surge
50
100
mA
IVREFAC VREFAC Sink or Source Current $1.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm
500 lfpm
QFN32
QFN32
31
27
°C/W
qJC Thermal Resistance (Junction−to−Case) (Note 4) QFN32 12 °C/W
Tsol Wave Solder 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7L585
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Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C
(Note 5)
Symbol Characteristic Min Typ Max Unit
POWER SUPPLY
VCC Power Supply Voltage VCC = 3.3V
VCC = 2.5V
3.0
2.375
3.3
2.5
3.6
2.625
V
ICC Power Supply Current (Inputs and Outputs Open) 185 225 mA
LVPECL Outputs
VOH Output HIGH Voltage (Note 6)
VCC = 3.3 V
VCC = 2.5 V
VCC – 1145
2155
1355
VCC – 800
2500
1700
mV
VOL Output LOW Voltage (Note 6)
VCC = 3.3 V
VCC = 2.5 V
VCC – 2000
1300
500
VCC – 1500
1800
1000
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 & 6)
VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV
VIL Single−ended Input LOW Voltage GND Vth − 100 mV
Vth Input Threshold Reference Voltage Range (Note 8) 1100 VCC −100 mV
VISE Single−ended Input Voltage (VIH − VIL) 200 1200 mV
VREFACx (for Capacitor− Coupled Inputs, Only)
VREFAC Output Reference Voltage @100 mA for Capacitor− Coupled
Inputs, Only
VCC – 1500 VCC – 1200 VCC – 1000 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9)
VIHD Differential Input HIGH Voltage (IN, IN) 1200 VCC mV
VILD Differential Input LOW Voltage (IN , IN) GND VIHD − 100 mV
VID Differential Input Voltage (IN , IN) (VIHD − VILD) 100 1200 mV
VCMR Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1050 VCC − 50 mV
IIH Input HIGH Current IN/IN (VTIN/VTIN Open) −150 150 mA
IIL Input LOW Current IN/IN (VTIN/VTIN Open) −150 150 mA
CONTROL INPUT (SEL Pin)
VIH Input HIGH Voltage for Control Pin 2.0 VCC mV
VIL Input LOW Voltage for Control Pin GND 0.8 mV
IIH Input HIGH Current −150 150 mA
IIL Input LOW Current −150 150 mA
TERMINATION RESISTORS
RTIN Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. LVPECL outputs (Qn/Qn) loaded with 50 W to VCC – 2 V for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10.VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
NB7L585
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Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol Characteristic Min Typ Max Unit
fMAX Maximum Input Clock Frequency; VOUTpp w 400 mV 5 7 GHz
fDATAMAX Maximum Operating Data Rate (PRBS23) 8 10 Gbps
fSEL Maximum Toggle Frequency, SEL 1.0 1.5 GHz
VOUTpp Output Voltage Amplitude (@ VINPPmin) fin ≤ 4 GHz
(Note 12) (Figures 8 and 10) fin ≤ 5 GHz
550
400
800
650
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
IN/IN to Q/Q
SEL to Q
125
75
175
200
250
300
ps
tPLH TC Propagation Delay Temperature Coefficient 50 Dfs/°C
tskew Output − Output skew (within device) (Note 13)
Device − Device skew (tpd max – tpdmin)
20
100
ps
tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 5.0 GHz 45 50 55 %
FNPhase Noise, fin = 1 GHz 10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−135
−137
−149
−150
−150
−151
dBc
tŐFNIntegrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS) 36 fs
tJITTER RJ – Output Random Jitter (Note 14) fin ≤ 5.0 GHz
DJ − Residual Output Deterministic Jitter (Note 15) ≤ 8 Gbps
0.2
5
0.8
15
ps rms
ps pk−pk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17) 0.7 psRMS
VINPP Input Voltage Swing (Differential Configuration) (Note 16) 100 1200 mV
tr,, tfOutput Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q 25 55 85 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC – 2 V. Input edge
rates 40 ps (20% − 80%).
12.Output voltage swing is a single−ended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16.Input voltage swing is a single−ended measurement operating in differential mode.
17.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical)
OUTPUT VOLTAGE AMPLITUDE
(mV)
0
200
1000
01 8765423
Q AMP (mV)
800
600
400
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Figure 4. Input Structure Figure 5. Differential Input Driven Single−Ended
Figure 6. Vth Diagram Figure 7. Differential Inputs Driven Differentially
Figure 8. Differential Inputs Driven Differentially Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
VIHD
VILD
VID = |VIHD(IN) − VILD(IN)|
IN
IN
IN
Vth
IN
IN
IN
IN
IN
Q
Q
tPLH
tPHL
VINPP = VIH(IN) − VIL(IN)
VOUTPP = VOH(Q) − VOL(Q)
50 W
50 W
INx
VTx
INx
VCC
VEE
Vthmin
Vthmax
Vth IN
VIHmax
VILmax
VIH
Vth
VIL
VIHmin
VILmin
VCC
VEE
VCMRmin
VCMRmax
VCMR
IN
IN
VIHDmax
VILDmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Vth
VIH
VIL
Figure 11. SEL to Qx Timing Diagram
tpd tpd
VCC / 2 VCC / 2
SEL
Qx
Qx
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VCC
LVPECL
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
NB7L585
VCC
VCC
CML
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VCC
VT = VCC
Figure 12. LVPECL Interface Figure 13. LVDS Interface
VT = VCC − 2.0 V
Figure 14. Standard 50 W Load CML Interface
VCC
LVDS
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VCC
VT = OPEN
GND GND GND GND
GND GND
VCC
Differential
Driver
IN
50 W
Zo = 50 W
Zo = 50 W
50 W
IN
VCC
VT = VREFAC*
Figure 15. Capacitor−Coupled Differential
Interface (VT Connected to VREFAC)
GND GND
*VREFAC bypassed to ground with a 0.01 mF capacitor.
CLKx CLKx
NB7L585
NB7L585 NB7L585
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
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DEVICE ORDERING INFORMATION
Device Package Shipping†
NB7L585MNG QFN−32
(Pb−Free)
74 Units / Rail
NB7L585MNR4G QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
SEATING
32 X
K
0.15 C
(A3)
A
A1
D2
b
1
916 17
32
2 X
2 X
E2
32 X
8
24
32 X
L
32 X
BOTTOM VIEW
EXPOSED PAD
TOP VIEW
SIDE VIEW
D
A
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
A0.10 B
C
0.05 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
DIM MIN NOM MAX
MILLIMETERS
A0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b0.180 0.250 0.300
D5.00 BSC
D2 2.950 3.100 3.250
E5.00 BSC
E2
e0.500 BSC
K0.200 −−− −−−
L0.300 0.400 0.500
2.950 3.100 3.250
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50 PITCH
3.20
0.28
3.20
32 X
28 X
0.63
32 X
5.30
5.30
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NB7L585/D
GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC).
LITERATURE FULFILLMENT:
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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