
HYB25D256400/800T/AT
256-MBit Double Data Rata SDRAM
3/01
Page 1 of 72
Features
• Double dat a rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received wit h data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned wit h data for writes
• Differential clock inputs (CK and CK )
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions wi th CK
transitions.
• Commands entered on each positive CK edge;
data and data mask ref erenced t o both edges of
DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto P recharge opt ion for each burst access
• Auto Ref resh and Se lf Refresh Mode s
•7.8 µs Maximum Average Per iodic Refresh
Interval
• 2.5V (SSTL_2 compati ble) I/O
•V
DDQ = 2.5V ± 0.2V / VDD = 2. 5V ± 0.2V
• TSO P66 package
Description
The 256Mb DDR SDRAM is a hi gh-speed CMO S,
dynamic random -access memory co ntaining
268,435,456 bits . It is in terna lly configured as a
quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation . The
double data rate archit ecture is essential ly a 2n
prefetch architecture with an i nte rface designe d to
tran sfer two data words per clock cycle at the I/O
pins. A single read or wri te access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidi rect ional data strobe (DQS) is transmit ted
externally, along with dat a, for use in data capt ur e at
the receiver. DQS is a strobe t ransmitted by the
DDR SDRAM during Reads and by t he memory
controller during Writes. DQS is edge-ali gned with
data for Reads and center-aligned with data f or
Writes.
The 256Mb DDR SDRAM operates from a differen-
tial cl oc k (CK and CK; the cros sing of CK going
HIGH and CK goin g LOW is referred to as the pos i -
tive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as
well as to bot h edges of CK.
Read and write accesse s to the DDR SDRAM are
burst oriented; acces ses start at a selected l ocati on
and continue for a programm ed number of locations
in a programmed se quence. Accesses beg in with
the regis tration of an Act ive com mand, which is then
followed by a Read or Writ e c ommand. The address
bits regist ered coinci dent with the Active command
are used to select the bank and row to be accessed.
The address bits registered coincident with the
Read or Write command ar e used to select the bank
and the starting column location for the burst
access.
The DDR SDRAM provides for programma bl e Read
or Wri t e burst lengths of 2, 4 or 8 locati ons. An Auto
Precharge fu nction may be enabled to provide a
self-timed row precharge that is init iated at the end
of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operati on, thereby providing high effective band -
width by hiding row precharge and activation time.
An auto refresh mod e is provided along with a
power-savi ng power-down mode. All inputs are
compati bl e with the JEDEC Standard for SSTL_2.
All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing
specifications includ ed in this data sheet are for th e
DLL Enabled m ode of operation.
CAS Latency and Frequency
CAS Laten cy Maximum Operat ing Frequen cy (MHz )
DDR266A
-7 DDR266B
-7.5 DDR200
-8
2 133 125 100
2.5 143 133 125
.