HYB25D256400-800T-AT - Infineon Technologies

HYB25D256400/800T/AT

256-MBit Double Data Rata SDRAM

3/01

Page 1 of 72

Features

• Double dat a rate architecture: two data transfers

per clock cycle

• Bidirectional data strobe (DQS) is transmitted

and received wit h data, to be used in capturing

data at the receiver

• DQS is edge-aligned with data for reads and is

center-aligned wit h data for writes

• Differential clock inputs (CK and CK )

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions wi th CK

transitions.

• Commands entered on each positive CK edge;

data and data mask ref erenced t o both edges of

DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2, 2.5

• Auto P recharge opt ion for each burst access

• Auto Ref resh and Se lf Refresh Mode s

•7.8 µs Maximum Average Per iodic Refresh

Interval

• 2.5V (SSTL_2 compati ble) I/O

•V

DDQ = 2.5V ± 0.2V / VDD = 2. 5V ± 0.2V

• TSO P66 package

Description

The 256Mb DDR SDRAM is a hi gh-speed CMO S,

dynamic random -access memory co ntaining

268,435,456 bits . It is in terna lly configured as a

quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate

architecture to achieve high-speed operation . The

double data rate archit ecture is essential ly a 2n

prefetch architecture with an i nte rface designe d to

tran sfer two data words per clock cycle at the I/O

pins. A single read or wri te access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit

wide, one clock cycle data transfer at the internal

DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

A bidi rect ional data strobe (DQS) is transmit ted

externally, along with dat a, for use in data capt ur e at

the receiver. DQS is a strobe t ransmitted by the

DDR SDRAM during Reads and by t he memory

controller during Writes. DQS is edge-ali gned with

data for Reads and center-aligned with data f or

Writes.

The 256Mb DDR SDRAM operates from a differen-

tial cl oc k (CK and CK; the cros sing of CK going

HIGH and CK goin g LOW is referred to as the pos i -

tive edge of CK). Commands (address and control

signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and

output data is referenced to both edges of DQS, as

well as to bot h edges of CK.

Read and write accesse s to the DDR SDRAM are

burst oriented; acces ses start at a selected l ocati on

and continue for a programm ed number of locations

in a programmed se quence. Accesses beg in with

the regis tration of an Act ive com mand, which is then

followed by a Read or Writ e c ommand. The address

bits regist ered coinci dent with the Active command

are used to select the bank and row to be accessed.

The address bits registered coincident with the

Read or Write command ar e used to select the bank

and the starting column location for the burst

access.

The DDR SDRAM provides for programma bl e Read

or Wri t e burst lengths of 2, 4 or 8 locati ons. An Auto

Precharge fu nction may be enabled to provide a

self-timed row precharge that is init iated at the end

of the burst access.

As with standard SDRAMs, the pipelined, multibank

architecture of DDR SDRAMs allows for concurrent

operati on, thereby providing high effective band -

width by hiding row precharge and activation time.

An auto refresh mod e is provided along with a

power-savi ng power-down mode. All inputs are

compati bl e with the JEDEC Standard for SSTL_2.

All outputs are SSTL_2, Class II compatible.

Note: The functionality described and the timing

specifications includ ed in this data sheet are for th e

DLL Enabled m ode of operation.

CAS Latency and Frequency

CAS Laten cy Maximum Operat ing Frequen cy (MHz )

DDR266A

-7 DDR266B

-7.5 DDR200

-8

2 133 125 100

2.5 143 133 125

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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Pin Configuration

27 41

VDD

DQ0

VDDQ

DQ1

VSSQ

VDDQ

DQ3

VSSQ

DQ2

VDDQ

VDD

NU, QFC

CAS

RAS

BA0

BA1

VSS

DQ7

VSSQ

DQ6

VDDQ

VSSQ

DQ4

VDDQ

DQ5

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

VDD

NU, QFC

CAS

RAS

BA0

BA1

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

A10/AP

VDD

A10/AP

VDD

VSS

Column Address Table

Organization Column Address

64Mb x 4 A0-A9, A11

32Mb x 8 A0-A9

*DM is internally loaded to match DQ and DQS identical l y.

64Mb x 4

32Mb x 8

66-pin Plastic TSOP-II 400mil

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

Page 3 of 72 3/01

Inpu t/Outp ut Funct ional Descriptio n

Symbol Type Function

CK, CK Input Clock: CK and CK are differential clock inpu ts. All ad dress and control input signals are sam-

pled on the crossing of the positive edge of CK and negative edge of CK. Outpu t (read ) da ta

is referenced to the crossings of CK and CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE Low deactivate s, internal clock signal s and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self Refre s h operation (all banks idle) , or Ac tive Power- Down (row Ac tive in any bank).

CKE is synchrono us for power down entry and exit, and f or self refresh entry. CKE is asyn-

chronous for self refresh exit. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input

buffers , excluding CKE, are disabled during self refresh.

CS Input Chip Select: All commands are masked when CS is regist ered HIGH. CS provides for exter-

nal bank selection on systems with multiple banks. CS is consid ered part of the command

code. The standard pinout includes one CS pin.

RAS, CAS, WE Input Co mm a nd Inp uts: RAS, CA S and WE (along with CS) define the command being entered.

DM Input

Input Data Mask: DM is an input mask signal for write data. Input da ta is masked when DM

is sampled HIGH coincident with that input data during a Write access. DM is s ampled on

both edges of DQS. Although DM pi ns are input only, the DM loading matches the DQ and

DQS loading.

BA 0, BA1 Inpu t Bank Address Inputs: BA0 and B A1 define to which bank an Active, Read, W rite or Pre-

charge command is being applied. BA0 and BA1 also determines if the mode r egister or

extended mode register is to be accessed dur ing a MRS or EMRS c ycle.

A0 - A12 Input

Add ress Inputs: Provi de the r ow address for Active commands, and the column address

and Auto Prechar ge bit for Read/ Write comman ds, to select one location out of the memory

arr ay in the resp ective bank. A10 is sampled during a Precharge c ommand to determine

whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one

bank is to be prechar ged, the bank is selected by BA0, BA1. The addr ess inputs also provide

the op-code during a Mode Register Set comman d.

DQ Input/Output Data Input/O utput: Data bus.

DQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

QFC Output

FET control: Optional. Output during ev ery Re ad and Write access. Is provided t o con trol

is olat io n swi t che s on mod ul es . Op en d rai n ou tput . Pull up resi st or mu st be tie d t o VDDQ at sec-

ond level of assembly.

Th e QF C pin is present on this product version, but all timings parameters related to this pin

are not te sted on the final product and are only guaran teed by design.

NC No Conn ect: No internal electrical connection is present.

VDDQ Supply DQ Powe r Supply : 2.5V ± 0.2V.

VSSQ Supply DQ G roun d

VDD Supply Power Supply: 2.5V ± 0.2V.

VSS Supply Ground

VREF Supply SSTL_2 ref erenc e voltage: (VDDQ / 2)

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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Ordering Information

P art Number (A STC) CAS

Latency Clock

(MHz) CAS

Latency Clock

(MHz) Speed Org. Package

HYB25D256400T-7

2.5

143

133 DDR266A x 4

66 pin TSOP-II

HYB25D256800T-7 x 8

HYB25D256400T-7.5 133 125 DDR266B x 4

HYB25D256800T-7.5 x 8

HYB25D256400T-8 125 100 DDR200 x 4

HYB25D256800T-8 x 8

Part Number (WOS) CAS

Latency Clock

(MHz) CAS

Latency Clock

(MHz) Speed Org. Package

HYB25D256400AT-7

2.5

143

133 DDR266A x 4

66 pin TSOP-II

HYB25D256800AT-7 x 8

HYB25D256400AT-7.5 133 125 DDR266B x 4

HYB25D256800AT-7.5 x 8

HYB25D256400AT-8 125 100 DDR200 x 4

HYB25D256800AT-8 x 8

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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Block Diagram (64Mb x 4)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 1024 x 8)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

DQ0-DQ3,

DQS

Read Latch

Write

FIFO

Drivers

Note: T hi s Func t io na l Blo ck Diag r am i s i nten de d t o fac il it ate use r un de rs tan di ng of the op er ati o n of

the device; it doe s not repres ent an actual circ uit implementat ion.

Note: D M is a unidirectional signal (input only ), but is int ernally loaded to match the load of the bidi-

rec tio na l D Q and DQ S sig na ls .

Column

Decoder

1024

(x8)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

QFC

generator DRVR QFC

(Optional)

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256-Mbit Double Data Rate SDRAM

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Block Diagram (32Mb x 8)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

DQ0-DQ7,

DQS

Read Latch

Write

FIFO

Drivers

Note: Thi s F unc tio na l Bl ock D iagr am is i nt end ed t o f a cili ta t e us er un de rst an di ng of th e o pe rat io n of

the device; it does not represent an actual circuit implementation.

Note: D M i s a unidirectional signal (input only), but i s internally loaded t o match the load of the bidi-

re c tio na l D Q an d D QS sig na ls .

Column

Decoder

512

(x16)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

QFC

generator DRVR QFC

(Optional)

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256-Mbit Double Data Rate SDRAM

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Functional Description

The 256Mb DDR SDRAM is a high-s peed CMOS, dynamic random-access memory containing 268, 435, 456

bits. The 256Mb DDR SDRAM is i nternally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a doubl e-data-rate architecture to achieve high-speed operation. The doubl e-

data-rate architecture is essentially a 2n prefetch architecture, with an i nterface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a

single 2n-bit wide, one clock c ycle data transfer at the in ternal DRAM core and t wo correspondi ng n-bit wide,

one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR S DRAM are burst oriented; accesses start at a selected location and

continue for a programmed numbe r of locations in a programmed sequence. Access es begin with the regis-

tration of an A ctiv e comm and, which is then followed by a Read or Write co mmand. The address bits regis-

tered coincident with the Active command are used to sel ect the bank and row to be accessed (B A0, BA1

select the bank; A0-A12 select the row). T he address bits registered coincident with the Read or Write com-

mand are used to select the starti ng colum n location for the burst access.

Prior to normal operation, the DDR SDRAM must be i nitiali zed. The following sections provi de detailed infor-

mation covering device initialization, register definition, command de scription s and device operation .

Initialization

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other

than those specified may result in undefined operation. The following two condition s must be met:

No power sequening is specified during power up or power down given the fol lwing criteria

VDD and VDDQ are driven from a single power converter output

VTT meets the specification

A minimu m resistance of 42 ohms limits the input current from the VTT supply into any pin and VREF

tracks VDDQ/2

The fol lowing relationshi p must be followed

VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V

VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V

VREF is driv en after or with VDDQ such tha t VREF < VDDQ + 0. 3V

The DQ and DQS outputs are in the High-Z state, where they rem ain until driven in normal operat ion (by a

read access). A fter all power supply and reference voltag es are stable, and the clock is stable, the DDR

SDRAM requires a 200µs del ay prior to applying an executable command.

Once the 200µs delay has been sat isfied, a Deselect or NOP command shoul d be applied, and CKE must be

brought HIGH. Following the NOP command, a Precharge ALL command must be appl ied. Nex t a Mode Reg-

ister Set c ommand must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register

Set command must be iss ued for the Mode Register, to reset the DLL, and to program t he operating parame-

ters. 200 cl ock cycles are required between the DLL reset and any read command. A Precharge ALL com-

mand should be applied, pla cing the device in the “all ba nk s id le” state

Once in th e idle state, t wo AUTO REFRES H cycles must be performed. Additionally, a Mode Register Set

command for the Mode Register, with the res et DLL bit deactivated (i.e. to p rogram operating parameters

without resetti ng the DLL) must be performed. Following these cycles, the DDR S DRAM is ready for normal

operation.

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256-Mbit Double Data Rate SDRAM

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Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. T hi s definition

includes the selection of a burst length, a burst ty pe, a CAS latency, and an operating mode. The Mo de Reg-

ister is programmed via the Mode Register Set comman d (with BA0 = 0 and BA1 = 0) and retai ns the stored

information unt i l it is programmed again or the device loses power (except for bit A8, which is sel f- clearing).

Mode Regist er bits A 0-A2 s pecify the burst length, A3 specifies the type of burst (sequential or i nterleaved),

A4-A6 specify the CAS latency, and A7-A12 specify the operating mode .

The Mode Register must be loaded when all banks are idle, and the controller must wait the s pecified time

before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-

tion.

B u r st Len gth

Read and write accesses to the DDR S DRAM are burst oriented, with the burst length being prog ramm abl e.

The burst length det ermines the maximum number of column locat i ons that can be accessed for a given

Read or Write command. Burst lengths of 2, 4 , or 8 loc ation s are available for both the sequential and the

interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is eff ectively

selected. All accesses for that burst take place within t his bl ock, meaning that the burst wraps wi thin the block

if a boundary is reached. T he bl ock is uni quely selected by A1-Ai when t he burst length is set to two, by A2-Ai

when the burst length is s et to four and by A3-Ai when the burs t length is s et to eight (where Ai is the m os t

significant column address bit for a g iven co nfiguration). The remaining (least significant) address bit(s) is

(are) used to select the starting location within the block. The programmed burst length applies to both Read

and Write bursts.

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256-Mbit Double Data Rate SDRAM

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Mode Register Operation

A8 A7 A6 A5 A4

CAS Latency

A3 A2 A1 A0

Burst Lengt hBT

Address Bus

CAS Latency

A6 A5 A4 Latency

000 Reserved

001 Reserved

010 2

011 Reserved

100 Reserved

101 Reserved

110 2.5

1 1 1 Reserved

Burst Length

A2 A1 A0 Burst Length

000 Reserved

001 2

010 4

011 8

100 Reserved

101 Reserved

110 Reserved

111 Reserved

BA1 BA0 A11 A10 A9

0* 0* Mode Register

Operating Mode

* BA0 and BA1 must be 0, 0 to select the Mode R egister

(vs. the Extended Mode Register).

A12 - A9 A8 A7 A6 - A0 Operat ing Mode

000Valid

Normal operation

Do not reset DLL

010Valid

Normal operation

in DLL Reset

0 0 1 Reserved

−−− Reserved

A3 Burst Type

0 Sequential

1 Interleave

VS** Vendor Specific

A12

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256-Mbit Double Data Rate SDRAM

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Notes:

1. For a burst length of two, A1-Ai selects the two-dat a-ele men t block; A0 s elects the first ac ces s within the

block.

2. F or a bu rst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within

the block.

3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access

within the block.

4. Whenev er a boundary of t he bl ock is reached within a giv en sequence abo v e, the f ollowi ng access wr aps

within the block.

Burst Type

Accesses within a given burst may be programmed to be ei ther sequential or interleaved; thi s is referred to as

the burst type and is sel ec ted via bit A 3. The ordering of accesses within a burst is determined by the burs t

length, the burst type and the starting column address, as shown in Burst Definition on page 10.

Read Latenc y

The Read latency, or CA S latency, i s the delay, in c lock cycl es, between the registration of a Read command

and the availability of the first burst of output dat a. The latency can be programmed 2 or 2.5 clocks.

If a Read command i s registered at clock edge n, and the lat ency is m cl o cks, the d ata is ava i lab l e nomin ally

coincident with clock edge n + m.

Reserv ed stat es shou ld not be used as un know n operat ion or inc ompatibility with future v ers ions may result.

Burst Definit ion

Burst Length Starting Column Address Order of Accesses Within a Burst

A2 A1 A0 Type = Sequential Type = Interleaved

20 0-1 0-1

11-0 1-0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

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256-Mbit Double Data Rate SDRAM

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Operati ng Mod e

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero ,

and bits A0-A6 set to the d es ired values. A DLL reset is in itiated by issuing a Mode Registe r Set command

with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode

to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and

reserved states should not be used as unknown operation or incompatibility with future versions m ay res ult.

Required CAS Latencies

NOP NOP NOP NOP NOPRead

CAS Latency = 2, BL = 4

Shown with nominal tAC, tDQSCK, an d tDQSQ.

Command

DQS

Don’t Ca re

CL=2

NOP NOP NOP NOP NOPRead

C AS Latency = 2.5, BL = 4

Command

DQS

CL=2.5

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256-Mbit Double Data Rate SDRAM

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Extended Mode Register

The Ext ended M ode Regi st er controls functions beyond those controll ed by t he Mode Register; these addi-

tional funct i ons include DLL enabl e/disable, out put drive strength selection (opti onal), and QFC output

enable/disable (opt ional). These functions are controlled via the bits shown in the E xten ded Mod e Register

Definition. The Extended Mode Register is programmed via the Mode Regi ster Set command (with BA0 = 1

and BA1 = 0) and retains the st ored inform ation until it is programmed again or the device loses power. The

Extende d Mode Register must be loaded when all banks are idle, and the controller must wait t he spec ified

time before initiating any subsequent operat ion. Violating either of these requirements result in unspecified

operation.

DLL Enable/ Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and

upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The

DLL is automatically disabled when entering self refresh operation and is automatically re-enabl ed upon exit

of self refresh operation. Any time the DLL is enabled, 200 clock cycl es must occur before a Read command

can be issued. Thi s is the reason 200 clock cycl es must occur bef ore i ssuing a Read or Write c ommand upon

exit of self refresh operati on.

Outp ut D ri ve Strength

The normal drive strength for all ou tputs is specified to be SSTL_2, Class II. I-V curv es fo r the normal drive

strength are included in this document.

An option for weak driver support intended for lighter load and/ o r point-to-point environment s i s under consi d-

eration for future versions of th is design. Selection of the weak driver option wil l reduce the output drive

strength by ~ 55% of that of the nor mal strength.

QFC Enable/Disable (optional)

The QFC s ignal is an optional DRAM output control used t o isolate module loads (DIMMs) from the system

memory bus by means of FET switches when the given module is not being accessed. The QFC pin is

present on this product version, but all t imings param eters related to this pin are not tested on the final prod-

uct and are only guaranteed by design.

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256-Mbit Double Data Rate SDRAM

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Extended Mode Register Definition

A8A7A6A5A4A3A2A1A0Addr ess Bus

Drive Stre ng th

A1Drive Strengt h

0Normal

1reserved

BA1 BA0

Op er a tin g Mode

A11 A10 A9

0*1*

* BA0 and BA1 m ust be 1, 0 to select the Extended Mode Register

Mode Register

Extended

DS DLL

A0DLL

0 Enable

1 Disable

An - A3 A2 - A0 Operating Mode

0 Valid Normal O peration

−−All other states

Reserved

(vs. the base Mode Register)

QFC

A2QFC

0 Disable

1Enable

(Optional)

A12

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256-Mbit Double Data Rate SDRAM

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Truth Table 1a: Commands

Name (Function) CS RAS CAS WE Address MNE Notes

Deselect (Nop) H X X X X NOP 1, 9

No Operation (Nop) L H H H X NOP 1, 9

Active (Selec t Bank And Activate Row) L L H H Bank/Row ACT 1, 3

Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1, 4

Write (Select Bank And Co lumn, And Start Write Burst) L H L L Bank/Col Write 1, 4

Burst T erminate L H H L X BST 1, 8

Pr echarge (Deactivate Row In Bank Or Banks) L L H L C ode PRE 1, 5

Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR / SR 1, 6, 7

Mode Register Set L L L L Op-Code M RS 1, 2

1. CK E is HIG H f or all commands shown except Se lf Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0

selects Exten ded Mode R egister; other combinations of BA0-BA1 ar e reserved ; A0-A12 prov ide the op-c ode to be written to the

selected Mode Register.)

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Au to

Precharge feature (nonpersistent), A1 0 LOW disables the Auto Precharge feature.

5. A10 LO W: BA0, BA1 determine which bank is precharged.

A10 HIG H: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; S elf Refresh if CKE is LOW.

7. Intern al refresh counter controls row and bank addressing; all inputs and I/O s are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) f or read b ursts wit h

Auto Precharge enabled or for write bursts

9. Deselect and NOP are functi onally in terchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

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Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM

is effectively deselected. Operation s already in progress are not affected.

No Operation (NOP)

The No Operatio n (NOP) command is used to perform a NOP to a DDR SDRAM . This prevents unwanted

command s from being registered during idle or wait states . Operat ions already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode re gister descriptions in the Reg-

ister Definition section. The Mode Register Set command can only be issued when all banks are idle and no

bursts are in p ro gress. A subseque nt execut able com man d cannot be issued until tMRD is met.

Active

The Active command is used to open (or activate) a row i n a particular bank for a su bsequent access. The

value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.

This row remains act ive (or open) for a ccesses until a Precharge (or Re ad or Write with A uto Pre charge) is

issued to that bank. A Precharge (or Read or Wri t e with Auto Precharge) command must be issued and com-

pleted before opening a different row in the sam e bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,

BA1 inputs select s t he bank, and the address provided on inputs A0-Ai, Aj (wher e [i = 9, j = don’t care] for x8;

where [i = 9, j = 11] for x4) selects the starting colum n l ocation. The value on input A10 determines whether or

not Auto Precharge is used. If Auto Precharge is selected, the row being acc ess ed is precharged at the end

of the Read burst; i f Auto Precharge is not selected, the row remains open for subsequent accesses .

Write

The Write command is used to ini tiate a burst write access to an acti ve (open) row. The value on the BA0,

BA1 inputs select s t he bank, and the address provided on inputs A0-Ai, Aj (wher e [i = 9, j = don’t care] for x8;

where [i = 9, j = 11] for x4) selects the starting colum n l ocation. The value on input A10 determines whether or

not Auto Precharge is used. If Auto Precharge is selected, the row being acc ess ed is precharged at the end

of the Write burs t; if Auto Precharge is not selected, the row remains open for subsequent accesse s. Input

data appearing on the DQs is written t o the memory array subject to the DM input logi c level appearing coin-

cident with the data. If a gi ven DM signal is registered low, the corresponding data is written to memory; if the

DM signal is registered high, the c orrespondi ng data inputs are ignored, and a Write is not executed to that

byte/column locat ion.

Precharge

The Precharge comm and is used to deactivate (close) the open row in a particul ar bank or t he open row(s) in

all banks. The bank(s ) will be available for a subsequent row access a specified time (tRP) after the Precharge

command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be p re charged, inputs BA0, BA1 select the bank. Otherw ise BA0, BA1 are treated

as “Don’t C a r e .” Once a bank has been precharged, it is in the idle state and m us t be activated prior to any

Read or Write commands being issued to that bank. A precharge c ommand is treated as a NOP if there is no

open row in that bank, or if the previously open row is already in t he proces s of precharging.

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Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function desc ribed above,

but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharg e in

conjunction with a specific Read or Write c om m and. A precharge of the bank/row that is addressed with the

Read or Write command is aut omatically performed upon compl etion of t he Read or Write burst . Auto P re-

charge is nonpersistent in that it i s either enabled or disabled for each individual Read or Write c om m and.

Auto Prechar ge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must

not issue anot her command to the same bank until the precharge (tRP) is compl eted. This is determined as if

an explicit P rec harge comm and was issued at the earliest possible time, as d es cribed for each burst type in

the Operation section of this data sheet.

Burs t Te rmin ate

The Burst Terminate comman d is used to truncate read bursts (wit h Auto Prec harge disabled). The mo st re-

cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Opera-

tion secti on of this data sheet.

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is a nalogo us to C AS Before RAS

(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be is sued eac h time a

refresh is required.

The refresh addressing is generated by the internal refresh controll er. This makes the address bits “Don’t

Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Ref resh cycles at an aver-

age periodic interval of 7. 8µs (maximum ).

To allow for imp r oved efficiency in scheduling and switching between tasks, some flexibility in the absolute

refresh int erval is provided. A maxi mum of eight Auto Refresh commands can be posted in th e system,

meaning that the maximum absolute interval between any Auto Refres h command and the next Aut o Refr esh

command is 9 * 7.8 µs (70.2µs ). This maximum absolute interval is short enough to allow for DLL update s

internal to the DDR SDRAM to be restricted to Auto Refresh cycles, wi thout allowing too much drift in tAC

between updates .

Self Refresh

The Self Re fresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is

powered down. When in the se lf refresh mode, the DDR SDRAM retains data without external clocking. The

Self Refresh command is initiated as an Auto Refresh command coinci dent with CKE transitioning low. The

DLL is automatically disabled upon entering Sel f Refresh, and is automatically enabled upon ex iti ng Self

Refresh (200 cl ock cycl es must then occur before a Read comm and can be issued). Input signals except

CKE (low) are “Don’t Care” during Self Ref resh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable p rior to

CKE returning high. Once CKE is high, the SDRAM must have NOP commands iss ued for tXSNR because

time is required for the co mpletion of any internal refresh in progress. A sim pl e algorithm for meeting both

refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

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Operations

Bank/Row Activation

Before any Read or Write c om m ands can be issued to a bank within th e DDR SDRAM, a row in that bank

must be “opened” (activ at ed) . This is accom pl ished via t he Acti ve command and addresses A0-A12, BA0 and

BA1 (see Activating a Specific Row in a Spe cific Bank), which decode and select both the bank and the row

to be activated. Af te r opening a row (is suing an Active command), a Read or Wri te command may be issued

to that row, subject to the tRCD s pecificat ion. A subsequent Active command to a different row in the sam e

bank can only be issued after the previous active row has been “closed” (precharged). The minimum time

interval between success ive Active commands to the same bank is defined by tRC. A subsequent Act ive com-

mand to another bank can be issued while the first bank i s being accessed, which resu lts in a reduction of

total row-access overhead. The minimum time interval between suc cessive Active comma nds to diff erent

banks is defined by tRRD.

Activating a Specific Row in a Specific Bank

HIGH

RA = row address.

BA = bank address.

CKE

RAS

CAS

A0-A12

BA0, BA1 Don’t Care

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Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bur sts

are initiated with a Read comma nd, as shown on Read Command on page 19.

The starting colum n and bank addresses are provided with the Read command and Auto Precharge is either

enabled or disabled for that burst access. If Au to Precharge is enabled, the row that is a ccessed s tarts pre-

charge at the completion of the burst, provided tRAS has been satisfied. For the generic Read comm ands

use d in the following illustrat io ns , A uto Prec ha rg e is d is ab led.

During Read bursts, the valid data-out element from the starting column address is available following the

CAS latency after the Read command. Each subsequent data-out element i s valid nominally at the next posi-

tive or negative clock edge (i.e. at the next cross ing of CK and CK). Read Burst: CAS Latencies (Burst Length

= 4) on page 20 shows general timing for each supported CAS latency setting. DQS is driven by the DDR

SDRAM along with output data. The initial low stat e on DQS is known as the read pream ble; the low state

coincident with the last data-out element is known as the read postamble. Upon completion of a burst,

assuming no other comman ds have been initiated, the DQs goes High-Z. Data from any Read burst may be

concatenate d with or truncated with data fro m a subs equent Read co mmand. In either case, a continuous

flow of data can be m aintained . The first data element from the new burst follows e ither the last element of a

completed burst or the last desired data element of a longer burst which is being truncated. The new Read

command should be issued x cycles after the f irst Read comma nd, where x equals the number of desired

data element pairs (pairs are required by the 2n prefetch archi t ecture). This is shown on Consecutive Read

Bursts: CAS Latencies (Burst Length = 4 or 8) on page 21. A Read command can be initiated on any cl ock

cycle following a previous Read command. Noncons ecut ive Read data is illustrated on Non-Consecutive

Read Bursts: CAS Latencies (Burst Length = 4) on page 22. Full-speed Random Read Access es: CAS

Latencies ( Burst Length = 2, 4 or 8) wit hin a page (or pages) can be performed as shown on page 23.

tRCD and tRRD Definition

ROW

ACT NOP

COLROW

BA y BA yBA x

ACT NOP NOP

Command

A0-A12

BA0, BA 1

Don’t Care

RD/WR

tRCD

tRRD

RD/WR NOP NOP

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Read Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9 EN AP

DIS AP

EN AP = enab le Auto Precharge

DIS AP = disable Auto Precharge

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Read Burst: CAS Latencies (Burst Length = 4)

CAS Latency = 2

NOP NOP NOP NOP NOPRead

Command

Address

DQS

CAS Latency = 2.5

Don’t Care

BA a,COL n

DOa-n

CL=2.5

NOP NOP NOP NOP NOPRead

Command

Address

DQS

BA a,COL n

DOa-n

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with no minal tAC, t DQSCK, and tDQSQ.

CL=2

QFC

tQPRE tQPST

(Optional)

tQPST

(Optional)

tQPRE

QFC is an open drain driver. Th e output high level is achieved through an ex ternal pul l up resistor connected to VDDQ.

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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

NOP Read NOP NOP NOPRead

Command

Address

DQS

CL=2

BAa, COL n BAa, COL b

Don’t Care

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst le ngth = 4, the bursts are concatenat ed.

When bur s t length = 8, the second bur st interrupts t he fir s t.

3 s ubseq uent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subse quent elements of data out appear in the programmed order following DO a-b.

Shown with nominal tAC, tDQSCK, an d tDQSQ.

CAS Latency = 2.5

NOP Read NOP NOP NOPRead

Command

Address

DQS

CL=2.5

BAa, COL n BAa,COL b

DOa-n

DOa- n DOa- b

DOa-b

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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

CAS Latency = 2

NOP NOP Read NOP NOPRead

Command

Address

DQS

DQ DO a-n DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 s ubseq uent elements of data out app ear in the pr ogrammed or der following DO a-n (and following DO a-b) .

Sh ow n wi th no mi nal tAC, tDQSCK, and tDQSQ.Don’t Care

BAa, COL n BAa, COL b

CL=2

CAS Latency = 2.5

NOP NOP Read NOP NOPRead

DO a-n DOa- b

BAa, COL n BAa, COL b

CL=2.5

Command

Address

DQS

NOP

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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

DOa-n

CAS Latency = 2

Read Read Read NOP NOPRead

DOa-bDOa-n’DOa-x DOa-x’DOa-b’DOa-g

Command

Address

DQS

DO a-n, etc. = data out from bank a, column n etc.

n’ etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Shown with nominal tAC, tDQSCK, and tDQSQ.

Don’t Care

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2

DOa-n

CAS Latency = 2.5

Read Read Read NOP NOPRead

DOa-bDOa-n’DOa-x DOa-x’DOa-b’

Command

Address

DQS

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2.5

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Data from any Read burst may be truncated with a Burst Terminate command, as shown on Terminat ing a

Read Burst: CAS Latencies (Burst Length = 8) on page 25. The Burst Terminate latency is equal to the read

(CAS) latency, i.e. the Burst Terminate command shoul d be issued x cycles afte r the Read comm and, where

x equals the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write comm and c an be

issued. If tr uncation is necessary, the Burst Terminate command must be used, as shown on Read to Write:

CAS Lat encies (Bu rst Length = 4 or 8) on page 26. The example is shown for tDQSS(min). The tDQSS(max)

case, not shown her e, has a longer bus idle t i me. tDQSS(m in) and tDQSS(max) are defi ned in the section on

Writes.

A Read burst may be followed by, or trunc ated with, a Precharge comm and to the same bank (provided that

Auto Precharge was not activa ted). The Precharge command should be issued x cycles after the Read com -

mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefet c h archi-

tecture). This is shown on Read to Precharge: CAS Latenc ies (Burst Length = 4 or 8) on page 27 fo r Read

latencies of 2 and 2.5. Following the Precharge command, a subsequent comm and to the sam e bank cannot

be issued until tRP i s met. Not e that part of the row precharge time is hidden during the ac cess of the last data

elements.

In the case of a Read be ing exec ute d to completion, a Precharge comm and issued at the optimum time (as

described above) provides the same operat ion that would result from t he sam e Read burst with Auto P re-

charge enabled. Th e disadvant age of the Precharge com ma nd is that it requires that the comma nd and

address bus ses be avai lable at the appropriate time to issue the command. The advantage of the Precharge

command is that it can be us ed to truncate bursts.

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Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CAS Latency = 2

NOP BST NOP NOP NOPRead

Command

Address

DQS

DO a-n = dat a ou t fr om ban k a, co lu m n n.

Cases shown are bursts of 8 ter minated after 4 data elements.

3 subseq uent elements of data out app ear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.

DOa-n

Don’t Care

BAa, COL n

CL=2

CAS Latency = 2.5

NOP BST NOP NOP NOPRead

Command

Address

DQS

DQ DOa-n

BAa, COL n

CL=2.5

No further output data after this point.

DQS tristated.

No further output data after this point.

DQS tristated.

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Read to Write: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

BST NOP Write NOP NOPRead

DI a-b

Command

Address

DQS

DOa-n

DO a-n = data out from ban k a, colum n n

1 subseq uent elements of data out appear in the programmed order follow ing DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length. Don’t Care

BAa, COL n BAa, COL b

CL=2 tDQSS (min)

CAS Latency = 2.5

BST NOP NOP Write NOPRead

Command

Address

DQS

DOa-n

BAa, COL n BAa, COL b

CL=2.5 tDQSS (min)

Dla-b

Show n wit h nominal tAC, tDQSCK, and tDQSQ.

DI a-b = data in to bank a, column b

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Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 s ubseq uent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.Don’t Care

BA a, COL n BA a or all BA a, ROW

CL=2.5

CAS Latency = 2.5

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

tRP

BA a, COL n BA a or all BA a, ROW

CL=2

tRP

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Writes

Write bursts ar e initiated wit h a Write command, as shown on Write Command on page 29.

The start ing column and bank addresses are provided with t he Write command, and Auto Prechar ge is either

enabled or disabled for that access. If A uto P rech arge is enabled, the row being accessed is precharged at

the compl etion of the burst. For the generic Write commands used i n the f ollowing illustrations, A uto Pre-

charge is disabled.

During Write bursts, t he first valid data-in element is registered on t he first rising edge of DQS following the

write command, and subseq uent data elements are registered on successive edge s of DQS. The Low state

on DQS between the Write command and t he first rising ed ge is known as the writ e pream ble; the Low state

on DQS followi ng the last data-in el em ent is known as the write postamble. The time between the Write com -

mand and the first corresponding rising edge of DQS (tDQSS) is specifie d with a relatively wide range (from

75% t o 125% of one cloc k cycle), so most of the Write diagrams that follow are drawn for the two extreme

cases (i.e. tDQSS(min) and tDQSS(max)). Write Burst (Burst Length = 4) on page 30 shows the two extremes of

tDQSS for a burst of four. Upon completion of a burst, assuming no other commands hav e been initiated, the

DQs and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Wri te command. In either

case, a continuous flow of input data can be maintained. T he new Write command can be i ssued on any pos-

itive edge of c lock f ollowing the previous Write command. The first data element from the new burst is applied

after either t he last eleme nt of a completed burst or t he last desired data elemen t of a longer burst whi ch is

being truncated. The new Write comma nd sho uld be issued x cycles after the first Write comman d, where x

equals the num ber of desired data element pairs (pairs are required by the 2n prefetch archi tecture). Write to

Write (Burst Length = 4) on page 31 shows concatenated bursts of 4. An ex ample of non-consecutive Wri tes

is shown on W rite to Writ e: Max DQSS, Non-Consecutive (Burst Length = 4) on page 32. Full-speed random

write accesses within a page or pages can be performed as shown on Random Wri te Cycles (Burst Length =

2, 4 or 8) on page 33. Data for any Write burst may be followed by a subsequent Read com mand. To follow a

Write without truncating the write burst, tWTR (Write to Read) should be met as shown on Write to Read: Non-

Interrupting (CAS Latency = 2; Burst Length = 4) on page 34.

Data for any Write burst may be truncat ed by a subsequent Read command, as shown in the figures on Write

to Read: I nterrupting (CAS Latency = 2; Burst Length = 8) on page 35 to Write to Read: Nominal DQSS, Inter-

rupting (CAS Latency = 2; Burst Length = 8) on page 37. Note that only the data-in pairs that are registered

prior to t he tWTR p eriod are written to the i nternal array, and any subsequent data-in must be masked with

DM, as shown in the diagrams noted previousl y.

Data for any Write burst may be foll owed by a subsequent Precharge command. To follow a Write without

truncating the write burst, tWR should be met as shown on Write to Precharge: Non-I nterrupting (B urst Length

= 4) on page 38.

Data for any Write burst may be t runcated by a subsequent P recharge command, as shown in the figures on

Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 39 to Write to Precharge: Nominal DQSS (2

bit Write), Interrupt ing (Burst Length = 4 or 8) on page 41. Not e that only the data-in pairs t hat are registered

prior to t he tWR period are writte n to the internal array , and any subseque nt data in should be masked with

DM. Following the Precharge command, a subsequent command to the same bank cannot be i ssued until tRP

is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the opti mum time

(as described above) provides the same operation that would result from the same burst with Aut o Pre -

charge. The disadvant age of the Precha rge comm and is that it requires that th e comm and and addres s bus -

ses be available at the appropr iate time to issue the command. The advantage of the Precharge command is

that it c an be used to truncate bursts.

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Write Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8 EN AP

DIS AP

EN AP = enab le Auto Prech arge

DIS AP = disable Auto Pr echarge

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Write Burst (Burst Length = 4)

T1 T2 T3 T4

tDQSS (ma x)

NOP NOP NOPWrite

DI a-b = data in for bank a, column b.

3 subse quent elements of data in are applied in the programmed order following DI a-b.

A non-i nterrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

Maximum DQSS

BA a, COL b

T1 T2 T3 T4

tDQSS (min)

NOP NOP NOPWrite

Command

Address

DQS

Minimum DQSS

BA a, COL b

Dla-b

QFC tQCK(max) tQOH(min)

(Optional)

QFC tQCK(max) tQOH(max)

QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to VDDQ.

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Write to Write (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP Write NOP NOP NOPWrite

DI a-b = data in for bank a, column b, etc.

3 subse quent elements of data in ar e applied in the programmed order f ollowing DI a-b.

3 subse quent elements of data in ar e applied in the programmed order f ollowing DI a-n.

A non-i nterrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP Write NOP NOP NOPWrite

Command

Address

DQS

BAa, COL b BAa, COL n

BA, COL b BA, COL n

tDQSS (min)

DI a-b DI a-n

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Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

T1 T2 T3 T4 T5

tDQSS (max)

NOP NOP Write NOPWrite

DI a -b, etc. = data in for bank a, column b, etc.

3 subseq uent elements of data i n are applied in th e progr ammed order following DI a-b.

3 subseq uent elements of data i n are applied in th e progr ammed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

DI a-b DI a-n

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Random Write Cycles (Burst Length = 2, 4 or 8)

T1 T2 T3 T4 T5

tDQSS (max)

Maximum DQSS

Write Write Write Write

Write

DI a-b DI a-n

DI a-b, etc. = data in for bank a, column b , etc.

b’, etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

DI a-b’DI a-x DI a-x’DI a-n’DI a-a DI a-a’

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL x BAa, COL n BA a , COL a BAa, COL g

T1 T2 T3 T4 T5

Minimum DQSS

Write Write Write Write

Write

DI a-b DI a-nDI a-b’DI a-x DI a-x’DI a-n’DI a-a DI a-a’

Command

Address

DQS

BAa, COL b BAa, COL x BAa, COL n BA a , COL a BAa, COL g

tDQSS (min)

DI a-g

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Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

CL = 2

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite

DI a-b

NOP

DI a-b = data in for bank a, column b.

3 s ubseq uent elements of data in are applied in the programmed order f ollowing DI a-b.

A non-i nterrupted burst is shown.

tWTR is refere nced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

The R ead and Wri te commands may be to any bank.

Command

Address

DQS

Don’t Care

Maximum DQSS

BAa, COL b BAa, COL n

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite NOP

Command

Address

Minimum DQSS

BAa, COL b BAa, COL n

tDQSS (ma x)

DI a-b

DQS

tDQSS (min)

CL = 2

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Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP NOP NOP ReadWrite NOP

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from th e first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands ar e not necessarily to the s ame bank.

DIa- b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 2

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 2

tDQSS (min)

1 = These bits are incorrectly written into the memory arra y if DM is low.

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Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interru pting (CAS

Latency = 2; Bu rst Length = 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are writte n.

2 subseq uent elements of data i n are applied in th e programme d order following DI a-b.

tWTR is referenced from the first positive CK edge afte r the last desired data in pair (not the last desired data in element)

The R ead comman d masks the last 2 data elements in the burst.

A10 is Low with the Write com m and (A uto Pr echarge is disabled) .

The Read and Write commands are not necessarily to the same bank.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 2

tDQSS (min)

DM 122

1 = This bit is correctly written into the memory array if DM is low.

2 = These bits are incorrec tly written into the memory array if DM is low .

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Write to Read: Nominal DQS S, Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (no m )

NOP NOP NOP ReadWrite NOP

DI a-b = data in for ban k a, co lu mn b.

An interrupted burst is shown, 4 data elements are written.

3 s ubseq uent elements of data in are applied in the programmed order f ollowing DI a-b.

tWTR is referenced from the first positive CK edge after the last desi red data in pair.

The R ead comman d masks the last 2 data elements in the burst .

A10 is Low with the Write command (Auto Precharge is disabled).

The R ead and Wri te commands are not neces sarily to the same bank.

DI a-b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 2

1 = These bits are incorrectly written into the memory array if DM is low.

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Write to Precharge: Non-Interrupting (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max )

NOP NOP NOP NOPWrite

DI a-b

PRE

DI a-b = data in for ban k a, column b.

3 subsequent elements of data in are a pplied in the programm ed order fo llowing DI a-b .

A non-int erru pted burst is shown.

tWR is referenced from the first positive CK edge after the last data in pair.

A10 is Low with t he Writ e comm and (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

BA a, COL b BA (a or al l)

tWR

Maximum DQSS

T1 T2 T3 T4 T5 T6

NOP NOP NOP NOPWrite PRE

Command

Address BA a, COL b BA (a or all)

tWR

Minimum DQSS

DI a-b

DQS

tDQSS (min)

tRP

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Write to Precharge: Interrupting (Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 s ubseq uent element of data in is applied in the programmed ord er following DI a-b.

tWR is referenced from the first positive CK edge after the las t desired da ta in pair.

The Prec harge command masks the last 2 data el emen ts in the burst, for burst length = 8.

A10 is Low with the Wri te command (Auto Precharge is disabl ed).

1 = Can be don’t car e for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don’t care at this point. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address

Maximum DQSS

DI a-b

DQS

tDQSS (max) tRP

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

Minimum DQSS

tWR

tRP

DI a-b

DQS

tDQSS (min) 2

BA a, COL b BA (a or all)

tWR

3 = These bits are in cor re ctl y written in to the memor y array if DM is low.

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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write) , Interruptin g

(Burst Length = 4 or 8)

DI a-b = data in for ban k a, co lu mn b.

An interrupted burst is shown, 1 data element is written.

tWR is referenced from the first positiv e CK edge after the last desired data in pair.

The Prec harge command masks the last 2 data el ements in the bur s t.

A1 0 is Lo w wit h the Wr ite com m an d ( Au t o Prechar g e is disa bled) .

1 = Can be don’t care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don’t ca re at thi s poin t.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or al l)

tWR

tRP

DI a-b

DQS

tDQSS (min) 2

DM 344

3 = This bit is cor rectly wr itten into the memo ry array if DM is lo w.

4 = These bits are incorrectly written into the memory array if DM is low.

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Write to Precharge: Nom inal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 s ubseq uent element of data in is applied in the programmed ord er following DI a-b.

tWR is referenced from the first positive CK edge after the las t desired da ta in pair.

The Precharge command masks the last 2 data elemen ts in the burs t.

A10 is Low with the Wri te command (Auto Precharge is disabl ed).

1 = Can be don’t care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don’t ca re at th is poin t. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address

BA a, COL b BA (a or all)

tRP

tDQSS (nom)

DI a-b

DQS

DM 1

tWR

3 = These bits are incorrectly written into the memory array if DM is low.

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Precharge

The Precharge command i s used to deactivate the open row in a particular bank or the open row in all banks.

The bank(s) will be available for a subsequent row access some specified time (tRP) after the Precharge com-

mand is issued. Input A10 determi nes whether one or all banks are to be precharged, and in the c ase where

only one bank is to be p re charged, inputs BA0, BA1 select the bank. When all banks are to be precharged,

inputs BA0, BA1 are treated as “Don’t Car e .” Once a bank has been precharged, it is in the idl e state and

must be activated prior to any Read or W rite comma nds being issued to that bank.

Precharge Command

HIGH

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

All Banks

One Ban k

(if A1 0 is Low, otherwise Don ’t Care).

A0-A9, A11, A12

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Power-Down

Power-down is entered when CKE is regist ered LOW (no accesses can be in progress). If power-down

occurs when all banks are idle, this mode is referred to as prec harge power-down ; if power-down occurs

when there is a row a ctive in any bank, this m ode is referred to as acti v e power-down. Entering power-dow n

deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down

mode, so for maximum power savings, the user has the option of disabli ng the DLL prior to entering P ower-

down. In tha t case, the DLL m ust be enabled after exiting power-down, and 200 cl ock cycles must occur

before a Read command can be issued . In power-down mode , CKE Low and a stable clock signal must be

maintained at the inputs of th e DDR SDRAM, and all other input sign als are “Don’t Car e ”. However, power-

down duration is limited by the ref resh requirem ents of the device, so in m os t applications, the self refresh

mode is preferred over the DLL-disabled power-down mode.

The power -down state is synchronously exited when CKE is regist ered HIGH (along with a Nop or Desel ect

command ). A valid, executable command may be applied one clock cy cle later.

Power Down

tIS

CKE

Command

No column

access in

progress

VALID NOP VALID

Don’t Care

Exit

power down

mode

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

NOP

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Truth Table 2: Clock Enable (CKE )

1. CKEn is the logic stat e of CKE at clock edge n: CKE n-1 w as the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediate ly prior to clock edge n.

3. COMM AND n is the c omman d registered at c lo ck edge n, and ACTION n is a res ul t of COMMAND n.

4. All states and sequences not sho wn are i l legal or reserved.

Current State

CKE n-1 CKEn

Command n Action n Notes

Cycle Current

Cycle

Se lf Ref r es h L L X Main ta in Se lf-Refre s h

Self Refresh L H Deselect or NOP Exit Self-Refresh 1

Power Down L L X Mai ntain Power-Down

Power Down L H Deselect or NOP Exit Power-Down

All Ban ks Idle H L Deselect or NOP Precharge Power-Down Entry

All Ban ks Idle H L AUTO REFRESH Self Refresh Entry

Bank(s) Active H L Dese lect or NOP Active Power-Down Entry

See “Tru th Tabl e 3: C urrent State

Bank n - Command to Bank n

(Same Bank)” on page 45

1. Deselec t or NOP command s should be issued on a ny clock edges occur ring du ring the Self Refresh Exit (tXSNR) period. A mini-

mum of 200 clock cycles are nee ded before applying a re ad comm and to allow the DLL to lock to the input clock.

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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) (Part 1 of 2)

Curre nt State CS RAS CAS WE Command Action Notes

Any H X X X Deselect NOP. Continue previous operation 1-6

L H H H No Operation NOP. Continue previous operation 1-6

Idle

L L H H A c tive Select and activate row 1-6

LLLH AUTO REFRESH 1-7

L L L L MODE REGISTER SET 1-7

Row Active

L H L H Read Select column and start Read burst 1-6, 10

L H L L Write Select column and start Write burst 1- 6, 10

L L H L Precharge Deactivate r ow in bank( s ) 1-6, 8

Read

(A uto P re ch arg e

Disabled)

L H L H Read Select column and start new Read burst 1- 6, 10

L L H L Prechar ge Truncate Rea d burst, start Precha rge 1-6, 8

L H H L BURST TERMINATE BURS T TERMINATE 1-6, 9

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD

has been met (if the previou s state was self refresh) .

2. This table is bank-specific, except where noted, i.e ., the current state is for a specific bank and the comma nds shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP ha s been met.

Row Active: A row in the bank has been activated, and tRCD has bee n me t . No da ta bu r st s/ a c ce s se s and no re gis te r

acc esses are in progress.

Read: A Rea d burst has been initi ated, with Auto Precharge disabled, and has not yet t erminated or be en terminated.

Write: A Wr ite burst has been init iated, with Aut o Precharge disabled, and has not yet terminated or been term inated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging: Starts wit h registration of a Precharg e command and ends wh en tRP is met. O nc e tRP is met, the bank is in the

idle state.

Row Activating: Starts with r egis trati on of an Acti ve comm and and ends when t RCD is met. Once tRCD is met, the bank is in the

“row active” state.

Read w/Auto Precharge Enabled: Starts with registrati on of a Re ad com mand with Auto Precharge enabled and ends when tRP

has been met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharg e Enabled: Starts with registration of a Write comman d with Auto Precharge enabled and ends wh en tRP

has been met. Once tRP is met, the bank is in the idle state.

Des el ec t or NOP co mma nds , o r allo w ab l e c omm and s to t he othe r ba nk s houl d b e is su ed on a n y cl oc k ed ge oc c urring du ri ng th es e

states. Allowable commands to the other b ank are determined by its current state and according t o Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each

positive clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. O nce tRFC is met, the DDR

SDRAM is in th e “all ba nk s idle ” state.

Accessing Mode Register: Starts w ith r egistr ation of a Mode Register Set co mmand and ends when tMRD has been met. Once

tMRD is met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in

the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires tha t all banks are idl e.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for pre charging.

9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed i n the Command/Action column include Reads or Writes wit h Auto Precharge enabled and Rea ds or Writes

with Auto Precharge disabled.

11. Requi res approp riate DM masking.

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Write

(A uto P re ch arg e

Disabled)

L H L H Read Select column and start Read burst 1-6, 10 , 11

L H L L Write Select column and start Write burst 1- 6, 10

L L H L Prechar ge Truncate Wri te burst, s tart Precharge 1-6, 8, 11

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) (Part 2 of 2)

Curre nt State CS RAS CAS WE Command Action Notes

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD

has been met (if the previou s state was self refresh) .

2. This table is bank-specific, except where noted, i.e ., the current state is for a specific bank and the comma nds shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP ha s been met.

Row Active: A row in the bank has been activated, and tRCD has bee n me t . No da ta bu r st s/ a c ce s se s and no re gis te r

acc esses are in progress.

Read: A Rea d burst has been initi ated, with Auto Precharge disabled, and has not yet t erminated or be en terminated.

Write: A Wr ite burst has been init iated, with Aut o Precharge disabled, and has not yet terminated or been term inated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging: Starts wit h registration of a Precharg e command and ends wh en tRP is met. O nc e tRP is met, the bank is in the

idle state.

Row Activating: Starts with r egis trati on of an Acti ve comm and and ends when t RCD is met. Once tRCD is met, the bank is in the

“row active” state.

Read w/Auto Precharge Enabled: Starts with registrati on of a Re ad com mand with Auto Precharge enabled and ends when tRP

has been met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharg e Enabled: Starts with registration of a Write comman d with Auto Precharge enabled and ends wh en tRP

has been met. Once tRP is met, the bank is in the idle state.

Des el ec t or NOP co mma nds , o r allo w ab l e c omm and s to t he othe r ba nk s houl d b e is su ed on a n y cl oc k ed ge oc c urring du ri ng th es e

states. Allowable commands to the other b ank are determined by its current state and according t o Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each

positive clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. O nce tRFC is met, the DDR

SDRAM is in th e “all ba nk s idle ” state.

Accessing Mode Register: Starts w ith r egistr ation of a Mode Register Set co mmand and ends when tMRD has been met. Once

tMRD is met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in

the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires tha t all banks are idl e.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for pre charging.

9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed i n the Command/Action column include Reads or Writes wit h Auto Precharge enabled and Rea ds or Writes

with Auto Precharge disabled.

11. Requi res approp riate DM masking.

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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Curre nt State CS RAS CAS WE Command Action Notes

Any H X X X Deselect NOP/continu e previous operation 1-6

L H H H No Operation NOP/continue pr evi ous op eration 1-6

Idle XXXX

Any C omman d Othe rwis e

Allowed to Bank m 1-6

Row Activa ting,

Active, or

Precharging

L L H H Active Select and activate row 1-6

L H L H Read Select column and start Read burst 1-7

L H L L Write Select column and start Write burst 1-7

L L H L Precharge 1-6

Read

(A uto P re ch arg e

Disabled)

L L H H Active Select and activate row 1-6

L H L H Read Select column and start new Read burst 1-7

L L H L Precharge 1-6

Write

(A uto P re ch arg e

Disabled)

L L H H Active Select and activate row 1-6

L H L H Read Select column and start Read burst 1-8

L H L L Write Select column and start new Write burst 1-7

L L H L Precharge 1-6

Read (With

Auto Precharge)

L L H H Active Select and activate row 1-6

L H L H Read Select column and start new Read burst 1-7,10

L H L L Write Select column and start Write burst 1-7,9,10

L L H L Precharge 1-6

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD

has been met (if the previou s state was self refresh) .

2. This table describes alterna te bank operati on, except where not ed, i.e., the current state is for bank n an d the commands shown

are those allowed to be issued t o bank m (assuming that b ank m is in such a state that the given command is allowable). Excep-

ti on s are covere d in th e notes bel ow.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register

acc esses are in progress.

Read: A Read b urst has been initiat ed, wi th Aut o Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated , w ith Auto Precharge disabl ed, and has not yet term inated or been te rminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. AUTO REFRESH and Mode R egister Set commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Write s listed in the Command/Acti on column include Reads o r Writes with Auto Precharge enabled and R eads or Writes

with Auto Precharge disabled.

8. Requi res appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. Concurrent Auto Precharge:

Thi s devi ce sup po rt s “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any

command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other

limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum dela y from a read or write

command wi th auto prec harge enable , to a command to a different banks is summariz ed in table 4a.

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Truth Table 4a : Concurrent Auto Precharge:

Write (With

Auto Precharge)

L L H H Active Select and activate row 1-6

L H L H Read Select column and start Read burst 1-7,10

LHLL Write Sele ct co lu mn and start ne w Write bur st 1-7,10

L L H L Precharge 1-6

From Command To Command

(different bank)

Minimum Delay with Con-

cur rent Auto P rec ha r g e

Support Units

WRITE w/AP

Read or Read w/AP 1 + (B L/2) + tWTR tCK

Wri te ot Wri t e w/ AP BL /2 t CK

Precharge or Activate 1 tCK

Read w/AP

Read or Read w/AP BL/2 tCK

Wri te or Write w/A P C L (r ou nd ed up) + BL/ 2 tCK

Precharge or Activate 1 tCK

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)

Curre nt State CS RAS CAS WE Command Action Notes

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD

has been met (if the previou s state was self refresh) .

2. This table describes alterna te bank operati on, except where not ed, i.e., the current state is for bank n an d the commands shown

are those allowed to be issued t o bank m (assuming that b ank m is in such a state that the given command is allowable). Excep-

ti on s are covere d in th e notes bel ow.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register

acc esses are in progress.

Read: A Read b urst has been initiat ed, wi th Aut o Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated , w ith Auto Precharge disabl ed, and has not yet term inated or been te rminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. AUTO REFRESH and Mode R egister Set commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Write s listed in the Command/Acti on column include Reads o r Writes with Auto Precharge enabled and R eads or Writes

with Auto Precharge disabled.

8. Requi res appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. Concurrent Auto Precharge:

Thi s devi ce sup po rt s “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any

command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other

limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum dela y from a read or write

command wi th auto prec harge enable , to a command to a different banks is summariz ed in table 4a.

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

Page 49 of 72 3/01

Sim plified State Diagram

Self

Auto

Idle

MRS

EMRS

Row

Precharge

Power

Write

Power

ACT

Read A

Read

REFS

REFSX

REFA

CKEL

MRS

CKEH

CKEL

Write

Power

Applied

Automatic Sequence

Command Sequence

Read A

Write A

Read

PRE PRE

PRE

Refresh

Down

Power

Down

Active

Read

Write A

Bur st Stop

PREALL

Active Precharge

Precharge

PREALL

Read

Write

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register S et

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

Page 50 of 72 3/01

Ab solu te Maximu m Rating s

Symbol Parameter Rating Units

VIN, VOUT Volta ge on I/O pins relative to VSS −0 .5 to VDDQ+ 0.5 V

VIN Voltage on Inputs relative to VSS −0.5 to +3.6 V

VDD Voltage on VDD supp ly relative to VSS −0.5 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS −0.5 to +3.6 V

TAOpera ting Temper ature (Ambient) 0 to +70 °C

TSTG Storage Temperature (Plastic) −55 to +150 °C

PDPower Dissipation 1.0 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of th e device at these or any other condit ions above those indicated in the operational sec-

tions of this sp ecification is not implied. Exposure to ab solute maximum rating conditions for extended peri ods may affect reliability.

HYB25D256400/800T/AT

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Page 51 of 72 3/01

Capacitance

Parameter Symbol Min. Max. Units Notes

Input Capacitance: CK, CK CI1 2.0 3.0 pF 1 ,3

Input Capacitance: All other input-only pins ( except DM) C I2 2.0 3 .0 pF 1, 3

Input/Output Capacitance: DQ, DQS, DM CIO 4.0 5.0 pF 1, 2, 3

Output Capacitan ce: QFC CO12. 0 4 .0 pF 1, 3

Delta Input capacitance for DQ, DQS, DM ∆C-0.5pF3

De lta Input ca pa cita nc e for CK , C K ∆C-0.25pF3

1. VDDQ = V DD = 2.5V ± 0.2V, f = 100MHz, TA = 25°C, V OUT (DC) = VDDQ/2,

VOUT (Peak to Peak) = 0.2V.

2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching

at the board level.

3. All capacitances are guaranteed by design and are tested on a samples basis only.

Electrical Characteristics and DC Operating Conditions

(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Character istics)

Symbol Parameter Min Max Units Notes

VDD Supply Voltage 2.3 2.7 V 1

VDDQ I/O Supply Voltage 2.3 2.7 V 1

VSS, VSSQ Su pply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Refere nce Voltage 0.49 x VDDQ 0.51 x VDDQ V1, 2

VTT I/O Termination Voltage (System) VREF − 0.04 VREF + 0.04 V 1, 3

VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1

VIL(DC) Input Low (Logic0) Voltage − 0.3 VREF − 0.15 V 1

VIN(DC) Input Voltage Level, CK and CK Inputs − 0.3 VDDQ + 0.3 V 1

VID(DC) Input Differential Voltage, CK and CK Inputs 0.3 VDDQ + 0.6 V 1 , 4

VIRatio VI-Matching Pullup Current to Pulldown Current 0.71 1.4 5

IIInput Leakage Current Any input 0V ≤ VIN ≤ VDD

(All o ther pins not under test = 0V) − 22µA1

IOZ Output Leakage Current (DQs are disabled; 0V ≤ Vout ≤ VDDQ) − 55µA1

IOH Output High Current, Normal Strength Driver

(VOUT = VDDQ - 0.373V, min VR EF,m in VTT) − 16.8 mA 1

IOL Output Low Current, Normal Strength Driver

(VOUT = 0.373V, max VREF, max. VTT) 16.8 mA 1

1. Inputs are not recognized as valid until VREF stabil izes.

2. VREF is expected to be equal to 0.5 VDDQ of the tran smitting device, and to track variations in the DC level of the same. Peak-to-

peak noi s e on VREF may not exceed ± 2% of the DC value.

3. VTT is not appli ed dir ec tly t o th e de v ice . VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC le v e l of VREF

4. VID is the magnit ude of the diff erence betwee n the input level on CK and the input level on CK.

5. The ratio n of the pullup cur rent to the pulldown current is specified for the same temperature and voltage, o ve r the entire tempera-

ture and voltage range, for device drai n to source volt age from 0.2 5 to 1.0V. For a given output, it repr esents the maximum differ-

ence between pullup and pulldown drivers due to process variation.

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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Pulld own and Pullup Characteristics

1. The nominal pull down V-I curve f or DDR SDRAM de vices is e xpected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

2. The full variation in driver pul ldown c urrent from minim um to maximum process , temperature, and voltage

lie within the o ute r bounding lines of the V-I curve.

3. The nominal pullup V-I cur ve for DDR SDRAM devices is expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve.

4. The full variation in driver pullup current from minimum to maximum process, temperatur e, and volt age l ie

within the outer bounding lines of t he V-I cur ve.

5. The full vari ation in the ratio of the m aximum to minimum pullup and pulldown current does not exc eed

1.7, for device d rain to s ou rce voltages from 0.1 to 1. 0.

6. The full vari ation in the ratio of the nom inal pullup to pulldown current sh ould be unity ± 10%, for device

drain to source voltage s from 0.1 to 1.0V.

Pulldown Characteristics

Pullup Characteristics

00.5 1 1.5 2 2.50

100

120

140

OUT

(m A)

VOUT (V)

Maximum

Nominal High

Nominal Low

Minimum

Maximum

Nomi nal High

Nomi nal Low

Minimum

VOUT (V)

0.5 1 1.5 2 2.50

-20

-40

-60

-80

-100

-120

-140

-160

OUT

(mA)

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Page 53 of 72 3/01

The above characteristics are specified under best, worst, and nominal process variations / conditions.

Pulldown and Pullup Currents

Pulldown Current (mA) Pullup Curren t (mA)

Vol tag e ( V) Nominal

Low Nominal

High Min Max Nominal

Low Nominal

High Min Max

0.16.06.84.69.6

−6.1 −7.6 −4.6 −10.0

0.2 12.2 13.5 9.2 18.2 −12.2 −14.5 −9.2 −20.0

0.3 18.1 20.1 13.8 26.0 −18.1 −21.2 −13.8 −29.8

0.4 24.1 26.6 18.4 33.9 −24.0 −27.7 −18.4 −38.8

0.5 29.8 33.0 23.0 41.8 −29.8 −34.1 −23.0 −46.8

0.6 34.6 39.1 27.7 49.4 −34.3 −40.5 −27.7 −54.4

0.7 39.4 44.2 32.2 56.8 −38.1 −46.9 −32.2 −61.8

0.8 43.7 49.8 36.8 63.2 −41.1 −53.1 −36.0 −69.5

0.9 47.5 55.2 39.6 69.9 −43.8 −59.4 −38.2 −77.3

1.0 51.3 60.3 42.6 76.3 −46.0 −65.5 −38.7 −85.2

1.1 54.1 65.2 44.8 82.5 −47.8 −71.6 −39.0 −93.0

1.2 56.2 69.9 46.2 88.3 −49.2 −77.6 −39.2 −100.6

1.3 57.9 74.2 47.1 93.8 −50.0 −83.6 −39.4 −108.1

1.4 59.3 78.4 47.4 99.1 −50.5 −89.7 −39.6 −115.5

1.5 60.1 82.3 47.7 103.8 −50.7 −95.5 −39.9 −123.0

1.6 60.5 85.9 48.0 108.4 −51.0 −101.3 −40.1 −130.4

1.7 61.0 89.1 48.4 112.1 −51.1 −107.1 −40.2 −136.7

1.8 61.5 92.2 48.9 115.9 −51.3 −112.4 −40.3 −144.2

1.9 62.0 95.3 49.1 119.6 −51.5 −118.7 −40.4 −150.5

2.0 62.5 97.2 49.4 123.3 −51.6 −124.0 −40.5 −156.9

2.1 62.9 99.1 49.6 126.5 −51.8 −129.3 −40.6 −163.2

2.2 63.3 100.9 49.8 129.5 −52.0 −134.6 −40.7 −169.6

2.3 63.8 101.9 49.9 132.4 −52.2 −139.9 −40.8 −176.0

2.4 64.1 102.8 50.0 135.0 −52.3 −145.2 −40.9 −181.3

2.5 64.6 103.8 50.2 137.3 −52.5 −150.5 −41.0 −187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

Pul ld own a nd P ul lu p P rocess Vari at i ons and Con di tio ns

Nominal Minimum Maximum

Operating Temperature 25 °C0 °C70 °C

VDD / VDDQ 2.5V 2.3V 2.7V

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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AC Characteristics

(Notes 1-5 apply to the following Tables; Elect rical Charact eristics and DC Operating Conditions, AC Operating

Condit ions, IDD Specifications and Condi tions, and Electrical Characteristics and AC Timing. )

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be con ducted at nominal ref erence/supply

volt age levels, but the related specificat ions and device operation are guaranteed for the full volta ge range specified.

3. The fi gure below r epresents the timing reference load used ind efi ning the relevant t iming paramet ers of the part. It i s

not in tended to be ei ther a prec ise represen tat ion of the typi cal sys tem enviro nment nor a de pi ction of the act ual load

presented by a prod uction tester. System designers will us IBIS or other si m ulation tools to correlate the timi ng refer-

ence load to a syst em environment. Ma nufacturers will correlate to their pr oduction test conditions (generally a coax-

ial t ransmissi on li ne terminat ed at the tester ele ctronics ).

4. AC timing and IDD tests may use a VIL to VIH s wing of up to 1.5V i n the test environment , but input ti m ing is stil l refer-

enced t o VREF (or to t he cros sing poi nt fo r CK, CK), and p arameter spec ificat ions ar e gua ranteed for th e spe cified AC

input levels under normal use cond it ions. The minim um slew ra te for the input signals is 1V/ns in the range between

VIL(AC) and VIH(AC).

5. The AC and DC input level specific ations are as defined in the SSTL_2 Standar d (i .e. the receiver eff ectively

switches as a result of the signal crossing th e AC input l evel, and remains i n that st ate as long as the signal doe s not

ring back above (below) t he DC input LOW (HIGH) level.

6. For DDR SDRAM AC Over shoot / Undershoot Specification see JEDEC ball ot JC-42.3-00-121, jcb-00-083,ltem 193B

For DQ / DM /DQS input slew rate see JEDEC ballot JC-42. 3-00-177, JCB-00-085, Item 1178.0 9

For I/ O Delt a Rise / Fall Derating see JEDEC ballo t JC- 42.3-00-208 , JCB- 00-088, Item 1178.13

For general standard ization of DDR SDRAM lew rat e see JEDEC ballot JC-42. 3-00-117, JCB-00-0 89, Item 1091B

AC Output Load Circuit Diagram / Timing Reference Load

50Ω

Timing Referenc e Po int

Output

(VOUT)

30pF

VTT

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

Page 55 of 72 3/01

AC Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V , See AC Characteri sti cs)

Symbol Parameter/Condition Min Max Unit Notes

VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VREF + 0.31 V 1, 2

VIL(AC) Inp ut Low (Logic 0) Voltage, DQ , D QS, and DM S igna ls VREF − 0.31 V 1, 2

VID(AC) Input Differential Voltage, CK and CK Input s 0.62 VDDQ + 0.6 V 1, 2, 3

VIX(AC) Input Closing Point Voltage, CK and CK Inputs 0.5*VDDQ − 0.2 0.5*VDDQ + 0.2 V 1, 2, 4

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnit ude of the diff erence betwee n the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5 *VDDQ of the transmitt ing device and must trac k va riations in the DC level of th e same.

IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

Characteristics)

Symbol Parameter/Condition DDR266 DDR200 Unit Notes

IDD0

Operating Current: one ba nk ; acti ve / prec ha rg e; tRC = tRC MIN; tCK = tCK MIN; DQ,

DM, and DQS input s changing twice per clock cycle; address and control inputs

changing once per clo c k cycl e 100 90 mA 1, 2

IDD1 O pe rati ng C urr e nt: one bank; active / rea d / prechar ge; Burst = 2; tRC = tRC MIN ;

CL = 2.5; tCK = tCK MIN; IOUT = 0mA ; address and control inputs changing once per

clock cycle 120 100 mA 1, 2

IDD2P Precharge Power-Down St andby Current: all banks idle; power-down mode;

CKE ≤ VIL MAX; tCK = tCK MIN 20 15 mA 1, 2

IDD2N Idle Standby Current: CS ≥ VIH MIN; all banks idle; CKE ≥ VIH MIN;

tCK = tCK MIN; addres s and control inputs changing once pe r clock cycle 40 35 mA 1, 2

IDD3P Active Po wer-Down Sta ndby Current: one bank active; power-down mode;

CKE ≤ VIL MAX; tCK = tCK MIN 20 15 mA 1, 2

IDD3N

Active Standby Current: one bank; active / precharge;CS ≥ VIH MIN;

CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, D M , and D QS inputs changing

twice per clock cycle; address and cont rol inputs changing once per clock cycle 70 60 mA 1, 2

IDD4R

Ope rati ng C urr e nt: one bank; Burst = 2; reads; contin uous burst; address and

control inputs changing once per clock cycle; DQ and DQS outpu ts changing twice

per clock cycle; CL = 2.5; tCK = tCK MIN; IOUT = 0 m A 190 150 mA 1, 2

IDD4W

Ope rati ng C urr e nt: one bank; Burst = 2; writes; continuo us burst; addres s and

control inputs changing once per cl ock cycle; DQ and DQS i nputs changing twice

per clock cycle; CL = 2.5; tCK = tCK MIN 170 130 mA 1, 2

IDD5 Auto-Refresh Current: tRC = tRFC MIN 190 180 mA 1, 2

IDD6 Se lf-Refresh Current: CKE ≤ 0.2V 3 3 mA 1, 2, 3

IDD7

Ope rati ng C urr e nt: fo ur bank; four bank interleaving with B L=4, address and con-

trol inp uts randomly changing; 50% of data changing at every transfer; tRC = t RC

MIN; IOUT = 0mA 325 250 mA 1

1. IDD specifications are tested afte r the device is properly initialized and measured at 100 Mhz

for DDR200 and 133 MHz for DDR266

2. Input slew rate = 1V/ns.

3. Enables on-chip refresh and address counters.

HYB25D256400/800T/AT

256-Mbit Double Data Rate SDRAM

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Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute

Specifications

(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Charac teristics ) (Part 1 of 3)

Symbol Parameter

DDR266A

-7 DDR266B

-7.5 DDR200

-8 Unit Notes

Min Max Min Max Min Max

tAC DQ output access time from CK/CK − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4

tDQSCK DQS output access time from CK/CK − 0.75 + 0.75 − 0. 75 + 0.75 − 0.8 + 0.8 ns 1-4

tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4

tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4

tHP Clock Half Period min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) ns 1-4

tCK Clock cycle time CL = 2.5 7 25 7.5 12 8 12 ns 1-4

tCK CL = 2.0 7.5 12 8 12 10 12 ns 1-4

tDH DQ and DM input hold time 0.5 0.5 0.6 ns 1-4

tDS DQ and DM input setup time 0.5 0.5 0.6 ns 1-4

tIPW Control and Addr. input pulse width (each input) 2 .2 2.2 2.5 ns 1-, 12

tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4,12

tHZ Data-out high-impedence time from

CK/CK − 0.75 + 0. 75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5

tLZ Data-out low -impedence time from

CK/CK − 0.75 + 0. 75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5

tDQSS Write command to 1st DQS latching

transition 0.75 1.25 0.75 1.25 0.75 1.25 tCK 1-4

tDQSQ DQS-DQ skew (for D QS & associated DQ signals) + 0.5 + 0.5 + 0. 6 ns 1-4

tQHS Data hold skew factor + 0.75 + 0.75 + 1.0 ns 1-4

tQH Data Output hold time from DQS tHP-tQHS tHP-tQHS tHP-tQHS ns 1-4

tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 tCK 1-4

1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.

2. T he C K/CK input reference level (for timing r eference to CK/CK) is the point at which CK and CK cross: the input reference level for

signals other than C K/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as me asured at the ti ming reference point indicated i n AC C haracter istics (No te 3) is VTT.

5. tHZ and tLZ transitions occu r in the same access time windows as valid data tran sitions . These parameters are not refe rred to a spe-

cific voltage level, bu t specify when th e device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The de vice operates with a greater value for this parameter, but system

performanc e (bus turna round) degrades accordingly.

7. The specific requirement is that DQS be valid (HIGH, LOW , or some point on a valid transition) on or bef ore this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the b us, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,

LOW, or tra nsitioning from HIGH to LOW at this time, dependin g on tDQSS.

8. A maximum of eight A utoref resh commands can be posted to any gi ven DDR SDRAM device.

9. QFC is enabled as soon as possible aft er the rising CK edge that registers the Write command.

10. QFC is disabled as soon as possible after the last valid DQS edge transitions Low.

11. For ea ch of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual syste m clock cycle tim e.

12. These parameters guarant ee device timing, but they are not necess arily teste d on each device

13. Fast slew r ate >= 1 V/ns , slow slew rate >= 0.5V/ns. For input setup & holdtime derating for slew rates less than 0.5 V/ns see

JEDEC ballot JC-423- 00-210, JCB-00-087, Item 1178.10

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256-Mbit Double Data Rate SDRAM

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tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 tCK 1-4

tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 tCK 1-4

tMRD Mode register set command cycle time 14 15 16 ns 1-4

tWPRES Write p reamble setup ti me 0 0 0 ns 1-4, 7

tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1-4, 6

tWPRE Write preamble 0.25 0.25 0.25 tCK 1-4

tIH Ad dr. an d co ntrol inpu t ho l d tim e ( fa st slew rate) 0.9 0. 9 1.2 ns

1-4,

12,13

tIS Addr. and c ontrol input setup time (fast slew rate) 0.9 0.9 1.2 ns

tIH Ad dr. an d co ntrol inpu t ho l d tim e ( sl ow sl ew r ate ) 1.0 1.0 1. 2 n s

tIS Addr. and c ontrol input setup time (slow slew rate) 1.0 1.0 1.2 ns

tRPRE Rea d pr e am b le 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1-4

tRPST Read post am b le 0 .4 0 0.6 0 0.4 0 0.6 0 0.4 0 0.6 0 tCK 1-4

tRAS Act ive to Prec harge command 45 120,000 45 120,000 50 120,000 ns 1-4

tRC Active to Active/Auto -refresh command period 65 65 70 ns 1-4

tRFC Auto-refresh to Active/Auto-refresh

command perio d 75 75 80 ns 1-4

tRCD Active to Read or Write delay 20 20 20 ns 1-4

tRP Precharge command per iod 20 20 20 ns 1-4

tRRD Active bank A t o Active bank B comma nd 15 15 15 ns 1-4

tWR Write recov ery time 15 15 15 ns 1-4

Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute

Specifications

(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Charac teristics ) (Part 2 of 3)

Symbol Parameter

DDR266A

-7 DDR266B

-7.5 DDR200

-8 Unit Notes

Min Max Min Max Min Max

1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.

2. T he C K/CK input reference level (for timing r eference to CK/CK) is th e point at which CK and CK cr oss: the input refere nce l evel for