P0066-08
VCC1
OUTA
INB
GND1
VCC2
INA
OUTB
GND2
ISO7421
D Package
(Top View)
1
2
3
4
8
7
6
5
Isolation
VCC1
INA
INB
GND1
VCC2
OUTA
OUTB
GND2
ISO7420
D Package
(Top View)
1
2
3
4
8
7
6
5
Isolation
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
Low-Power Dual Digital Isolators
Check for Samples: ISO7420,ISO7420M,ISO7421
1FEATURES APPLICATIONS
2•Highest Signaling Rate: 1 Mbps •Optocoupler Replacement in:
•Low Power Consumption, Typical ICC per –Industrial Fieldbus
Channel (3.3V operation): –Profibus
–ISO7420: 1.1 mA, ISO7421: 1.5 mA –Modbus
•Low Propagation Delay –9 ns Typ. and Low –DeviceNet™Data Buses
Skew –300 ps Typ. –Servo Control Interface
•Wide TARange Specified: –40°C to 125°C–Motor Control
•UL 1577 Approved with 2.5 kVrms Rating –Power Supplies
•4-kVpeak Maximum Isolation, IEC/VDE and –Battery Packs
CSA Approvals, IEC 60950-1, IEC 61010-1 End
Equipment Standards Approvals. All
Approvals Pending.
•50 kV/μs Transient Immunity, Typical
•Over 25-Year Isolation Integrity at Rated
Voltage
•Operates From 3.3V and 5V Supply and Logic
Levels
DESCRIPTION
The ISO7420, ISO7420M and ISO7421 provide galvanic isolation up to 2.5 kVrms for 1 minute per UL. These
digital isolators have two isolated channels. Each isolation channel has a logic input and output buffer separated
by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices
prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or
damaging sensitive circuitry. The suffix M indicates wide temperature range (–40°C to 125°C).
The devices have TTL input thresholds and require two supply voltages, 3.3V or 5V, or any combination. All
inputs are 5-V tolerant when supplied from a 3.3V supply.
Note: The ISO7420 and ISO7421 are specified for signaling rates up to 1 Mbps. Due to their fast response time,
under most cases, these devices will also transmit data with much shorter pulse widths. Designers should add
external filtering to remove spurious signals with input pulse duration <20ns if desired.
SPACER
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DeviceNet is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains Copyright ©2009–2011, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
INA 7 I Input, channel A
INB 3 I Input, channel B
GND1 4 –Ground connection for VCC1
GND2 5 –Ground connection for VCC2
OUTA 2 O Output, channel A
OUTB 6 O Output, channel B
VCC1 1–Power supply, VCC1
VCC2 8–Power supply, VCC2
Table 1. FUNCTION TABLE(1)
INPUT SIDE OUTPUT SIDE INPUT OUTPUT
VCC VCC IN OUT
H H
PU PU L L
Open H(2)
PD PU X H(2)
(1) PU = Powered up (VCC ≥3 V); PD = Powered down (VCC ≤2.4 V);
X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output is at high level for ISO7420, ISO7420M
and ISO7421.
AVAILABLE OPTIONS
RATED INPUT CHANNEL MARKED ORDERING
PRODUCT PACKAGE RATED TA
ISOLATION THRESHOLD DIRECTION AS NUMBER
ISO7420D (rail)
ISO7420 –40°C to 105°C IS7420 ISO7420DR (reel)
Same direction ISO7420MD (rail)
~1.5 V (TTL)
ISO7420M 2.5 kVrms D-8 –40°C to 125°C I7420M ISO7420MDR
(CMOS compatible) (reel)
ISO7421D (rail)
Opposite
ISO7421 –40°C to 105°C IS7421
directions ISO7421DR (reel)
2Copyright ©2009–2011, Texas Instruments Incorporated
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
VCC Supply voltage(2), VCC1, VCC2 –0.5 V to 6 V
VIVoltage at IN, OUT –0.5 V to 6 V
IOOutput current ±15 mA
Human-body model JEDEC Standard 22, Test Method A114-C.01 ±4 kV
Electrostatic Field-induced charged-device
ESD JEDEC Standard 22, Test Method C101 All pins ±1.5 kV
discharge model
Machine model ANSI/ESDS5.2-1996 ±200 V
TJ(Max) Maximum junction temperature 150°C
Tstg Storage temperature -65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
VCC1, VCC2 Supply voltage - 3.3V operation 3.15 3.3 3.45 V
Supply voltage - 5V operation 4.75 5 5.25
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
TJ(1) Junction temperature –40 136 °C
1/tui Signaling rate 0 1 Mbps
tui Input pulse duration 1 us
(1) To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the ICC limits in this data
sheet.
Copyright ©2009–2011, Texas Instruments Incorporated 3
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5V ±5%; TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH =–4 mA; see Figure 1. VCC –0.8 4.6
VOH High-level output voltage V
IOH =–20 μA; see Figure 1. VCC –0.1 5
IOL = 4 mA; see Figure 1. 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 1. 0 0.1
VI(HYS) Input threshold voltage hysteresis 400 mV
IIH High-level input current 10 μA
INx at 0 V or VCC
IIL Low-level input current –10 μA
CMTI Common-mode transient immunity VI= VCC or 0 V; see Figure 3. 25 50 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7420
ICC1 Supply current for VCC1 0.4 1
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 3 6
ISO7421
ICC1 Supply current for VCC1 2 4
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 2 4
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5V ±5%; TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 1. 9 14 ns
PWD(1) Pulse width distortion |tPHL –tPLH| 0.3 3.7 ns
tsk(pp) Part-to-part skew time 4.9 ns
tsk(o) Channel-to-channel output skew time 3.6 ns
trOutput signal rise time See Figure 1. 1 ns
tfOutput signal fall time 1 ns
tfs Fail-safe output delay time from input power loss See Figure 2. 6 μs
(1) Also known as pulse skew.
4Copyright ©2009–2011, Texas Instruments Incorporated
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS
VCC1 at 5V ±5%, VCC2 at 3.3V ±5%; TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH =–4 mA; ISO7421 (5-V side) VCC –0.8 4.6
see Figure 1.ISO7420 / 7421 (3.3-V VCC –0.4 3
VOH High-level output voltage V
side) .
IOH =–20 μA; see Figure 1, VCC –0.1 VCC
IOL = 4 mA; see Figure 1. 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 1. 0 0.1
VI(HYS) Input threshold voltage hysteresis 400 mV
IIH High-level input current 10 μA
INx at 0 V or VCC
IIL Low-level input current –10 μA
CMTI Common-mode transient immunity VI= VCC or 0 V; see Figure 3. 25 40 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7420
ICC1 Supply current for VCC1 0.4 1 mA
DC to 1 Mbps VI= VCC or 0 V, 15 pF load
ICC2 Supply current for VCC2 2 4.5 mA
ISO7421
ICC1 Supply current for VCC1 2 4 mA
DC to 1 Mbps VI= VCC or 0 V, 15 pF load
ICC2 Supply current for VCC2 1.5 3.5 mA
SWITCHING CHARACTERISTICS
VCC1 at 5V ±5%, VCC2 at 3.3V ±5%; TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 1. 10 17 ns
PWD(1) Pulse width distortion |tPHL –tPLH| 0.5 5.6 ns
tsk(pp) Part-to-part skew time 6.3 ns
tsk(o) Channel-to-channel output skew time 4 ns
trOutput signal rise time See Figure 1. 2 ns
tfOutput signal fall time 2 ns
tfs Fail-safe output delay time from input power loss See Figure 2. 6 μs
(1) Also known as pulse skew.
Copyright ©2009–2011, Texas Instruments Incorporated 5
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC1 at 3.3V ±5%, VCC2 at 5V ±5%; TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH =–4 mA; ISO7420 / 7421 (5-V side). VCC –0.8 4.6
see Figure 1.
VOH High-level output voltage V
ISO7421 (3.3-V side) VCC –0.4 3
IOH =–20 μA; see Figure 1 VCC –0.1 VCC
IOL = 4 mA; see Figure 1. 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 1. 0 0.1
VI(HYS) Input threshold voltage hysteresis 400 mV
IIH High-level input current 10 μA
INx at 0 V or VCC
IIL Low-level input current –10 μA
CMTI Common-mode transient immunity VI= VCC or 0 V; see Figure 3. 25 40 kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7420
ICC1 Supply current for VCC1 0.2 0.7
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 3 6
ISO7421
ICC1 Supply current for VCC1 1.5 3.5
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 2 4
SWITCHING CHARACTERISTICS
VCC1 at 3.3V ±5%, VCC2 at 5V ±5%, TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 1. 10 17 ns
PWD(1) Pulse width distortion |tPHL –tPLH| 0.5 4 ns
tsk(pp) Part-to-part skew time 8.5 ns
tsk(o) Channel-to-channel output skew time 4 ns
trOutput signal rise time See Figure 1. 2 ns
tfOutput signal fall time 2 ns
tfs Fail-safe output delay time from input power loss See Figure 2. 6 μs
(1) Also known as pulse skew.
6Copyright ©2009–2011, Texas Instruments Incorporated
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3V ±5%, TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH =–4 mA; see Figure 1. VCC –0.4 3
VOH High-level output voltage V
IOH =–20 μA; see Figure 1. VCC –0.1 3.3
IOL = 4 mA; see Figure 1. 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 1. 0 0.1
VI(HYS) Input threshold voltage hysteresis 400 mV
IIH High-level input current 10 μA
INx at 0 V or VCC
IIL Low-level input current –10 μA
Common-mode transient
CMTI VI= VCC or 0 V; see Figure 3. 25 40 kV/μs
immunity
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7420
ICC1 Supply current for VCC1 0.2 0.7
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 2 4.5
ISO7421
ICC1 Supply current for VCC1 1.5 3.5
DC to 1 Mbps VI= VCC or 0 V, 15 pF load mA
ICC2 Supply current for VCC2 1.5 3.5
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3V ±5%, TA=–40°C to 125°C for ISO7420M, TA=–40°C to 105°C for ISO742x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 12 20 ns
PWD(1) Pulse width distortion |tPHL –tPLH| See Figure 1. 1 5 ns
tsk(pp) Part-to-part skew time 6.8 ns
tsk(o) Channel-to-channel output skew time 5.5 ns
trOutput signal rise time 2 ns
See Figure 1.
tfOutput signal fall time 2 ns
tfs Fail-safe output delay time from input power loss See Figure 2. 6 μs
(1) Also known as pulse skew.
Copyright ©2009–2011, Texas Instruments Incorporated 7
S0412-01
IsolationBarrier
VI50 W
IN
VO
Input
Generator(1) CL
(2)
OUT 1.4V
10%
90%
VI
VO
tPLH tPHL
1.4V
VCC1
0V
V /2
CC
trtf
VOH
V /2
CC
VOL
Isolation Barrier
VI
IN VO
0 V
or
VCC1
CL
(1)
OUT
VCC1
tfs
2.7 V
VCC1
0 V
VI
VOL
VOH
50%
VO
S0414-01
IsolationBarrier
C=0.1 F±1%m
IN
VOH orVOL
(1)
OUT
VCC1
+–
VCM
VCC2 C=0.1 F±1%m
GND2GND1
S1
+
–
Pass-failcriteria –
outputmustremain
stable.
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle,
tr≤3 ns, tf≤3 ns, ZO= 50 Ω. At the input, a 50-Ωresistor is required to terminate the Input Generator signal. It is not
needed in an actual application.
(2) CL= 15 pF ±20% includes instrumentation and fixture capacitance.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
(1) CL= 15 pF ±20% includes instrumentation and fixture capacitance.
Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
(1) CL= 15 pF ±20% includes instrumentation and fixture capacitance.
Figure 3. Common-Mode Transient Immunity Test Circuit
8Copyright ©2009–2011, Texas Instruments Incorporated
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm
Minimum external tracking Shortest terminal-to-terminal distance across the
L(I02) 4.3 mm
(creepage) package surface
Tracking resistance (comparative
CTI DIN IEC 60112 / VDE 0303 Part 1 >175 V
tracking index)
Minimum internal gap (internal Distance through the insulation 0.014 mm
clearance) VIO = 500 V, TA<100°C>1012 Ω
Isolation resistance, input to
RIO output(1) VIO = 500 V, 100°C≤TA≤max >1011 Ω
Barrier capacitance, input to
CIO VIO = 0.4 sin (2πft), f = 1 MHz 1 pF
output(1)
CIInput capacitance(2) VI= VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal according to the
measurement techniques shown in the Isolation Glossary. Techniques such as inserting
grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
INSULATION CHARACTERISTICS(3)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum working insulation voltage 560 Vpeak
VPR Input-to-output test voltage t = 1 s (100% production), partial discharge 5 pC 1050 Vpeak
t = 60 s (qualification)
VIOTM Transient overvoltage 4000 Vpeak
t = 1 s (100% production)
t = 60 s (qualification) 2500
VISO Isolation voltage per UL Vrms
t = 1 s (100% production) 3000
RSInsulation resistance VIO = 500 V at TS>109Ω
Pollution degree 2
(3) Climatic Classification 40/125/21
Table 2. IEC 60664-1 RATINGS TABLE
PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group III-a
Rated mains voltage ≤150 Vrms I–IV
Installation classification Rated mains voltage ≤300 Vrms I–III
Rated mains voltage ≤400 Vrms I–II
Copyright ©2009–2011, Texas Instruments Incorporated 9
10
100
0 250 500 750 1000
V – WorkingVoltage – V
IORM
LifeExpectancy – Years
880120
V at560V
IORM
28 Years
G001
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
REGULATORY INFORMATION
VDE CSA UL
Certified according to IEC Approved under CSA Component Recognized under 1577 Component Recognition
60747-5-2 Acceptance Notice Program(1)
File number: pending (40016131) File number: pending (1698195) File number: E181974
(1) Production tested ≥3000 Vrms for 1 second in accordance with UL 1577.
LIFE EXPECTANCY vs WORKING VOLTAGE
Figure 4. Life Expectancy vs Working Voltage
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θJA = 212°C/W, VI= 5.25 V, TJ= 150°C, TA= 25°C 112
Safety input, output, or supply
ISmA
current θJA = 212°C/W, VI= 3.45 V, TJ= 150°C, TA= 25°C 171
TSMaximum case temperature 150 °C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity
Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
10 Copyright ©2009–2011, Texas Instruments Incorporated
Case Temperature − C°
0
20
40
60
80
100
120
140
160
180
0 50 100 150 200
Safety Limiting Current − mA
G002
VCC1, V
CC2 at 3.45 V
VCC1, VCC2 at 5.25 V
S0417-01
1
2
3
4
8
7
6
5
VCC1
0.1 Fm
2 mm
max.
from
VCC1
OUTA
INB
OUTPUT
INPUT
GND1
ISO7421
VCC2
0.1 Fm
2 mm
max.
from
VCC2
INA
OUTB OUTPUT
INPUT
GND2
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
PACKAGE THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K thermal resistance(1) 212
θJA Junction-to-air thermal resistance °C/W
High-K thermal resistance(1) 122
θJB Junction-to-board thermal resistance 37 °C/W
θJC Junction-to-case thermal resistance 69.1 °C/W
VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF,
PDDevice power dissipation 390 mW
Input a 150-Mbps 50% duty-cycle square wave
(1) Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages
Figure 5. θJC Thermal Derating Curve per IEC 60747-5-2
Figure 6. Typical ISO7421 Application Circuit
Copyright ©2009–2011, Texas Instruments Incorporated 11
TA − Free-Air Temperature − °C
0
2
4
6
8
10
12
14
−55 −35 −15 5 25 45 65 85 105 125
tpd − Propagation Delay Time − ns
VCC1, VCC2 at 3.3 V
G004
VCC1, V CC2 at 5 V
TA − Free-Air Temperature − °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
−55 −35 −15 5 25 45 65 85 105 125
Input Voltage Switching Threshold − V
VIT−, 3.3 V
G005
VIT+, 5 V
VIT+, 3.3 V
VIT−, 5 V
TA − Free-Air Temperature − °C
2.52
2.53
2.54
2.55
2.56
2.57
2.58
2.59
2.60
2.61
2.62
−55 −35 −15 5 25 45 65 85 105 125
Fail-Safe Voltage Threshold − V
G006
FS+
FS−
VOH − High-Level Output Voltage − V
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 1 2 3 4 5 6
IOH − High-Level Output Current − mA
VCC1, V CC2 at 3.3 V
G007
VCC1, VCC2 at 5 V
TA = 25°C
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
60
70
80
0 1 2 3 4 5 6
IOL − Low-Level Output Current − mA
VCC1, V CC2 at 3.3 V
G008
VCC1, VCC2 at 5 V
TA = 25°C
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME INPUT VOLTAGE SWITCHING THRESHOLD
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 8. Figure 9.
FAIL-SAFE VOLTAGE THRESHOLD HIGH-LEVEL OUTPUT CURRENT
vs vs
FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE
Figure 10. Figure 11.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
Figure 12.
Copyright ©2009–2011, Texas Instruments Incorporated 13
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
REVISION HISTORY
Changes from Original (June 2009) to Revision A Page
•Added devices ISO7420 and ISO7420M to the data sheet .................................................................................................. 1
•Added the ICC EQUATIONS section ................................................................................................................................... 11
Changes from Revision A (December 2009) to Revision B Page
•Switching Characteristics Table, Added Note (2) - Typical specifications are measured at ideal conditions of 25°C.
Max or Min specifications are measured at worst case conditions for VCC and temperature. .............................................. 4
Changes from Revision B (February 2010) to Revision C Page
•Added devices ISO7420F and ISO7420FM to the data sheet ............................................................................................. 1
•Added The suffix M indicates wide temperature range (–55°C to 125°C) and the suffix F indicates output-low option
in fail-safe condition. All other devices without the F suffix default to output-high in fail-safe state. .................................... 1
•Changed the Function Table Output values for PU (Open) From: H To: H/L ...................................................................... 2
•Changed the Function Table Output values for PU (X) From: H To: H/L ............................................................................. 2
•Changed the Function Table Output values for PU (X) From: H/L To: H ............................................................................. 2
•Added Note (2) in the Function Table ................................................................................................................................... 2
•Added ISO7420F and ISO7420FM tothe Available Options Table ...................................................................................... 2
•Changed value from a max of 4 mA to a min of -4 mA ........................................................................................................ 3
•Changed value from a min of -4 mA to a max of 4 mA ........................................................................................................ 3
•Changed Electrical Characteristics Conditions ..................................................................................................................... 4
•Deleted Cifrom the ELECTRICAL CHARACTERISTICS ..................................................................................................... 4
•Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 4
•Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 4
•Changed PWD parameter from duration to width ................................................................................................................. 4
•Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 5
•Added High-level output voltage ISO7420 / 7421 (3.3-V side) test condition ...................................................................... 5
•Changed High-level output voltage min value ...................................................................................................................... 5
•Deleted CIspecification ........................................................................................................................................................ 5
•Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 5
•Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 5
•Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 5
•Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 6
•Added High-level output voltage ISO7420 / 7421 (5-V side) test condition ......................................................................... 6
•Changed High-level output voltage min value ...................................................................................................................... 6
•Deleted CIspecification ........................................................................................................................................................ 6
•Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 6
•Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 6
•Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 6
•Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 7
•Deleted CIspecification ........................................................................................................................................................ 7
•Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 7
•Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 7
•Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 7
•Changed Note 1 Figure 1 ..................................................................................................................................................... 8
14 Copyright ©2009–2011, Texas Instruments Incorporated
ISO7420
ISO7420M
ISO7421
www.ti.com
SLLS984E –JUNE 2009–REVISED JUNE 2011
•Changed Figure 2 ................................................................................................................................................................. 8
•Added input to output and note 1 to Isolation resistance, input to output ............................................................................ 9
•Changed the Isolation resistance test conditions ................................................................................................................. 9
•Changed the Isolation resistance test conditions ................................................................................................................. 9
•Added note 1 to Barrier capacitance, input to output ........................................................................................................... 9
•Added Input capacitance ...................................................................................................................................................... 9
•Changed TJ= 170°C to TJ= 150°C .................................................................................................................................... 10
•Changed From: 124mA To: 107mA .................................................................................................................................... 10
•Changed TJ= 170°C to TJ= 150°C .................................................................................................................................... 10
•Changed From: 190mA To: 164mA .................................................................................................................................... 10
•Changed Figure 5 ............................................................................................................................................................... 11
•Changed Figure 7 ............................................................................................................................................................... 12
Changes from Revision C (March 2010) to Revision D Page
•Deleted devices ISO7420F and ISO7420FM from the data sheet ....................................................................................... 1
•Updated the Features List .................................................................................................................................................... 1
•Updated the device Description. Add paragraph - Note: The ISO7420 and ISO7421 ......................................................... 1
•Changed the Function Table Output values for PU (Open) From: H/L To: H ...................................................................... 2
•Changed ISO7420M TAtemp From: -55 to 125 To: 40 to 125 in the Available Options Table ............................................ 2
•Added Tstg to the Absolute Maximum Ratings Table .......................................................................................................... 3
•Updated the Recommended Operating Conditions Table .................................................................................................... 3
•Updates throughout the Electrical Characteristics and Switching Characteristics tables ..................................................... 4
•Updated the Supply Current test conditions ......................................................................................................................... 4
•Changed Figure 2 ................................................................................................................................................................. 8
•Changed Note 1 in Figure 3 ................................................................................................................................................. 8
•Changed Minimum internal gap MIN value From: 0.008 To: 0.014mm ................................................................................ 9
•Changed the Barrier capacitance, input to output test conditions ........................................................................................ 9
•Changed the Input capacitance test conditions .................................................................................................................... 9
•Changed the VIORM, VPR, and VIOTM unit values From: V To: Vpeak .................................................................................... 9
•Changed VIFrom: 5.5V To: 5.25V ...................................................................................................................................... 10
•Changed From: 107mA To: 112mA .................................................................................................................................... 10
•Changed VIFrom: 3.6V To: 3.45V ...................................................................................................................................... 10
•Changed From: 164mA To: 171mA .................................................................................................................................... 10
•Changed Figure 5 ............................................................................................................................................................... 11
•Deleted the ICC EQUATIONS section ................................................................................................................................. 11
•Changed Figure 7 ............................................................................................................................................................... 12
•Deleted the SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) graphs and the EYE DIAGRAM plots ............... 13
Copyright ©2009–2011, Texas Instruments Incorporated 15
ISO7420
ISO7420M
ISO7421
SLLS984E –JUNE 2009–REVISED JUNE 2011
www.ti.com
Changes from Revision D (July 2010) to Revision E Page
•Added new fifth bullet to Features and deleted text from 4-kVpeak bullet item ................................................................... 1
•Changed first paragraph in Description from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421 ............ 1
•Changed Note 2 in Function Table from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421 ................... 2
•Deleted the last row in the Available Options table .............................................................................................................. 2
•Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 4
•Changed the MAX value in the SWITCHING CHAR table 2nd row from 3.5 to 3.7 and 3rd row from 4 to 4.9 ................... 4
•Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 5
•Changed the MAX value in the 2nd SWITCHING CHAR table 2nd row from 4 to 5.6 and 3rd row from 5 to 6.3 ............... 5
•Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 6
•Changed the MAX value in the 3rd SWITCHING CHAR table 3rd row from 5 to 8.5 .......................................................... 6
•Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 7
•Changed the MAX value in the 4rd SWITCHING CHAR table 3rd row from 6 to 6.8 .......................................................... 7
•Changed Regulatory Information table last row, last column from: pending (E181974) to: E181974 ................................ 10
16 Copyright ©2009–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 9-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO7420D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7420DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7420MD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7420MDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7421D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7421DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Jul-2012
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7420DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7420MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7421DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7420DR SOIC D 8 2500 367.0 367.0 35.0
ISO7420MDR SOIC D 8 2500 367.0 367.0 35.0
ISO7421DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Aug-2012
Pack Materials-Page 2
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