ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com Low-Power Dual Digital Isolators Check for Samples: ISO7420, ISO7420M, ISO7421 FEATURES APPLICATIONS * * * 1 2 * * * * * * * Highest Signaling Rate: 1 Mbps Low Power Consumption, Typical ICC per Channel (3.3V operation): - ISO7420: 1.1 mA, ISO7421: 1.5 mA Low Propagation Delay - 9 ns Typ. and Low Skew - 300 ps Typ. Wide TA Range Specified: -40C to 125C UL 1577 Approved with 2.5 kVrms Rating 4-kVpeak Maximum Isolation, IEC/VDE and CSA Approvals, IEC 60950-1, IEC 61010-1 End Equipment Standards Approvals. All Approvals Pending. 50 kV/s Transient Immunity, Typical Over 25-Year Isolation Integrity at Rated Voltage Operates From 3.3V and 5V Supply and Logic Levels Optocoupler Replacement in: - Industrial Fieldbus - Profibus - Modbus - DeviceNetTM Data Buses - Servo Control Interface - Motor Control - Power Supplies - Battery Packs DESCRIPTION The ISO7420, ISO7420M and ISO7421 provide galvanic isolation up to 2.5 kVrms for 1 minute per UL. These digital isolators have two isolated channels. Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The suffix M indicates wide temperature range (-40C to 125C). The devices have TTL input thresholds and require two supply voltages, 3.3V or 5V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3V supply. Note: The ISO7420 and ISO7421 are specified for signaling rates up to 1 Mbps. Due to their fast response time, under most cases, these devices will also transmit data with much shorter pulse widths. Designers should add external filtering to remove spurious signals with input pulse duration < 20ns if desired. SPACER 1 INA 2 INB 3 GND1 4 ISO7421 D Package (Top View) 8 VCC2 VCC1 1 7 OUTA OUTA 2 6 OUTB INB 3 5 GND2 GND1 4 Isolation VCC1 Isolation ISO7420 D Package (Top View) 8 VCC2 7 INA 6 OUTB 5 GND2 P0066-08 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS PIN NAME I/O NO. DESCRIPTION INA 7 I Input, channel A INB 3 I Input, channel B GND1 4 - Ground connection for VCC1 GND2 5 - Ground connection for VCC2 OUTA 2 O Output, channel A OUTB 6 O Output, channel B VCC1 1 - Power supply, VCC1 VCC2 8 - Power supply, VCC2 Table 1. FUNCTION TABLE (1) INPUT SIDE VCC PU PD (1) (2) OUTPUT SIDE VCC PU PU INPUT IN OUTPUT OUT H H L L Open H (2) X H (2) PU = Powered up (VCC 3 V); PD = Powered down (VCC 2.4 V); X = Irrelevant; H = High level; L = Low level In fail-safe condition, output is at high level for ISO7420, ISO7420M and ISO7421. AVAILABLE OPTIONS PRODUCT RATED ISOLATION PACKAGE INPUT THRESHOLD RATED TA CHANNEL DIRECTION -40C to 105C ISO7420 MARKED AS IS7420 Same direction ISO7420M ISO7421 2 2.5 kVrms D-8 ~1.5 V (TTL) (CMOS compatible) -40C to 125C -40C to 105C ISO7420D (rail) ISO7420DR (reel) ISO7420MD (rail) I7420M Opposite directions ORDERING NUMBER IS7421 ISO7420MDR (reel) ISO7421D (rail) ISO7421DR (reel) Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE VCC Supply voltage (2), VCC1, VCC2 -0.5 V to 6 V VI Voltage at IN, OUT -0.5 V to 6 V IO Output current ESD Electrostatic discharge 15 mA Human-body model JEDEC Standard 22, Test Method A114-C.01 Field-induced charged-device model JEDEC Standard 22, Test Method C101 Machine model ANSI/ESDS5.2-1996 4 kV 1.5 kV All pins 200 V TJ(Max) Maximum junction temperature Tstg (1) (2) 150C Storage temperature -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC1, VCC2 TYP MAX Supply voltage - 3.3V operation 3.15 3.3 3.45 Supply voltage - 5V operation 4.75 5 5.25 -4 UNIT V IOH High-level output current IOL Low-level output current VIH High-level input voltage 2 VCC VIL Low-level input voltage 0 0.8 V TJ (1) Junction temperature -40 136 C 1/tui Signaling rate 0 1 tui Input pulse duration 1 (1) mA 4 mA V Mbps us To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the ICC limits in this data sheet. Copyright (c) 2009-2011, Texas Instruments Incorporated 3 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5V 5%; TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN TYP IOH = -4 mA; see Figure 1. VCC - 0.8 4.6 IOH = -20 A; see Figure 1. VCC - 0.1 5 High-level input current IIL Low-level input current 0.2 0.4 IOL = 20 A; see Figure 1. 0 0.1 CMTI Common-mode transient immunity 400 -10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT V IOL = 4 mA; see Figure 1. VI(HYS) Input threshold voltage hysteresis IIH MAX A A 50 kV/s SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.4 1 3 6 2 4 2 4 mA ISO7421 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load mA SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5V 5%; TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 4 TEST CONDITIONS See Figure 1. See Figure 1. See Figure 2. MIN TYP MAX UNIT 9 14 ns 0.3 3.7 ns 4.9 ns 3.6 ns 1 ns 1 ns 6 s Also known as pulse skew. Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 5V 5%, VCC2 at 3.3V 5%; TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER TEST CONDITIONS IOH = -4 mA; see Figure 1. VOH High-level output voltage MIN TYP ISO7421 (5-V side) VCC - 0.8 4.6 ISO7420 / 7421 (3.3-V side) . VCC - 0.4 3 VCC - 0.1 VCC IOH = -20 A; see Figure 1, VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX V IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 A; see Figure 1. 0 0.1 400 -10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT A A 40 kV/s SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.4 1 mA 2 4.5 mA 2 4 mA 1.5 3.5 mA ISO7421 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load SWITCHING CHARACTERISTICS VCC1 at 5V 5%, VCC2 at 3.3V 5%; TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) TEST CONDITIONS See Figure 1. See Figure 1. See Figure 2. MIN TYP MAX 10 17 ns 0.5 5.6 ns 6.3 ns 4 ns 2 UNIT ns 2 ns 6 s Also known as pulse skew. Copyright (c) 2009-2011, Texas Instruments Incorporated 5 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 3.3V 5%, VCC2 at 5V 5%; TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER TEST CONDITIONS IOH = -4 mA; see Figure 1. VOH High-level output voltage MIN TYP ISO7420 / 7421 (5-V side). VCC - 0.8 4.6 ISO7421 (3.3-V side) VCC - 0.4 3 VCC - 0.1 VCC IOH = -20 A; see Figure 1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX V IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 A; see Figure 1. 0 0.1 400 -10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT A A 40 kV/s SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.2 0.7 3 6 1.5 3.5 2 4 mA ISO7421 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 mA SWITCHING CHARACTERISTICS VCC1 at 3.3V 5%, VCC2 at 5V 5%, TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 6 TEST CONDITIONS See Figure 1. See Figure 1. See Figure 2. MIN TYP MAX 10 17 ns 0.5 4 ns 8.5 ns 4 ns 2 UNIT ns 2 ns 6 s Also known as pulse skew. Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3V 5%, TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER TEST CONDITIONS VOH High-level output voltage VOL Low-level output voltage MIN IOH = -4 mA; see Figure 1. VCC - 0.4 3 IOH = -20 A; see Figure 1. VCC - 0.1 3.3 High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX 0.2 0.4 IOL = 20 A; see Figure 1. 0 0.1 400 -10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT V IOL = 4 mA; see Figure 1. VI(HYS) Input threshold voltage hysteresis IIH TYP A A 40 kV/s SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.2 0.7 2 4.5 1.5 3.5 1.5 3.5 mA ISO7421 ICC1 Supply current for VCC1 ICC2 Supply current for VCC2 mA SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3V 5%, TA = -40C to 125C for ISO7420M, TA = -40C to 105C for ISO742x PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) TEST CONDITIONS See Figure 1. See Figure 1. See Figure 2. MIN TYP MAX 12 20 UNIT ns 1 5 ns 6.8 ns 5.5 ns 2 ns 2 ns 6 s Also known as pulse skew. Copyright (c) 2009-2011, Texas Instruments Incorporated 7 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com Isolation Barrier PARAMETER MEASUREMENT INFORMATION IN Input Generator (1) 50 W VI VCC1 VI OUT 1.4 V 1.4 V 0V VO CL tPLH (2) tPHL 90% 10% VCC/2 VO VCC/2 VOH VOL tr tf S0412-01 (1) The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr 3 ns, tf 3 ns, ZO = 50 . At the input, a 50- resistor is required to terminate the Input Generator signal. It is not needed in an actual application. (2) CL = 15 pF 20% includes instrumentation and fixture capacitance. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VCC1 0 V IN or VCC1 Isolation Barrier VI VCC1 VI OUT 2.7 V 0V VO tfs VOH (1) CL 50% VO VOL (1) CL = 15 pF 20% includes instrumentation and fixture capacitance. Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 mF 1% VCC2 GND1 C = 0.1 mF 1% Pass-fail criteria - output must remain stable. Isolation Barrier VCC1 OUT + VOH or VOL GND2 (1) - + VCM - S0414-01 (1) CL = 15 pF 20% includes instrumentation and fixture capacitance. Figure 3. Common-Mode Transient Immunity Test Circuit 8 Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4.3 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >175 V Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) CI Input capacitance (2) (1) (2) >1012 11 VIO = 0.4 sin (2ft), f = 1 MHz 1 pF VI = VCC/2 + 0.4 sin (2ft), f = 1 MHz, VCC = 5 V 1 pF VIO = 500 V, TA < 100C VIO = 500 V, 100C TA max >10 All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. INSULATION CHARACTERISTICS (3) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIORM Maximum working insulation voltage VPR Input-to-output test voltage VIOTM Transient overvoltage VISO Isolation voltage per UL RS Insulation resistance t = 1 s (100% production), partial discharge 5 pC t = 60 s (qualification) t = 1 s (100% production) UNIT 560 Vpeak 1050 Vpeak 4000 Vpeak t = 60 s (qualification) 2500 t = 1 s (100% production) 3000 VIO = 500 V at TS >109 Pollution degree (3) SPECIFICATION Vrms 2 Climatic Classification 40/125/21 Table 2. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group III-a Rated mains voltage 150 Vrms I-IV Rated mains voltage 300 Vrms I-III Rated mains voltage 400 Vrms I-II Copyright (c) 2009-2011, Texas Instruments Incorporated 9 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File number: pending (40016131) File number: pending (1698195) File number: E181974 (1) Production tested 3000 Vrms for 1 second in accordance with UL 1577. LIFE EXPECTANCY vs WORKING VOLTAGE Life Expectancy - Years 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 VIORM - Working Voltage - V G001 Figure 4. Life Expectancy vs Working Voltage IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current TS Maximum case temperature TEST CONDITIONS MIN TYP MAX JA = 212C/W, VI = 5.25 V, TJ = 150C, TA = 25C 112 JA = 212C/W, VI = 3.45 V, TJ = 150C, TA = 25C 171 150 UNIT mA C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 10 Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com PACKAGE THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS Junction-to-air thermal resistance JB Junction-to-board thermal resistance JC Junction-to-case thermal resistance PD (1) 212 122 VCC1 = VCC2 = 5.5 V, TJ = 150C, CL = 15 pF, Input a 150-Mbps 50% duty-cycle square wave Device power dissipation TYP High-K thermal resistance (1) Low-K thermal resistance JA MIN (1) MAX UNIT C/W 37 C/W 69.1 C/W 390 mW Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages Safety Limiting Current - mA 180 VCC1, VCC2 at 3.45 V 160 140 120 100 VCC1, VCC2 at 5.25 V 80 60 40 20 0 0 50 100 150 200 Case Temperature - C G002 Figure 5. JC Thermal Derating Curve per IEC 60747-5-2 VCC1 0.1mF OUTPUT INPUT GND1 VCC2 2 mm 2 mm max. max. ISO7421 from from VCC1 VCC2 8 1 OUTA INA 7 2 INB OUTB 6 3 5 4 0.1mF INPUT OUTPUT GND2 S0417-01 Figure 6. Typical ISO7421 Application Circuit Copyright (c) 2009-2011, Texas Instruments Incorporated 11 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com ISO742x and ISO7420M Input VCC1 VCC1 VCC1 Output VCC2 1 MW 8W 500 W IN OUT 13 W Figure 7. Device I/O Schematics 12 Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE INPUT VOLTAGE SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE 1.6 12 Input Voltage Switching Threshold - V tpd - Propagation Delay Time - ns 14 VCC1, VCC2 at 3.3 V 10 8 VCC1, VCC2 at 5 V 6 4 2 0 -55 -35 -15 5 25 45 65 85 105 TA - Free-Air Temperature - C 1.4 1.2 1.1 VIT-, 5 V 1.0 VIT-, 3.3 V 0.9 0.8 -55 125 -35 -15 5 25 45 65 85 105 TA - Free-Air Temperature - C G004 125 G005 Figure 8. Figure 9. FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 IOH - High-Level Output Current - mA Fail-Safe Voltage Threshold - V VIT+, 3.3 V 1.3 2.62 2.61 FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS- 2.54 2.53 2.52 -55 VIT+, 5 V 1.5 TA = 25C -10 -20 -30 -40 VCC1, VCC2 at 3.3 V -50 -60 -70 VCC1, VCC2 at 5 V -80 -90 -35 -15 5 25 45 65 85 105 TA - Free-Air Temperature - C 125 0 1 2 3 4 VOH - High-Level Output Voltage - V G006 Figure 10. 5 6 G007 Figure 11. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE IOL - Low-Level Output Current - mA 80 TA = 25C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 VOL - Low-Level Output Voltage - V 5 6 G008 Figure 12. Copyright (c) 2009-2011, Texas Instruments Incorporated 13 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 www.ti.com REVISION HISTORY Changes from Original (June 2009) to Revision A Page * Added devices ISO7420 and ISO7420M to the data sheet .................................................................................................. 1 * Added the ICC EQUATIONS section ................................................................................................................................... 11 Changes from Revision A (December 2009) to Revision B * Page Switching Characteristics Table, Added Note (2) - Typical specifications are measured at ideal conditions of 25C. Max or Min specifications are measured at worst case conditions for VCC and temperature. .............................................. 4 Changes from Revision B (February 2010) to Revision C Page * Added devices ISO7420F and ISO7420FM to the data sheet ............................................................................................. 1 * Added The suffix M indicates wide temperature range (-55C to 125C) and the suffix F indicates output-low option in fail-safe condition. All other devices without the F suffix default to output-high in fail-safe state. .................................... 1 * Changed the Function Table Output values for PU (Open) From: H To: H/L ...................................................................... 2 * Changed the Function Table Output values for PU (X) From: H To: H/L ............................................................................. 2 * Changed the Function Table Output values for PU (X) From: H/L To: H ............................................................................. 2 * Added Note (2) in the Function Table ................................................................................................................................... 2 * Added ISO7420F and ISO7420FM tothe Available Options Table ...................................................................................... 2 * Changed value from a max of 4 mA to a min of -4 mA ........................................................................................................ 3 * Changed value from a min of -4 mA to a max of 4 mA ........................................................................................................ 3 * Changed Electrical Characteristics Conditions ..................................................................................................................... 4 * Deleted Ci from the ELECTRICAL CHARACTERISTICS ..................................................................................................... 4 * Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 4 * Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 4 * Changed PWD parameter from duration to width ................................................................................................................. 4 * Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 5 * Added High-level output voltage ISO7420 / 7421 (3.3-V side) test condition ...................................................................... 5 * Changed High-level output voltage min value ...................................................................................................................... 5 * Deleted CI specification ........................................................................................................................................................ 5 * Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 5 * Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 5 * Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 5 * Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 6 * Added High-level output voltage ISO7420 / 7421 (5-V side) test condition ......................................................................... 6 * Changed High-level output voltage min value ...................................................................................................................... 6 * Deleted CI specification ........................................................................................................................................................ 6 * Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 6 * Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 6 * Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 6 * Changed ELECTRICAL CHARACTERISTICS conditions .................................................................................................... 7 * Deleted CI specification ........................................................................................................................................................ 7 * Added (All inputs switching with square wave clock signal for dynamic ICC measurement) ............................................... 7 * Changed SWITCHING CHARACTERISTICS conditions ..................................................................................................... 7 * Changed Pulse duration distortion to Pulse width distortion ................................................................................................ 7 * Changed Note 1 Figure 1 ..................................................................................................................................................... 8 14 Copyright (c) 2009-2011, Texas Instruments Incorporated ISO7420 ISO7420M ISO7421 www.ti.com SLLS984E - JUNE 2009 - REVISED JUNE 2011 * Changed Figure 2 ................................................................................................................................................................. 8 * Added input to output and note 1 to Isolation resistance, input to output ............................................................................ 9 * Changed the Isolation resistance test conditions ................................................................................................................. 9 * Changed the Isolation resistance test conditions ................................................................................................................. 9 * Added note 1 to Barrier capacitance, input to output ........................................................................................................... 9 * Added Input capacitance ...................................................................................................................................................... 9 * Changed TJ = 170C to TJ = 150C .................................................................................................................................... 10 * Changed From: 124mA To: 107mA .................................................................................................................................... 10 * Changed TJ = 170C to TJ = 150C .................................................................................................................................... 10 * Changed From: 190mA To: 164mA .................................................................................................................................... 10 * Changed Figure 5 ............................................................................................................................................................... 11 * Changed Figure 7 ............................................................................................................................................................... 12 Changes from Revision C (March 2010) to Revision D Page * Deleted devices ISO7420F and ISO7420FM from the data sheet ....................................................................................... 1 * Updated the Features List .................................................................................................................................................... 1 * Updated the device Description. Add paragraph - Note: The ISO7420 and ISO7421 ......................................................... 1 * Changed the Function Table Output values for PU (Open) From: H/L To: H ...................................................................... 2 * Changed ISO7420M TA temp From: -55 to 125 To: 40 to 125 in the Available Options Table ............................................ 2 * Added Tstg to the Absolute Maximum Ratings Table .......................................................................................................... 3 * Updated the Recommended Operating Conditions Table .................................................................................................... 3 * Updates throughout the Electrical Characteristics and Switching Characteristics tables ..................................................... 4 * Updated the Supply Current test conditions ......................................................................................................................... 4 * Changed Figure 2 ................................................................................................................................................................. 8 * Changed Note 1 in Figure 3 ................................................................................................................................................. 8 * Changed Minimum internal gap MIN value From: 0.008 To: 0.014mm ................................................................................ 9 * Changed the Barrier capacitance, input to output test conditions ........................................................................................ 9 * Changed the Input capacitance test conditions .................................................................................................................... 9 * Changed the VIORM, VPR, and VIOTM unit values From: V To: Vpeak .................................................................................... 9 * Changed VI From: 5.5V To: 5.25V ...................................................................................................................................... 10 * Changed From: 107mA To: 112mA .................................................................................................................................... 10 * Changed VI From: 3.6V To: 3.45V ...................................................................................................................................... 10 * Changed From: 164mA To: 171mA .................................................................................................................................... 10 * Changed Figure 5 ............................................................................................................................................................... 11 * Deleted the ICC EQUATIONS section ................................................................................................................................. 11 * Changed Figure 7 ............................................................................................................................................................... 12 * Deleted the SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) graphs and the EYE DIAGRAM plots ............... 13 Copyright (c) 2009-2011, Texas Instruments Incorporated 15 ISO7420 ISO7420M ISO7421 SLLS984E - JUNE 2009 - REVISED JUNE 2011 Changes from Revision D (July 2010) to Revision E www.ti.com Page * Added new fifth bullet to Features and deleted text from 4-kVpeak bullet item ................................................................... 1 * Changed first paragraph in Description from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421 ............ 1 * Changed Note 2 in Function Table from: ISO7420M, ISO7421, and ISO7421M to: ISO7420M and ISO7421 ................... 2 * Deleted the last row in the Available Options table .............................................................................................................. 2 * Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 4 * Changed the MAX value in the SWITCHING CHAR table 2nd row from 3.5 to 3.7 and 3rd row from 4 to 4.9 ................... 4 * Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 5 * Changed the MAX value in the 2nd SWITCHING CHAR table 2nd row from 4 to 5.6 and 3rd row from 5 to 6.3 ............... 5 * Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 6 * Changed the MAX value in the 3rd SWITCHING CHAR table 3rd row from 5 to 8.5 .......................................................... 6 * Changed ISO742xM in the ELEC CHAR and SWITCHING CHAR table to ISO7420M ...................................................... 7 * Changed the MAX value in the 4rd SWITCHING CHAR table 3rd row from 6 to 6.8 .......................................................... 7 * Changed Regulatory Information table last row, last column from: pending (E181974) to: E181974 ................................ 10 16 Copyright (c) 2009-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 9-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ISO7420D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7420DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7420MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7420MDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7421D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7421DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Jul-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7420DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7420MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7421DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7420DR SOIC D 8 2500 367.0 367.0 35.0 ISO7420MDR SOIC D 8 2500 367.0 367.0 35.0 ISO7421DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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