July 2015
©2013 Fairchild Semiconductor Corporation
FDMS86101DC Rev. 1.7 www.fairchildsemi.com
1
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
FDMS86101DC
N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
100 V, 60 A, 7.5 mΩ
Features
Shielded Gate MOSFET Technology
Dual CoolTM Top Side Cooling PQFN package
Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 14.5 A
Max rDS(on) = 12 mΩ at VGS = 6 V, ID = 11.5 A
High performance technology for extremely low rDS(on)
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. Advancements in both
silicon and Dual CoolTM package technologies have been
combined to offer the lowest rDS(on) while maintaining excellent
switching performance by extremely low Junction-to-Ambient
thermal resistance.
Applications
Primary DC-DC MOSFET
Secondary Synchronous Rectifier
Load Switch
Bottom
Top
D
D
D
D
S
S
S
G
Pin 1
S
GSS
D
DDD
Dual CoolTM 56
S
Pin 1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 100 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C 60 A -Continuous TA = 25 °C (Note 1a) 14.5
-Pulsed 200
EAS Single Pulse Avalanche Energy (Note 3) 216 mJ
PDPower Dissipation TC = 25 °C 125 W
Power Dissipation T A = 25 °C (Note 1a) 3.2
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case (Top Source) 2.3
°C/W
RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81
RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23
RθJA Thermal Resistance, Junction to Ambient (Note 1k) 1 1
Device Marking Device Package Reel Size Tape Width Quantity
86101 FDMS86101DC Dual CoolTM 56 13’’ 12 mm 3000 units
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
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©2013 Fairchild Semiconductor Cor poration
FDMS86101DC Rev. 1.7
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characte ri st ic s
Dynamic Characterist ic s
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25°C 70 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA22.74V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -10 mV/°C
rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 14.5 A 6 7.5 mΩVGS = 6 V, ID = 11.5 A 8.3 12
VGS = 10 V, ID = 14.5 A, TJ = 125 °C 10 13
gFS Forward Transconductance VDD = 10 V, ID = 14.5 A 44 S
Ciss Input Capacitance VDS = 50 V, VGS = 0 V,
f = 1 MHz
2354 3135 pF
Coss Output Capacitance 467 625 pF
Crss Reverse Transfer Capacitance 23 35 pF
RgGate Resistance 0.1 1.4 3 Ω
td(on) Turn-On Del ay Time VDD = 50 V , ID = 14.5 A,
VGS = 10 V, RGEN = 6 Ω
14 25 ns
trRise Time 8.2 17 ns
td(off) Turn-Off Delay Time 25 40 ns
tfFall Time 5.5 11 ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 50 V
ID = 14.5 A
31 44 nC
Total Gate Charge VGS = 0 V to 5 V 18 25 nC
Qgs Total Gate Charge 8.3 nC
Qgd Gate to Drain “Miller” Charge 7 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.7 A (Note 2) 0.71 1.2 V
VGS = 0 V, IS = 14.5 A (Note 2) 0.78 1.3
trr Reverse Recovery Time IF = 14.5 A, di/dt = 100 A/μs 54 87 ns
Qrr Reverse Recovery Charge 62 99 nC
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
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©2013 Fairchild Semiconductor Cor poration
FDMS86101DC Rev. 1.7
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case (Top Source) 2.3
°C/W
RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81
RθJA Thermal Resistance, Junction to Ambient (Note 1c) 27
RθJA Thermal Resistance, Junction to Ambient (Note 1d) 34
RθJA Thermal Resistance, Junction to Ambient (Note 1e) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1f) 19
RθJA Thermal Resistance, Junction to Ambient (Note 1g) 26
RθJA Thermal Resistance, Junction to Ambient (Note 1h) 61
RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23
RθJA Thermal Resistance, Junction to Ambient (Note 1k) 1 1
RθJA Thermal Resistance, Junction to Ambient (Note 1l) 13
NOTES:
1. RθJA is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz copper
h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper
i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 38 A, VDD = 90 V, VGS = 10 V.
a. 38 °C/W when mounted on
a 1 in2 pad of 2 oz copper b. 81 °C/W when mounted on
a minimum pad of 2 oz copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
www.fairchildsemi.com
4
©2013 Fairchild Semiconductor Corporation
FDMS86101DC Rev. 1.7
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
012345
0
50
100
150
200
VGS = 6 V
VGS = 10 V
VGS = 7 V
VGS = 8 V
VGS = 5 V
PULSE DU R ATION = 80 μs
DUTY CYCLE = 0.5% MA X
ID, DRAIN CURRENT (A)
VDS, DR AIN TO S OURCE VO LTAGE (V )
On-Region Characteristics Figure 2.
0 50 100 150 200
0
1
2
3
4
5
VGS = 8 V
PULSE D U RA TION = 80 μs
DUTY CYCLE = 0.5% MA X
NORMALIZED
DRAIN TO SOU RC E ON-RESISTA NCE
ID, DRA IN CURRENT (A)
VGS = 6 V
VGS = 5 V
VGS = 7 V
VGS = 10 V
Normalized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
ID = 14.5 A
VGS = 10 V
NORMALIZED
DRAIN TO SO UR CE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Te mperature Figure 4.
45678910
0
5
10
15
20
25
TJ = 125 oC
ID = 14.5 A
TJ = 25 oC
VGS, G ATE TO SOURCE VOLTAG E (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DU R ATION = 80 μs
DUTY CYCLE = 0.5% MA X
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
2345678
0
50
100
150
200
TJ = 25 oC
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% M A X
TJ = -55 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
www.fairchildsemi.com
5
©2013 Fairchild Semiconductor Corporation
FDMS86101DC Rev. 1.7
Figure 7.
0 8 16 24 32
0
2
4
6
8
10
ID = 14.5 A
VDD = 25 V
VDD = 50 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 75 V
Gate Charge Characteristics Figure 8.
0.1 1 10 100
10
100
1000
5000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100 300
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
Uncl a mped I nduc t ive
Switching Capability Figure 10.
25 50 75 100 125 150
0
15
30
45
60
75
90
Limited by Package VGS = 6 V
RθJC = 1.0 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERA TURE (oC)
Maximum Continuous Drain
Current vs Case Temperature
Figure 11.
0.01 0.1 1 10 100 500
0.01
0.1
1
10
100
300
10 s
10 ms
DC
1 s
100 m s
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MA X RA TED
RθJA = 81 oC/W
TA = 25 oC
Forward Bias Safe
Operating Area Figure 12. Single Pulse Maximum
Power Dissipation
10-3 10-2 10-1 110
100 1000
1
10
100
1000
2000 SINGLE PULSE
RθJA = 81 oC/W
TA = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench® MOSFET
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©2013 Fairchild Semiconductor Corporation
FDMS86101DC Rev. 1.7
Figure 13. Junction-to-Ambient Transient Thermal Respon se Curve
10-3 10-2 10-1 110
100 1000
0.001
0.01
0.1
1
2
SINGLE PULSE
RθJA = 81 oC/W
DUTY CYC L E-D ESCEND ING O R DER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
Typical Characteristics TJ = 25 °C unless otherwise noted
C
L
L
C
5.00
4.80
5.85
5.50
C
1.27
3.86
3.61
CHAMFER
CORNER
AS PIN #1
IDENT MAY
APPEAR AS
OPTIONAL
1.27
3.81
1.27
3.91 1.27
123
4
8567
14
85
LAND PATTERN
RECOMMENDATION
12 3 4
876
0.10 C A B
0.50
0.40 (8X)
5
0.77
A
B
(0.34)
0.61
NOTES:
A) PACKAGE IS NOT FULLY COMPLIANT
TO JEDEC MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08DREV4
SEE
DETAIL A
SCALE: 2:1
0.05
0.00
0.30
0.20
0.08 C
OPTIONAL DRAFT ANGLE
MAY APPEAR ON FOUR
SIDES OF THE PACKAGE
OPTIONAL PIN 1
INDICATOR
SEATING
PLANE
0.10 C
1.05
0.95
7°
0.1 MAX
(0.90)
(2.60)
(3.30)
0.71
0.44
(0.82)
5.10
3.81
KEEP-
OUT
AREA
4.90
5.80
A
A
A
A
A(1.40)
3.58
3.38 (0.20)
A
0.41
0.31
A(8X)
(2.08)
0.65
0.45
(4X)
(4X)
(8X)
0.35
0.25 0.40
0.30
(0.50)
.1 C
.1 C
(2X)
(2X)
(1.05)
(1.02)
2.67
2.04
1.22
2.54
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