FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET 100 V, 60 A, 7.5 m Features General Description Shielded Gate MOSFET Technology High performance technology for extremely low rDS(on) This N-Channel MOSFET is produced using Fairchild Semiconductor's advanced PowerTrench(R) process that incorporates Shielded Gate technology. Advancements in both silicon and Dual CoolTM package technologies have been combined to offer the lowest rDS(on) while maintaining excellent switching performance by extremely low Junction-to-Ambient thermal resistance. 100% UIL Tested Applications RoHS Compliant Primary DC-DC MOSFET Dual Cool TM Top Side Cooling PQFN package Max rDS(on) = 7.5 m at VGS = 10 V, ID = 14.5 A Max rDS(on) = 12 m at VGS = 6 V, ID = 11.5 A Secondary Synchronous Rectifier Load Switch D D D S Pin 1 S D S D S D G D D G Top S S Pin 1 S Bottom Dual CoolTM 56 MOSFET Maximum Ratings TA = 25 C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 C -Continuous TA = 25 C TJ, TSTG 20 V (Note 1a) 14.5 A 200 Single Pulse Avalanche Energy PD Units V 60 -Pulsed EAS Ratings 100 (Note 3) Power Dissipation TC = 25 C Power Dissipation TA = 25 C 216 125 (Note 1a) Operating and Storage Junction Temperature Range 3.2 -55 to +150 mJ W C Thermal Characteristics RJC Thermal Resistance, Junction to Case (Top Source) 2.3 RJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0 RJA Thermal Resistance, Junction to Ambient (Note 1a) 38 RJA Thermal Resistance, Junction to Ambient (Note 1b) 81 RJA Thermal Resistance, Junction to Ambient (Note 1i) 16 RJA Thermal Resistance, Junction to Ambient (Note 1j) 23 RJA Thermal Resistance, Junction to Ambient (Note 1k) 11 C/W Package Marking and Ordering Information Device Marking 86101 Device FDMS86101DC (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 Package Dual CoolTM 56 1 Reel Size 13'' Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET July 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 A, VGS = 0 V BVDSS TJ Breakdown Voltage Temperature Coefficient ID = 250 A, referenced to 25C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 A IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 4 V 100 V 70 mV/C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 A VGS(th) TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 A, referenced to 25 C rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 11.5 A 8.3 12 VGS = 10 V, ID = 14.5 A, TJ = 125 C 10 13 VDD = 10 V, ID = 14.5 A 44 2 -10 VGS = 10 V, ID = 14.5 A gFS Forward Transconductance 2.7 6 mV/C 7.5 m S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V, f = 1 MHz 0.1 2354 3135 pF 467 625 pF 23 35 pF 1.4 3 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 50 V , ID = 14.5 A, VGS = 10 V, RGEN = 6 Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 5 V Qgs Total Gate Charge Qgd Gate to Drain "Miller" Charge VDD = 50 V ID = 14.5 A 14 25 ns 8.2 17 ns 25 40 ns 5.5 11 ns 31 44 nC 18 25 nC 8.3 nC 7 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 VGS = 0 V, IS = 2.7 A (Note 2) 0.71 1.2 VGS = 0 V, IS = 14.5 A (Note 2) 0.78 1.3 IF = 14.5 A, di/dt = 100 A/s 2 V 54 87 ns 62 99 nC www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET Electrical Characteristics TJ = 25 C unless otherwise noted RJC Thermal Resistance, Junction to Case (Top Source) 2.3 RJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0 RJA Thermal Resistance, Junction to Ambient (Note 1a) 38 RJA Thermal Resistance, Junction to Ambient (Note 1b) 81 RJA Thermal Resistance, Junction to Ambient (Note 1c) 27 RJA Thermal Resistance, Junction to Ambient (Note 1d) 34 RJA Thermal Resistance, Junction to Ambient (Note 1e) 16 RJA Thermal Resistance, Junction to Ambient (Note 1f) 19 RJA Thermal Resistance, Junction to Ambient (Note 1g) 26 RJA Thermal Resistance, Junction to Ambient (Note 1h) 61 RJA Thermal Resistance, Junction to Ambient (Note 1i) 16 RJA Thermal Resistance, Junction to Ambient (Note 1j) 23 RJA Thermal Resistance, Junction to Ambient (Note 1k) 11 RJA Thermal Resistance, Junction to Ambient (Note 1l) 13 C/W NOTES: 1. RJA is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. RJC is guaranteed by design while RCA is determined by the user's board design. b. 81 C/W when mounted on a minimum pad of 2 oz copper a. 38 C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz copper h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. 3. Starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 38 A, VDD = 90 V, VGS = 10 V. (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 3 www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET Thermal Characteristics 5 VGS = 8 V VGS = 10 V ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 200 VGS = 7 V VGS = 6 V 150 100 VGS = 5 V 50 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS = 5 V 4 VGS = 6 V 3 VGS = 7 V 2 1 0 0 50 100 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics 200 25 ID = 14.5 A VGS = 10 V 2.0 rDS(on), DRAIN TO 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (m) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 150 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.2 ID = 14.5 A PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 20 15 TJ = 125 oC 10 5 0 4 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) TJ = 25 oC 5 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage IS, REVERSE DRAIN CURRENT (A) 200 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10 V VGS = 8 V PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 VDS = 5 V 100 TJ = 150 oC 50 TJ = 25 oC 200 100 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 TJ = -55 oC 0 2 3 4 5 6 7 0.001 0.0 8 Figure 5. Transfer Characteristics (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted 5000 ID = 14.5 A Ciss VDD = 25 V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V 6 VDD = 75 V 4 1000 Coss 100 2 f = 1 MHz VGS = 0 V 0 0 8 16 24 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage 100 TJ ID, DRAIN CURRENT (A) 90 = 25 oC 10 TJ = 100 oC TJ = 125 oC 75 60 VGS = 10 V 45 VGS = 6 V Limited by Package 30 15 o RJC = 1.0 C/W 1 0.001 0.01 0.1 1 10 0 25 100 300 50 150 2000 P(PK), PEAK TRANSIENT POWER (W) 100 1 ms 10 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms SINGLE PULSE TJ = MAX RATED 1s RJA = 81 oC/W 10 s TA = 25 oC 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 300 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) IAS, AVALANCHE CURRENT (A) Crss 10 0.1 32 0.1 DC 1 10 100 500 TA = 25 oC 100 10 1 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 SINGLE PULSE RJA = 81 oC/W 1000 Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA SINGLE PULSE o RJA = 81 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve (c)2013 Fairchild Semiconductor Corporation FDMS86101DC Rev. 1.7 6 www.fairchildsemi.com FDMS86101DC N-Channel Dual CoolTM 56 Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted (2X) A .1 C 4.90 (2X) A (2.60) (0.90) 5.10 .1 C CL 8 0.77 B 5 CL 8 7 6 1.27 5 KEEPOUT 2.04 AREA 2.54 A (3.30) 3.91 5.80 1.22 (2.08) 2.67 (0.82) 1 1.27 4 (1.05) OPTIONAL PIN 1 INDICATOR 1 SEE DETAIL A 2 3 4 0.61 1.27 3.81 LAND PATTERN RECOMMENDATION A 5.00 4.80 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR A 0.41 (8X) SIDES OF THE PACKAGE 0.31 0.50 (8X) 0.40 7 0.10 C A B 3.81 1.27 (0.34) 1 2 3 A 0.71 (4X) 0.44 4 A (1.40) 0.35 0.25 0.40 0.30 CHAMFER CORNER AS PIN #1 IDENT MAY APPEAR AS OPTIONAL 3.58 3.38 1.05 0.95 (0.50) 5.85 A 5.50 (0.20) (8X) 8 7 6 5 0.65 0.45 (4X) 3.86 3.61 0.1 MAX 0.10 C 0.08 C (1.02) 0.30 0.20 SCALE: 2:1 0.05 0.00 C SEATING PLANE NOTES: A) PACKAGE IS NOT FULLY COMPLIANT TO JEDEC MO-240, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08DREV4 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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