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5/3/06
DirectFET Power MOSFET
Description
The IRF6635PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packag-
ing to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The
DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and
vapor phase, infra-red or convection soldering techniques. Application note AN-1035 is followed regarding the manufacturing
methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems,
improving previous best thermal resistance by 80%.
The IRF6635PbF balances industry leading on-state resistance while minimizing gate charge along with ultra low package
inductance to reduce both conduction and switching losses. The reduced losses make this product ideal for high frequency/
high efficiency DC-DC converters that power high current loads such as the latest generation of microprocessors. The
IRF6635PbF has been optimized for parameters that are critical in synchronous buck converter’s SyncFET sockets.
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
Fig 1. Typical On-Resistance vs. Gate-to-Source Voltage
Typical values (unless otherwise specified)
Fig 2. Total Gate Charge vs. Gate-to-Source Voltage
SQ SX ST MQ MX MT
DirectFET ISOMETRIC
MX
VDSS VGS RDS(on) RDS(on)
30V max ±20V max 1.3m@ 10V 1.8m@ 4.5V
Qg tot Qgd Qgs2 Qrr Qoss Vgs(th)
47nC 17nC 4.7nC 48nC 29nC 1.8V
012345678910
VGS, Gate -to -Source Vol tage (V)
0
2
4
6
8
10
Typical RDS(on) (m)
ID = 32A
TJ = 25°C
TJ = 125°C
0 102030405060
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
VDS = 24V
VDS = 15V
ID= 25A
PD - 97086
l RoHs Compliant
l Lead-Free (Qualified up to 260°C Reflow)
l Application Specific MOSFETs
lIdeal for CPU Core DC-DC Converters
l Low Conduction Losses
l High Cdv/dt Immunity
l Low Profile (<0.7mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount Techniques
IRF6635PbF
IRF6635TRPbF
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.63mH, RG = 25, IAS = 25A.
Notes:
Absolute Maximum Ratin
g
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
e
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V
e
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
f
IDM Pulsed Drain Current
g
EAS Single Pulse Avalanche Energy
h
mJ
IAR Avalanche Current
g
A
Max.
25
180
250
±20
30
32
200
25
IRF6635PbF
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Repetitive rating; pulse width limited by max. junction temperature.
Pulse width 400µs; duty cycle 2%.
Notes:
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V
∆ΒVDSS/TJ Breakdown Voltage Temp. Coefficient ––– 24 ––– mV/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 1.3 1.8 m
––– 1.8 2.4
VGS(th) Gate Threshold Voltage 1.35 1.8 2.35 V
VGS(th)/TJGate Threshold Voltage Coefficient ––– -6.1 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 45 ––– ––– S
QgTotal Gate Charge ––– 47 71
Qgs1 Pre-Vth Gate-to-Source Charge ––– 12 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 4.7 ––– nC
Qgd Gate-to-Drain Charge ––– 17
Qgodr Gate Charge Overdrive ––– 13 ––– See Fig. 15
Qsw Switch Charge (Qgs2 + Qgd)––– 22 –––
Qoss Output Charge ––– 29 ––– nC
RGGate Resistance ––– 1.0 –––
td(on) Turn-On Delay Time ––– 21 –––
trRise Time ––– 13 –––
td(off) Turn-Off Delay Time ––– 33 ––– ns
tfFall Time ––– 8.3 –––
Ciss Input Capacitance ––– 5970 –––
Coss Output Capacitance ––– 1280 ––– pF
Crss Reverse Transfer Capacitance ––– 600 –––
Diode Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 110
(Body Diode) A
ISM Pulsed Source Current ––– ––– 250
(Body Diode)g
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Recovery Time ––– 20 30 ns
Qrr Reverse Recovery Charge ––– 48 72 nC
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 4.5V
ID = 25A
VGS = 0V
VDS = 15V
ID = 25A
TJ = 25°C, IF = 25A
di/dt = 500A/µs iSee Fig. 18
TJ = 25°C, IS = 25A, VGS = 0V i
showing the
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 32A i
VGS = 4.5V, ID = 25A i
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
MOSFET symbol
Clamped Inductive Load
VDS = 15V, ID = 25A
Conditions
See Fig. 16 & 17
ƒ = 1.0MHz
VDS = 16V, VGS = 0V
VDD = 16V, VGS = 4.5Vi
VDS = 15V
IRF6635PbF
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Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
0.6784 0.001268
17.299 0.033387
17.566 0.508924
9.4701 11.19309
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci= τi/Ri
Ci= τi/Ri
τA
τA
τ4
τ4
R4
R4
Used double sided cooling, mounting pad with large heatsink.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Notes:
Rθ is measured at TJ of approximately 90°C.
Surface mounted on 1 in. square Cu
(still air).
Mounted to a PCB with
small clip heatsink (still air)
Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
Absolute Maximum Ratin
g
s
Parameter Units
PD @TA = 25°C Power Dissipation
e
W
PD @TA = 70°C Power Dissipation
e
PD @TC = 25°C Power Dissipation
f
TP Peak Soldering Temperature °C
TJ Operating Junction and
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJA Junction-to-Ambient
el
––– 45
RθJA Junction-to-Ambient
jl
12.5 –––
RθJA Junction-to-Ambient
kl
20 ––– °C/W
RθJC Junction-to-Case
fl
––– 1.4
RθJ-PCB Junction-to-PCB Mounted 1.0 –––
Linear Derating Factor
e
W/°C
0.022
270
-40 to + 150
Max.
89
2.8
1.8
IRF6635PbF
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Fig 5. Typical Output Characteristics
Fig 4. Typical Output Characteristics
Fig 6. Typical Transfer Characteristics Fig 7. Normalized On-Resistance vs. Temperature
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage Fig 9. Normalized Typical On-Resistance vs.
Drain Current and Gate Voltage
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
60µs PULSE WIDTH
Tj = 150°C
VGS
TOP 10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
BOTTOM 2.5V
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
BOTTOM 2.5V
60µs PULSE WIDTH
Tj = 25°C
2.5V
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
Typical RDS(on) (Normalized)
ID = 32A
VGS = 4.5V
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
20 60 100 140 180 220 260
ID, Drain Current (A)
0
5
10
15
20
25
30
Typical RDS(on) Normalized (m)
TJ = 25°C
Vgs = 3.0V
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 10V
1 2 3 4
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 150°C
TJ = 25°C
TJ = -40°C
VDS = 15V
60µs PULSE WIDTH
IRF6635PbF
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Fig 13. Threshold Voltage vs. Temperature
Fig 12. Maximum Drain Current vs. Case Temperature
Fig 10. Typical Source-Drain Diode Forward Voltage Fig11. Maximum Safe Operating Area
Fig 14. Maximum Avalanche Energy vs. Drain Current
0.01 0.10 1.00 10.00 100.00
VDS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
OPERATION I N THI S AREA
L IMITED BY R DS(on)
TA = 25°C
TJ = 150°C
Single Pulse
100µsec
1msec
10msec
100msec
25 50 75 100 125 150
TC , Case Temperature (°C)
0
25
50
75
100
125
150
175
200
ID, Drain Current (A)
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
VGS(th) Gate threshold Voltage (V)
ID = 250µA
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
0
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 150°C
TJ = 25°C
TJ = -40°C
VGS = 0V
25 50 75 100 125 150
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
900
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 9.1A
11A
BOTTOM 25A
IRF6635PbF
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Fig 15a. Gate Charge Test Circuit Fig 15b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 16b. Unclamped Inductive Waveforms
tp
V
(BR)DSS
I
AS
Fig 16a. Unclamped Inductive Test Circuit
Fig 17b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
Fig 17a. Switching Time Test Circuit
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
1K
VCC
DUT
0
L
IRF6635PbF
www.irf.com 7
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
Inductor Current
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
+
-
+
+
+
-
-
-
RGVDD
D.U.T
DirectFET Substrate and PCB Layout, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
D
D
G
S
S
IRF6635PbF
8www.irf.com
DirectFET Outline Dimension, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DirectFET Part Marking
CODE
A
B
C
D
E
F
G
H
J
K
L
M
R
P
MAX
0.250
0.201
0.156
0.018
0.028
0.028
0.056
0.033
0.017
0.039
0.095
0.0274
0.0031
0.007
MAX
6.35
5.05
3.95
0.45
0.72
0.72
1.42
0.84
0.42
1.01
2.41
0.676
0.080
0.17
MIN
6.25
4.80
3.85
0.35
0.68
0.68
1.38
0.80
0.38
0.88
2.28
0.616
0.020
0.08
MIN
0.246
0.189
0.152
0.014
0.027
0.027
0.054
0.032
0.015
0.035
0.090
0.0235
0.0008
0.003
DIMENSIONS
METRIC IMPERIAL
IRF6635PbF
www.irf.com 9
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/06
DirectFET Tape & Reel Dimension (Showing component orientation).
REEL DIMENSIONS
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6635TRPBF). For 1000 parts on 7"
reel, order IRF6635TR1PBF
STANDARD OPTION (QTY 4800)
MIN
330.0
20.2
12.8
1.5
100.0
N.C
12.4
11.9
CODE
A
B
C
D
E
F
G
H
MAX
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
MIN
12.992
0.795
0.504
0.059
3.937
N.C
0.488
0.469
MAX
N.C
N.C
0.520
N.C
N.C
0.724
0.567
0.606
METRIC IMPERIAL
TR1 OPTION (QTY 1000)
IMPERIAL
MIN
6.9
0.75
0.53
0.059
2.31
N.C
0.47
0.47
MAX
N.C
N.C
12.8
N.C
N.C
13.50
12.01
12.01
MIN
177.77
19.06
13.5
1.5
58.72
N.C
11.9
11.9
METRIC
MAX
N.C
N.C
0.50
N.C
N.C
0.53
N.C
N.C
LOADED TAPE FEED DIRECTION
MIN
7.90
3.90
11.90
5.45
5.10
6.50
1.50
1.50
CODE
A
B
C
D
E
F
G
H
MAX
8.10
4.10
12.30
5.55
5.30
6.70
N.C
1.60
MIN
0.311
0.154
0.469
0.215
0.201
0.256
0.059
0.059
MAX
0.319
0.161
0.484
0.219
0.209
0.264
N.C
0.063
DIMENSIONS
METRIC IMPERIAL
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/