1
Copyright
©
Cirrus Logic, Inc. 2004
(All Rights Reserved)
Cirrus Logic, Inc.
http://www.cirrus.com
CS4334/5/8/9
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
24-Bit Conversion
96 dB Dynamic Range
-88 dB THD+N
Low Clock Jitter Sensitivity
Single +5 V Power Supply
Filtered Line Level Outputs
On-Chip Digital De-emphasis
Popguard® Technology
Functionally Compatible with CS4330/31/33
Description
The CS4334 family members are complete, stereo
digital-to-analog output systems including interpolation,
1-bit D/A conversion and output analog filtering in an
8-pin package. The CS4334/5/8/9 support all major
audio data interface formats, and the individual devices
differ only in the supported interface format.
The CS4334 family is based on Delta-Sigma modulation,
where the modulator output controls the reference volt-
age input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
The CS4334 family contains on-chip digital de-empha-
sis, operates from a single +5V power supply, and
requires minimal support circuitry. These features are
ideal for set-top boxes, DVD players, SVCD players, and
A/V receivers.
ORDERING INFORMATION
See page 24
I
LRCK 3
SDATA 1
DEM/SCLK
2
MCLK
4
VA
AOUTL
8
AOUTR
5
Serial Input
Interface
Interpolator
Interpolator
De-emphasis
Modulator
∆Σ
Modulator
DAC
DAC
Voltage Reference
Analog
Low-Pass
Filter
Analog
Low-Pass
Filter
7
AGND
6
∆Σ
JUL ‘04
DS248F3
CS4334/5/8/9
2DS248F3
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 8
SWITCHING CHARACTERISTICS .......................................................................................... 9
2. TYPICAL CONNECTION DIAGRAM ..................................................................................... 11
3. GENERAL DESCRIPTION .................................................................................................... 12
3.1 Digital Interpolation Filter ................................................................................................. 12
3.2 Delta-Sigma Modulator .................................................................................................... 12
3.3 Switched-Capacitor DAC ................................................................................................. 12
3.4 Analog Low-Pass Filter .................................................................................................... 12
4. SYSTEM DESIGN .................................................................................................................. 13
4.1 Master Clock .................................................................................................................... 13
4.2 Serial Clock ...................................................................................................................... 13
4.2.1 External Serial Clock Mode ................................................................................. 13
4.2.2 Internal Serial Clock Mode .................................................................................. 13
4.3 De-Emphasis ................................................................................................................... 13
4.4 Initialization and Power-Down .......................................................................................... 14
4.5 Output Transient Control .................................................................................................. 14
4.6 Grounding and Power Supply Decoupling ....................................................................... 14
4.7 Analog Output and Filtering ............................................................................................. 14
4.8 Overall Base-Rate Frequency Response ........................................................................ 18
4.9 Overall High-Rate Frequency Response ......................................................................... 19
4.10 Base Rate Mode Performance Plots .............................................................................. 20
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the infor-
mation is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain
the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are
sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringe-
ment, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for
manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other
intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of
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to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHO-
RIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COM-
PONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICA-
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STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES
OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY
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ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
I²C is a registered trademark of Philips Semiconductor. Purchase of I²C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies con-
veys a license under the Phillips I²C Patent Rights to use those components in a standard I²C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard® are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/
CS4334/5/8/9
DS248F3 3
4.11 High Rate Mode Performance Plots .............................................................................. 21
5. PIN DESCRIPTIONS ............................................................................................................. 22
6. PARAMETER DEFINITIONS ................................................................................................. 23
7. REFERENCES ....................................................................................................................... 23
8. ORDERING INFORMATION: ............................................................................................... 24
9. FUNCTIONAL COMPATIBILITY ........................................................................................... 24
10. PACKAGE DIMENSIONS ................................................................................................... 25
LIST OF FIGURES
Figure 1. Output Test Load .......................................................................................................... 7
Figure 2. Maximum Loading......................................................................................................... 7
Figure 3. Power vs. Sample Rate ................................................................................................ 7
Figure 4. External Serial Mode Input Timing.............................................................................. 10
Figure 5. Internal Serial Mode Input Timing ............................................................................... 10
Figure 6. Internal Serial Clock Generation ................................................................................ 10
Figure 7. Recommended Connection Diagram.......................................................................... 11
Figure 8. System Block Diagram................................................................................................ 12
Figure 9. De-Emphasis Curve (Fs = 44.1kHz) ........................................................................... 13
Figure 10. CS4334 Data Format (I2S).......................................................................................... 15
Figure 11. CS4335 Data Format .................................................................................................. 15
Figure 12. CS4338 Data Format .................................................................................................. 15
Figure 13. CS4339 Data Format .................................................................................................. 16
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence ............................................ 17
Figure 15. Stopband Rejection..................................................................................................... 18
Figure 16. Transition Band........................................................................................................... 18
Figure 17. Transition Band........................................................................................................... 18
Figure 18. Passband Ripple......................................................................................................... 18
Figure 19. Stopband Rejection..................................................................................................... 19
Figure 20. Transition Band........................................................................................................... 19
Figure 21. Transition Band........................................................................................................... 19
Figure 22. Passband Ripple......................................................................................................... 19
Figure 23. 0 dBFS FFT (BRM) ..................................................................................................... 20
Figure 24. -60 dBFS FFT (BRM).................................................................................................. 20
Figure 25. Idle Channel Noise FFT (BRM)................................................................................... 20
Figure 26. Twin Tone IMD FFT (BRM)......................................................................................... 20
Figure 27. THD+N vs. Amplitude (BRM) ...................................................................................... 20
Figure 28. THD+N vs. Frequency (BRM) ..................................................................................... 20
Figure 29. 0 dBFS FFT (HRM)..................................................................................................... 21
Figure 30. -60 dBFS FFT (HRM).................................................................................................. 21
Figure 31. Idle Channel Noise FFT (HRM) .................................................................................. 21
Figure 32. Twin Tone IMD FFT (HRM) ........................................................................................ 21
Figure 33. THD+N vs. Amplitude (HRM)...................................................................................... 21
Figure 34. THD+N vs. Frequency (HRM)..................................................................................... 21
Figure 35.
LIST OF TABLES
Table 1. Common Clock Frequencies ..................................................................................... 13
Table 2.
CS4334/5/8/9
4DS248F3
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Parameters Symbol Min Nom Max Units
DC Power Supply VA 4.75 5.0 5.5 V
Ambient Operating Temperature (Power Applied) -KS
-BS/-DS TA
-10
-40
-
-
+70
+85
°C
°C
Parameters Symbol Min Max Units
DC Power Supply VA -0.3 6.0 V
Input Current, Any Pin Except Supplies Iin -±10mA
Digital Input Voltage VIND -0.3 VA+0.4 V
Ambient Operating Temperature (power applied) TA-55 125 °C
Storage Temperature Tstg -65 150 °C
CS4334/5/8/9
DS248F3 5
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load RL = 10 kΩ, CL =
10 pF (see Figure 1). Fs for Base-Rate Mode = 48 kHz, Measurement Bandwidth 10 Hz to 20 kHz, unless other-
wise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise spec-
ified.)
Note: 1. One-half LSB of triangular PDF dither added to data.
Parameter
Base-Rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance for CS4334/5/8/9-KS
Dynamic Range (Note 1)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
88
91
86
89
93
96
91
94
-
-
-
-
-
91
-
89
90
96
88
94
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-83
-68
-28
-81
-66
-26
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-83
-65
-25
-81
-63
-23
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 94 - - 95 - dB
Dynamic Performance for CS4334/5/8/9-BS/-DS
Dynamic Range (Note 1)
18 to 24-Bit unweighted
A-Weighted
16-Bit unweighted
A-Weighted
85
88
83
86
93
96
91
94
-
-
-
-
-
88
-
86
90
96
88
94
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-82
-65
-25
-70
-63
-23
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-82
-62
-22
-80
-60
-20
dB
dB
dB
dB
dB
dB
Interchannel Isolation (1 kHz) - 94 - - 95 - dB
CS4334/5/8/9
6DS248F3
ANALOG CHARACTERISTICS (Continued)
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 15-22) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in High-Rate Mode.
6. Refer to Figure 2.
Parameter
Base-Rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response
(Note 2)
Passband (Note 3)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4780
-
.4996
-
0
0
-
-
-
-
.4650
.4982
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz -.01 - +.08 -.05 - +.2 dB
Passband Ripple - - ±.08 - - ±.2 dB
StopBand .5465 - - .5770 - - Fs
StopBand Attenuation (Note 4) 50 - - 55 - - dB
Group Delay tgd - 9/Fs - - 4/Fs - s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
- ±0.36/Fs - -
-
±1.39/Fs
±0.23/Fs
-
-
s
s
De-emphasis Error Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
(Note 5)
dB
dB
dB
Parameters Symbol Min Typ Max Units
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.4 dB
Gain Error - ±5 - %
Gain Drift - 100 - ppm/°C
Analog Output
Full Scale Output Voltage 3.25 3.5 3.75 Vpp
Quiescent Voltage VQ-2.2-VDC
Max AC-Load Resistance (Note 6) RL-3-kΩ
Max Load Capacitance (Note 6) CL- 100 - pF
CS4334/5/8/9
DS248F3 7
POWER AND THERMAL CHARACTERISTICS
Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V.
Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current normal operation
power-down state
IA
IA
-
-
15
40
19
-
mA
µA
Power Dissipation (Note 7)
normal operation
power-down
-
-
75
0.2
104
-
mW
mW
Package Thermal Resistance θJA -110-°C/Watt
Power Supply Rejection Ratio (1 kHz) PSRR - 79 - dB
AOUTx
AGND
10 µF
Vout
RLCL
Figure 1. Output Test Load
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k
Ω
)
L
125
3
20
Figure 2. Maximum Loading
75
50
30
Power (mW)
Sample Rate (kHz)
BRM
HRM
70
65
60
55
40 50 60 70 80 90 100
Figure 3. Power vs. Sample Rate
CS4334/5/8/9
DS248F3 9
SWITCHING CHARACTERISTICS
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures 10-13)
Parameters Symbol Min Typ Max Units
Input Sample Rate Fs 2 - 100 kHz
MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns
MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only) 40 50 60 %
SCLK Pulse Width Low tsclkl 20 - - ns
SCLK Pulse Width High tsclkh 20 - - ns
SCLK Period Base-Rate Mode
MCLK / LRCK = 512, 256 or 384
tsclkw --ns
SCLK Period High-Rate Mode
MCLK / LRCK = 128 or 192
tsclkw --ns
SCLK rising to LRCK edge delay tslrd 20 - - ns
SCLK rising to LRCK edge setup time tslrs 20 - - ns
SDATA valid to SCLK rising setup time tsdlrs 20 - - ns
SCLK rising to SDATA hold time tsdh 20 - - ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - %
SCLK Period (Note 10) tsclkw --ns
SCLK rising to LRCK edge tsclkr --µs
SDATA valid to SCLK rising setup time tsdlrs --ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh --ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh --ns
1
128()Fs
----------------------
1
64()Fs
-------------------
1
SCLK
-----------------
tsclkw
2
------------------
1
512()Fs
----------------------10+
1
512()Fs
----------------------15+
1
384()Fs
----------------------15+
CS4334/5/8/9
10 DS248F3
sclkh
t
slrs
t
slrd
t
sdlrs
tsdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 4. External Serial Mode Input Timing
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 5. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4334/5/8/9.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1N
2
N
Figure 6. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/8/9.
N equals MCLK divided by SCLK
CS4334/5/8/9
DS248F3 11
2. TYPICAL CONNECTION DIAGRAM
DEM/SCLK
6
Audio
Data
Processor
External Clock MCLK
AGND
AOUTR
CS4334
CS4335
CS4338
CS4339
SDATA
LRCK
VA
AOUTL
3
1
2
4
70.1 µF
+
1µF
8Left Audio
Output
5
Right Audio
Output
+5V
3.3 µF
10 kΩC
560 Ω
+
R+560
C= 4πFs(R 560)
RL
3.3 µF
10 kΩC
560 Ω
+
267 k RL
L
L
Ω
267 kΩ
Figure 7. Recommended Connection Diagram
CS4334/5/8/9
12 DS248F3
3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete
stereo digital-to-analog system including digital
interpolation, fourth-order delta-sigma digital-to-
analog conversion, digital de-emphasis and analog
filtering, as shown in Figure 8. This architecture
provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modula-
tion techniques is to avoid the limitations of resis-
tive laser trimmed digital-to-analog converter
architectures by using an inherently linear 1-bit
digital-to-analog converter. The advantages of a
1-bit digital-to-analog converter include: ideal dif-
ferential linearity, no distortion mechanisms due to
resistor matching errors and no linearity drift over
time and temperature due to variations in resistor
values.
The CS4334 family of devices supports two modes
of operation. The devices operate in Base Rate
Mode (BRM) when MCLK/LRCK is 256, 384 or
512 and in High Rate Mode (HRM) when
MCLK/LRCK is 128 or 192. High Rate Mode al-
lows input sample rates up to 100 kHz.
3.1 Digital Interpolation Filter
The digital interpolation filter increases the sample
rate, Fs, by a factor of 4 and is followed by a
32× digital sample-and-hold (16× in HRM). This
filter eliminates images of the baseband audio sig-
nal which exist at multiples of the input sample
rate. The resulting frequency spectrum has images
of the input signal at multiples of 4 Fs. These imag-
es are easily removed by the on-chip analog low-
pass filter and a simple external analog filter (see
Figure 7).
3.2 Delta-Sigma Modulator
The interpolation filter is followed by a fourth
order delta-sigma modulator which converts the
interpolation filter output into 1-bit data at a rate of
128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
The delta-sigma modulator is followed by a digital-
to-analog converter which translates the 1-bit data
into a series of charge packets. The magnitude of
the charge in each packet is determined by sam-
pling of a voltage reference onto a switched capac-
itor, where the polarity of each packet is controlled
by the 1-bit data. This technique greatly reduces the
sensitivity to clock jitter and provides low-pass fil-
tering of the output.
3.4 Analog Low-Pass Filter
The final signal stage consists of a continuous-time
low-pass filter which serves to smooth the output
and attenuate out-of-band noise.
Interpolator
Delta-Sigma
Modulator DAC
Analog
Low-Pass
Filter
Analog
Output
Digital
Input
Figure 8. System Block Diagram
CS4334/5/8/9
DS248F3 13
4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio
sample rates including 48, 44.1 and 32 kHz in
BRM and 96, 88.2 and 64 kHz in HRM. Audio data
is input via the serial data input pin (SDATA). The
Left/Right Clock (LRCK) defines the channel and
delineation of data, and the Serial Clock (SCLK)
clocks audio data into the input data buffer. The
CS4334/5/8/9 differ in serial data formats as shown
in Figures 10-13.
4.1 Master Clock
MCLK must be either 256x, 384x or 512x the de-
sired input sample rate in BRM and either 128x or
192x the desired input sample rate in HRM. The
LRCK frequency is equal to Fs, the frequency at
which words for each channel are input to the de-
vice. The MCLK-to-LRCK frequency ratio is de-
tected automatically during the initialization
sequence by counting the number of MCLK transi-
tions during a single LRCK period. Internal divid-
ers are set to generate the proper clocks. Table 1
illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please
note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
Table 1. Common Clock Frequencies
4.2 Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4334 family supports
both external and internal serial clock generation
modes. Refer to Figures 10-13 for data formats.
4.2.1 External Serial Clock Mode
The CS4334 family will enter the External Serial
Clock Mode when 16 low to high transitions are
detected on the DEM/SCLK pin during any phase
of the LRCK period. When this mode is enabled,
the Internal Serial Clock Mode and de-emphasis
filter cannot be accessed. The CS4334 family will
switch to Internal Serial Clock Mode if no low to
high transitions are detected on the DEM/SCLK
pin for 2 consecutive frames of LRCK. Refer to
Figure 14.
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK frequency ratio is ei-
ther 32, 48, or 64 depending upon data format. Op-
eration in this mode is identical to operation with
an external serial clock synchronized with LRCK.
This mode allows access to the digital de-emphasis
function. Refer to Figures 10 - 14 for details.
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-em-
phasis. Figure 9 shows the de-emphasis curve for
Fs equal to 44.1 kHz. The frequency response of
the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 5 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
LRCK
(kHz)
MCLK (MHz)
HRM BRM
128x 192x 256x 384x 512x
32 4.0960 6.1440 8.1920 12.2880 16.3840
44.1 5.6448 8.4672 11.2896 16.9344 22.5792
48 6.1440 9.2160 12.2880 18.4320 24.5760
64 8.1920 12.2880 - - -
88.2 11.2896 16.9344 - - -
96 12.2880 18.4320 - - -
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
CS4334/5/8/9
14 DS248F3
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow
chart is shown in Figure 14. The CS4334 family en-
ters the Power-Down State upon initial power-up.
The interpolation filters and delta-sigma modula-
tors are reset, and the internal voltage reference,
one-bit digital-to-analog converters and switched-
capacitor low-pass filters are powered down. The
device will remain in the Power-Down mode until
MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are count-
ed over one LRCK period to determine the
MCLK/LRCK frequency ratio. Power is then ap-
plied to the internal voltage reference. Finally, pow-
er is applied to the D/A converters and switched-
capacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
4.5 Output Transient Control
The CS4334 family uses Popguard® technology to
minimize the effects of output transients during
power-up and power-down. This technique elimi-
nates the audio transients commonly produced by
single-ended single-supply converters when it is
implemented with external DC-blocking capacitors
connected in series with the audio outputs. To
make best use of this feature, it is necessary to un-
derstand its operation.
When the device is initially powered-up, the audio
outputs, AOUTL and AOUTR, are clamped to
AGND. After a short delay of approximately 1000
sample periods, each output begins to ramp to-
wards its quiescent voltage, VQ. Approximately
10,000 sample cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to VQ, effectively blocking the
quiescent DC voltage.
To prevent transients at power-down, the device
must first enter its power-down state. This is ac-
complished by removing MCLK or LRCK. When
this occurs, audio output ceases and the internal
output buffers are disconnected from AOUTL and
AOUTR. A soft-start current sink is substituted in
place of AOUTL and AOUTR which allows the
DC-blocking capacitors to slowly discharge. Once
this charge is dissipated, the power to the device
may be turned off, and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the power-
down state. If full discharge does not occur, a tran-
sient will occur when the audio outputs are initially
clamped to AGND. The time that the device must
remain in the power-down state is related to the
value of the DC-blocking capacitance. For exam-
ple, with a 3.3 µF capacitor, the time that the device
must remain in the power-down state will be ap-
proximately 0.4 seconds.
4.6 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4334
family requires careful attention to power supply
and grounding arrangements to optimize perfor-
mance. Figure 7 shows the recommended power ar-
rangement with VA connected to a clean +5V
supply. For best performance, decoupling capaci-
tors should be located as close to the device pack-
age as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a
switched-capacitor filter followed by a continuous
time low pass filter. Its response, combined with
that of the digital interpolator, is given in Figures
15 - 22.
CS4334/5/8/9
DS248F3 15
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
I2S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I2S)
LRCK
SCLK
Left Channel Right Channel
SDATA +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Internal SCLK Mode External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
LRCK
SCLK
Left Channel Right Channel
SDATA 654321098715 14 13 12 11 10 654321098715 14 13 12 11 10
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 12. CS4338 Data Format
CS4334/5/8/9
16 DS248F3
LRCK
SCLK
Left Channel Right Channel
SDATA 654321098715 14 13 12 11 10
10 654321098715 14 13 12 11 1017 16 17 16
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 18-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 13. CS4339 Data Format
CS4334/5/8/9
DS248F3 17
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence
CS4334/5/8/9
18 DS248F3
4.8 Overall Base-Rate Frequency Response
Figure 15. Stopband Rejection Figure 16. Transition Band
Figure 17. Transition Band Figure 18. Passband Ripple
CS4334/5/8/9
DS248F3 19
4.9 Overall High-Rate Frequency Response
Figure 19. Stopband Rejection Figure 20. Transition Band
Figure 21. Transition Band Figure 22. Passband Ripple
CS4334/5/8/9
20 DS248F3
4.10 Base Rate Mode Performance Plots
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
-14 0
+0
-13 0
-12 0
-11 0
-10 0
-9 0
-8 0
-7 0
-6 0
-5 0
-4 0
-3 0
-2 0
-1 0
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
20k
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
(16k FFT of a 1 kHz input signal)
Figure 23. 0 dBFS FFT (BRM)
(16k FFT of a 1 kHz input signal)
Figure 24. -60 dBFS FFT (BRM)
-14 0
+0
-13 0
-12 0
-11 0
-10 0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12 k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
(16k FFT with no input signal)
Figure 25. Idle Channel Noise FFT (BRM)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 26. Twin Tone IMD FFT (BRM)
-110
-60
-100
-90
-80
-70
d
B
r
A
-60 +0-50 -40 -30 -20 -10
dBFS
-50 -40 -30 -20 -10
dBFS
-60 +0
-110
-100
-90
-80
-70
-60
dBr A
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
dBr A
100
50 200 500 1k 2k 5k 10k
Hz
20 20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 27. THD+N vs. Amplitude (BRM)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 28. THD+N vs. Frequency (BRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
CS4334/5/8/9
DS248F3 21
4.11 High Rate Mode Performance Plots
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12 k 14 k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
-1 40
+0
-1 30
-1 20
-1 10
-1 00
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
(16k FFT of a 1 kHz input signal)
Figure 29. 0 dBFS FFT (HRM)
(16k FFT of a 1 kHz input signal)
Figure 30. -60 dBFS FFT (HRM)
-1 40
+0
-1 30
-1 20
-1 10
-1 00
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
A
u
di
o
P
rec
i
s
i
on
08/05/99
11
:
11
:
36D
-
A
CCIF
IMD
vs
AMPLITUDE
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
2k 4k 6k 8k 10k 12k 14k 16k 18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr A
2k 6k4k 8k 10k 12k 14k 16k 18k 20k
Hz
(16k FFT with no input signal)
Figure 31. Idle Channel Noise FFT (HRM)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 32. Twin Tone IMD FFT (HRM)
-110
-60
-100
-90
-80
-70
d
B
r
A
-60 +0-50 -40 -30 -20 -10
dBFS
-50 -40 -30 -20 -10
dBFS
-60 +0
-110
-100
-90
-80
-70
-60
dBr A
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr A
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
100
50 200 500 1k 2k 5k 10k
Hz
20 20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
dBr A
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 33. THD+N vs. Amplitude (HRM)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 34. THD+N vs. Frequency (HRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
CS4334/5/8/9
22 DS248F3
5. PIN DESCRIPTIONS
No. Pin Name I/O Pin Function and Description
1SDATA I
Serial Audio Data Input
- two’s complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel
is determined by LRCK.
2DEM/SCLKI
De-Emphasis/External Serial Clock Input
- used for de-emphasis filter control or exter-
nal serial clock input.
3LRCK I
Left/Right Clock
- determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA.
4MCLK I
Master Clock
- frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
5AOUTRO
Analog Right Channel Output
- typically 3.5 Vp-p for a full-scale input signal.
6AGND I
Analog Ground
- analog ground reference is 0V.
7VA I
Analog Power
- analog power supply is nominally +5V.
8AOUTLO
Analog Left Channel Output
- typically 3.5 Vp-p for a full-scale input signal.
SERIAL DATA INPUT SDATA AOUTL ANALOG LEFT CHANNEL OUTPUT
DE-EMPHASIS / SCLK DEM/SCLK VA ANALOG POWER
LEFT / RIGHT CLOCK LRCK AGND ANALOG GROUND
MASTER CLOCK MCLK AOUTR ANALOG RIGHT CHANNEL OUTPUT
72
63
54
81
CS4334/5/8/9
DS248F3 23
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the
rms sum of all other spectral components over the specified bandwidth (typically 10Hz to
20kHz), including distortion components. Expressed in decibels.
Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other
spectral components over the specified bandwidth. Dynamic range is a signal-to-noise
measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added
to the resulting measurement to refer the measurement to full scale. This technique ensures that
the distortion components are below the noise level and do not effect the measurement. This
measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and
the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured
for each channel at the converter's output with all zeros to the input under test and a full-scale
signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in
decibels.
Gain Error - The deviation from the nominal full scale analog output for a full scale digital
input.
Gain Drift - The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4334/5/8/9 Evaluation Board Datasheet
CS4334/5/8/9
24 DS248F3
8. ORDER INFORMATION:
9. FUNCTIONAL COMPATIBILITY
CS4330-KS
⇒
CS4339-KS
CS4331-KS
⇒
CS4334-KS
CS4333-KS
⇒
CS4338-KS
CS4330-BS
⇒
CS4339-BS/-DS
CS4331-BS
⇒
CS4334-BS/-DS
CS4333-BS
⇒
CS4338-DS
Model Temperature Package Serial Interface
CS4334-KS -10 to +70 °C 8-pin Plastic SOIC 16 to 24-bit, I2S
CS4335-KS -10 to +70 °C 8-pin Plastic SOIC 16 to 24-bit, left justified
CS4334-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free 16 to 24-bit, I2S
CS4335-KSZ -10 to +70 °C 8-pin Plastic SOIC, lead free 16 to 24-bit, left justified
CS4338-KS -10 to +70 °C 8-pin Plastic SOIC 16-bit, right justified
CS4339-KS -10 to +70 °C 8-pin Plastic SOIC 18-bit, right justified, 32 Fs Internal SCLK mode
CS4334-BS -40 to +85 °C 8-pin Plastic SOIC 16 to 24-bit, I2S
CS4339-BS -40 to +85 °C 8-pin Plastic SOIC 18-bit, right justified, 32 Fs Internal SCLK mode
CS4334-DS -40 to +85 °C 8-pin Plastic SOIC 16 to 24-bit, I2S
CS4335-DS -40 to +85 °C 8-pin Plastic SOIC 16 to 24-bit, left justified
CS4338-DS -40 to +85 °C 8-pin Plastic SOIC 16-bit, right justified
CS4339-DS -40 to +85 °C 8-pin Plastic SOIC 18-bit, right justified, 32 Fs Internal SCLK mode
Revision Date Changes
F3 July 2004 Removed CS4335-BS and CS4339-BS from the Ordering Information section.
Table 2. Revision History
CS4334/5/8/9
DS248F3 25
10. PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.19 0.25
D 0.189 0.197 4.80 5.00
E 0.150 0.157 3.80 4.00
e 0.040 0.060 1.02 1.52
H 0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
∝0° 8° 0° 8°
JEDEC # : MS-012
8L SOIC (150 MIL BODY) PACKAGE DRAWING
D
H
E
e
b
A1
A
c
L
∝
SEATING
PLANE
1
