April 2002 1/12
This is preliminary information on a new product nowin development. Details are subject tochange without notice.
Rev. 1.1
ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3TM
(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
DATA BRIEFING
■Memories
– Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E3TM(Emulat-
ed EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
■Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 80 ns (25 MHz int. clock)
■Interrupt Management
– 80, 77 or 48 I/O pins (depending on device)
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up oraddition-
al external interrupt with multi-level interrupt handler
■Timers
– 16-bit Timer with 8-bitPrescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
■Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only)
– J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
– One or two full I C multiple Master/Slave Interfaces
supporting Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces with:
– Up to 1 MBit/s communication speed
– 3 Transmit Mailboxes with priority configuration
by software
– Enhanced Filtering mechanism
– 2 prioritized FIFO receive schemes
– Time-Triggered Communication support
■DMA controller for reduced processor overhead
■10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
■Instruction Set
– Rich Instruction Set with 14 Addressing Modes
– Division-by-zero trap generation
■Development Tools
– Versatile Development Tools, including Assembler,
Linker, C-Compiler, Source Level Debugger, Real
Time Operating System (OSEK OS, CMX) and CAN
drivers
– Hardware Emulator, Flash Programming Boards
DEVICE SUMMARY
PQFP100
14x20
TQFP64
14x14
TQFP100
14x14
Features ST92F124R9 ST92F150C(R/V)1 ST92F150JV1 ST92F150JDV1 ST92F250CV2
FLASH - bytes 60K 128K 256K
RAM - bytes 2K 4K 6K 8K
E3TM- bytes 1K
Timers 2 MFT, STIM, WD 2 MFT, 0/2 EFT,
STIM, WD 2 MFT, 2 EFT, STIM, WD
Serial Int erface SCI, SPI , I C 1/2 S CI, SP I, I C 2 S CI, SP I, 2 I C
ADC 8 x 10 bits 8/16 x 10 bits 16 x 10 bits
Network Interface - CAN J1850 2 CAN, J1850 CAN
Temp. Range -40oCto85
oCor-40
oCto125
oC
Packages TQFP64 P/TQFP100 and TQFP64 PQFP100 P/TQFP100
9
2/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92F124/F150/F250 microcontroller is de-
veloped and manufactured by STMicroelectronics
using a proprietary n-well HCMOS process. Its
performance derives from the use of a flexible
256-register programming model for ultra-fast con-
text switching and real-time event response. The
intelligent on-chipperipherals offload the ST9 core
from I/O and data management processing tasks
allowing critical application tasks to get the maxi-
mum use of core resources. The new-generation
ST9 MCU devices now also support low power
consumption and low voltage operationfor power-
efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit(CPU),the RegisterFile, theInter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.
Four independent buses are controlled by the
Core: a 22-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in theon-chip peripherals with the
core.
This multiple bus architecture makes theST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bitprocessing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the
ST92F150/F124 with 48 (64-pin devices) or 77
(100-pin devices) I/O lines dedicated to digital In-
put/Output andwith 80 I/O lines bythe ST92F250.
These lines are grouped into up to ten 8-bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/data bus for interfacing to the external
memory, timer inputs and outputs, analog inputs,
external interrupts and serial or parallel I/O. Two
memory spaces are available to support this wide
range of configurations: a combined Program/
Data Memory Space and the internal Register File,
which includes the control and status registers of
the on-chip peripherals.
1.1.2 External Memory Interface
100-pin devices have a 22-bit external address
bus allowing them to address upto 4M bytes of ex-
ternal memory. 64-pin devices have an 11-bit ex-
ternal address bus for addressing up to 2K bytes.
1.1.3 On-chip Peripherals
Two 16-bit Multifunction Timers, each with an 8 bit
Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.
On 100-pin devices, two Extended Function Tim-
ers provide further timing and signal generation
capabilities.
A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.
An I2C interface (two in the ST92F250) provides
fast I2C and Access Bus support.
The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimastersystems.
A J1850 Byte Level Protocol Decoder is available
(on some devices only) for communicating with a
J1850 network.
The bxCAN (basic extended) interface supports
2.0B Active protocol. It has 3 transmit mailboxes, 2
independent receive FIFOs and 8 filters.
In addition, there isan 16channel Analog to Digital
Converter with integral sample and hold, fast con-
version time and 10-bit resolution. In the 64-pin
version only 8 input channels are available.
There is one Multiprotocol Serial Communications
Interface withan integral generator, asynchronous
and synchronous capability (fully programmable
format) and associated address/wake-up option,
plus two DMA channels.
On some devices, there is an additional asynchro-
nous Serial Communications interface.
Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
25MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.
9
3/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 1. ST92F124R9: Architectural Block Diagram
256 bytes
Register File
RAM
2 Kbytes
ST9 CORE
8/16 bits
CPU
Interrupt
Management
MEMORY BUS
RCCU
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Port1
REGISTER BUS
WATCHDOG
AS
DS
RW
WAIT
NMI
DS2
MISO
MOSI
SCK
SS
A[10:8]
A[7:0]
D[7:0]
ST. TIMER
SPI
SDA
SCL
I2C BUS
SCI M
FLASH
60 Kbytes
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
WDOUT
HW0SW1
STOUT
Fully
Prog.
I/Os
P0[7:0]
P1[2:0]
P2[7:0]
P3[7:4]
P4[7:4]
P5[7:0]
P6[5:2,0]
P7[7:0]
MF TIMER 0
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
INT[5:0]
WKUP[13:0]
MF TIMER 1
E3TM
1 Kbyte
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
ADC AVDD
AVSS
AIN[15:8]
EXTRG
VREG VOLTAGE
REGULATOR
The alternate functions (
Italic characters
) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6
and Port7.
9
4/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 2. ST92F150C: Architectural Block Diagram
256 bytes
Register File
RAM
4 Kbytes
ST9 CORE
8/16 bits
CPU
Interrupt
Management
MEMORY BUS
RCCU
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports
1,9*
REGISTER BUS
WATCHDOG
AS
DS
RW
WAIT
NMI
DS2
RW*
MISO
MOSI
SCK
SS
A[10:8]
A[21:11]*
A[7:0]
D[7:0]
ST. TIMER
SPI
SDA
SCL
I2C BUS
FLASH
128 Kbytes
WDOUT
HW0SW1
STOUT
* Not available on 64-pin version.
Fully
Prog.
I/Os
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
P7[7:0]
P8[7:0]*
P9[7:0]*
MF TIMER 0
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
INT[5:0]
INT6
*
WKUP[13:0]
WKUP[15:14]*
MF TIMER 1
E3TM
1 Kbyte
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
ADC
AVDD
AVSS
AIN[15:8]
AIN[7:0]*
EXTRG
RX0
TX0
CAN_0
VREG VOLTAGE
REGULATOR
The alternate functions (
Italic characters
) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8* and Port9*.
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
EF TIMER 0 *
EF TIMER 1 *
SCI M
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
SCI A
RDI
TDO
9
5/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 3. ST92F150J: Architectural Block Diagram
256 bytes
Register File
ST9 CORE
8/16 bit
CPU
Interrupt
Management
MEMORY BUS
RCCU
REGISTER BUS
WATCHDOG
AS
DS
RW
WAIT
NMI
DS2
RW
MISO
MOSI
SCK
SS
EF TIMER 0
ST. TIMER SPI
SCI M
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
WDOUT
HW0SW1
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
Fully Prog.
I/Os
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1]
P4[7:0]
P5[7:0]
P6[5:0]
P7[7:0]
P8[7:0]
P9[7:0]
RDI
TDO
MF TIMER 0
TINPA0
TOUTA0
TINPB0
TOUTB0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA1
TOUTA1
TINPB1
TOUTB1
INT[6:0]
WKUP[15:0]
EF TIMER 1
MF TIMER 1
SCI A
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
CK_AF
ADC AVDD
AVSS
AIN[15:0]
EXTRG
SDA
SCL
I2CBUS
VPWI
VPWO
J1850
JBLPD
A[7:0]
D[7:0]
A[21:8]
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports 1,9
RAM
4/6 Kbytes
FLASH
128 Kbytes
E3TM
1K byte
The alternate functions (
Italic characters
) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,
* Available on ST92F150JDV1 only
RX0
TX0
CAN_0 *
RX1
TX1
CAN_1 *
VREG VOLTAGE
REGULATOR
Port8 and Port9.
RDI
TDO
FLASH
128 Kbytes
9
6/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 4. ST92F250CV2: Architectural Block Diagram
256 bytes
Register File
ST9 CORE
8/16 bit
CPU
Interrupt
Management
MEMORY BUS
RCCU
REGISTER BUS
WATCHDOG
AS
DS
RW
WAIT
NMI
DS2
RW
MISO
MOSI
SCK
SS
EF TIMER 0
ST. TIMER
SPI
SCI M
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
WDOUT
HW0SW1
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
Fully Prog.
I/Os
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P4[7:0]
P5[7:0]
P6[7:0]
P7[7:0]
P8[7:0]
P9[7:0]
RDI
TDO
MF TIMER 0
TINPA0
TOUTA0
TINPB0
TOUTB0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA1
TOUTA1
TINPB1
TOUTB1
INT[6:0]
WKUP[15:0]
EF TIMER 1
MF TIMER 1
SCI A
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
CK_AF
ADC
AVDD
AVSS
AIN[15:0]
EXTRG
SDA1
SCL1
I2C BUS _1
A[7:0]
D[7:0]
A[21:8]
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports 1,9
RAM
8 Kbytes
FLASH
256 Kbytes
E3TM
1K byte
The alternate functions (
Italic characters
) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,
RX0
TX0
CAN_0
VREG VOLTAGE
REGULATOR
Port8 and Port9.
SDA0
SCL0
I2C BUS _0
1
7/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 5. ST92F124/ST92F150: Pin Configuration (Top-view TQFP64)
TX0*/WAIT/WKUP5/P5.0
RX0*/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCL0/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
HW0SW1
RESET
OSCOUT
OSCIN
VDD
VSS
P7.7/AIN15/WKUP13
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.4/AIN12/WKUP3
P7.3/AIN11
P7.2/AIN10
P7.1/AIN9
P7.0/AIN8/CK_AF
AVSS
AVDD
N.C
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
RW
TINPA0/P2.0
TINPB0/P2.1
TOUTA0/P2.2
TOUTB0/P2.3
TINPA1/P2.4
TINPB1/P2.5
TOUTA1/P2.6
TOUTB1/P2.7
VSS
VDD
VREG
VTEST
A8/P1.0
A9/P1.1
A10/P1.2
64 63626160 59585756 55545352 515049
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1718192021222324 2930313225262728
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ST92F124 /
* Not available on ST92F124 version
ST92F150
1718192021222324 2930313225262728
9
8/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 6. ST92F150: Pin Configuration (Top-view PQFP100)
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P9.2/A16
P9.1/TDO
P9.0/RDI
HW0SW1
RESET
OSCOUT
OSCIN
VDD
VSS
P7.7/AIN15/7/WKUP13
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.4/AIN12/WKUP3
P7.3/AIN11
P7.2/AIN10
P7.1/AIN9
P7.0/AIN8/CK_AF
AVSS
AVDD
P8.7/AIN7
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
VPWO*
P6.5/WKUP10/INTCLK/VPWI
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
VREG
RW
TINPA0/P2.0
TINPB0/P2.1
TOUTA0/P2.2
TOUTB0/P2.3
TINPA1/P2.4
TINPB1/P2.5
TOUTA1/P2.6
TOUTB1/P2.7
VSS
VDD
VREG
VTEST
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
**RX1/WKUP6
**TX1
1
50
30
ST92F150
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
80
51
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
49484746454443424140393837363534333231
81828384858687888990919293949596979899100
*On devices without JPBLD peripheral, this pin must not be connected.
**On devices without CAN1 peripheral, these pins must not be connected.
9
9/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 7. ST92F150: Pin Configuration (Top-view TQFP100)
*V
TEST must be kept low in standard operating mode.
**On devices without CAN1 peripheral, these pins must not be connected.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
262728 2930 3132 333435 363738 394041424344 4546 474849 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10099 98 9796 95 949392 91 908988 878685 8483 828180 79787776
ST92F150
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
VPWO
P6.5/WKUP10/INTCLK/VPWI
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P0.4/A4/D4
P1.7/A15
A20/P9.6
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
TXCLK/CLKOUT/P5.4
OCMPA1/P4.2
VDD
A21/P9.7
WDIN/SOUT/P5.3
DCD/WKUP8/P5.6
VSS
ICAPB1/OCMPB1/P4.3
SDA/P4.6
SIN/WKUP2/P5.2
RXCLK/WKUP7/P5.5
CLOCK2/P4.1
EXTCLK1/WKUP4/P4.4
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
WKUP9/RTS/P5.7
ICAPA1/P4.0
EXTRG/STOUT/P4.5
WKUP1/SCL/P4.7
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
P9.5/A19
P9.4/A18
P9.2/A16
HW0SW1
P7.7/AIN15/7/WKUP13
P7.4/AIN12/WKUP3
P9.3/A17
P9.0/RDI
RESET
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.1/AIN9
P9.1/TDO
OSCIN
VSS
P7.3/AIN11
P7.0/AIN8/CK_AF
P8.7/AIN7
OSCOUT
VDD
P7.2/AIN10
AVSS
AVDD
P8.6/AIN6
P8.5/AIN5
MOSI/P3.6
SCK/WKUP0/P3.7
RW
TOUTA0/P2.2
VSS
*VTEST
VREG
TINPB0/P2.1
TOUTB0/P2.3
VDD
VREG
A10/P1.2
TINPA0/P2.0
TINPB1/P2.5
TOUTB1/P2.7
A8/P1.0
A11/P1.3
A12/P1.4
TINPA1/P2.4
TOUTA1/P2.6
A9/P1.1
**RX1/WKUP6
**TX1
A13/P1.5
A14/P1.6
9
10/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 8. ST92F250: Pin Configuration (Top-view PQFP100)
*V
TEST must be kept low in standard operating mode.
SDA1/A17/P9.3
SCL1/A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA0/P4.6
WKUP1/SCL0/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P9.2/A16
P9.1/TDO
P9.0/RDI
HW0SW1
RESET
OSCOUT
OSCIN
VDD
VSS
P7.7/AIN15/7/WKUP13
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.4/AIN12/WKUP3
P7.3/AIN11
P7.2/AIN10
P7.1/AIN9
P7.0/AIN8/CK_AF
AVSS
AVDD
P8.7/AIN7
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
P3.0
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
VREG
RW
TINPA0/P2.0
TINPB0/P2.1
TOUTA0/P2.2
TOUTB0/P2.3
TINPA1/P2.4
TINPB1/P2.5
TOUTA1/P2.6
TOUTB1/P2.7
VSS
VDD
VREG
*VTEST
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
P6.6
P6.7
1
50
30
ST92F250
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
80
51
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
49484746454443424140393837363534333231
81828384858687888990919293
94
9596979899100
9
11/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 9. ST92F250: Pin Configuration (Top-view TQFP100)
*V
TEST must be kept low in standard operating mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627 2829 3031 323334 3536 3738 39 404142 4344 4546 4748 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10099 98 979695 949392 91 9089 8887 868584 8382 818079 787776
ST92F250
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
P3.0
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P0.4/A4/D4
P1.7/A15
A20/P9.6
TX/WAIT/WKUP5/P5.0
RX/WKUP6/WDOUT/P5.1
TXCLK/CLKOUT/P5.4
OCMPA1/P4.2
VDD
A21/P9.7
WDIN/SOUT/P5.3
DCD/WKUP8/P5.6
VSS
ICAPB1/OCMPB1/P4.3
SDA0/P4.6
SIN/WKUP2/P5.2
RXCLK/WKUP7/P5.5
CLOCK2/P4.1
EXTCLK1/WKUP4/P4.4
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
WKUP9/RTS/P5.7
ICAPA1/P4.0
EXTRG/STOUT/P4.5
WKUP1/SCL0/P4.7
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
P9.5/A19
P9.4/A18/SCL1
P9.2/A16
HW0SW1
P7.7/AIN15/7/WKUP13
P7.4/AIN12/WKUP3
P9.3/A17/SDA1
P9.0/RDI
RESET
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.1/AIN9
P9.1/TDO
OSCIN
VSS
P7.3/AIN11
P7.0/AIN8/CK_AF
P8.7/AIN7
OSCOUT
VDD
P7.2/AIN10
AVSS
AVDD
P8.6/AIN6
P8.5/AIN5
MOSI/P3.6
SCK/WKUP0/P3.7
RW
TOUTA0/P2.2
VSS
*VTEST
VREG
TINPB0/P2.1
TOUTB0/P2.3
VDD
VREG
A10/P1.2
TINPA0/P2.0
TINPB1/P2.5
TOUTB1/P2.7
A8/P1.0
A11/P1.3
A12/P1.4
TINPA1/P2.4
TOUTA1/P2.6
A9/P1.1
P6.6
P6.7
A13/P1.5
A14/P1.6
9
12/12
ST92F124/F150/F250 - GENERAL DESCRIPTION
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor forany infringement of patentsor other rights of third parties which mayresult from its use. Nolicense is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel- Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
1
