ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD DATA BRIEFING Memories - Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM) - In-Application Programming (IAP) - 224 general purpose registers (register file) available as RAM, accumulators or index pointers TQFP64 - Register-oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP modes - 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range - PLL Clock Generator (3-5 MHz crystal) - Minimum instruction time: 80 ns (25 MHz int. clock) 14x14 Interrupt Management Timers - 16-bit Timer with 8-bit Prescaler, and Watchdog Timer (activated by software or by hardware) - 16-bit Standard Timer that can be used to generate a time base independent of PLL Clock Generator - Two 16-bit independent Extended Function Timers (EFTs) with Prescaler, 2 Input Captures and two Output Compares (100-pin devices only) - Two 16-bit Multifunction Timers, with Prescaler, 2 Input Captures and two Output Compares - One or two full I C multiple Master/Slave Interfaces supporting Access Bus - One or two CAN 2.0B (150 version only) Active interfaces with: - Up to 1 MBit/s communication speed - 3 Transmit Mailboxes with priority configuration by software - Enhanced Filtering mechanism - 2 prioritized FIFO receive schemes - Time-Triggered Communication support DMA controller for reduced processor overhead 10-bit Analog to Digital Converter allowing up to 16 input channels on 100-pin devices or 8 input channels on 64-pin devices Instruction Set - Rich Instruction Set with 14 Addressing Modes - Division-by-zero trap generation Communication Interfaces - Serial Peripheral Interface (SPI) with Selectable Master/Slave mode - One Multiprotocol Serial Communications Interface with asynchronous and synchronous capabilities - One asynchronous Serial Communications Interface (on 100-pin versions only) - J1850 Byte Level Protocol Decoder (JBLPD) (on F150J versions only) 14x20 TQFP100 - 80, 77 or 48 I/O pins (depending on device) - 4 external fast interrupts + 1 NMI - Up to 16 pins programmable as wake-up or additional external interrupt with multi-level interrupt handler PQFP100 14x14 Clock, Reset and Supply Management Development Tools - Versatile Development Tools, including Assembler, Linker, C-Compiler, Source Level Debugger, Real Time Operating System (OSEK OS, CMX) and CAN drivers - Hardware Emulator, Flash Programming Boards DEVICE SUMMARY Features FLASH - bytes RAM - bytes E3 TM - bytes Timers Serial Interface ADC Network Interface Temp. Range Packages ST92F124R9 60K 2K 2 MFT, STIM, WD SCI, SPI, I C 8 x 10 bits TQFP64 ST92F150C(R/V)1 4K ST92F150JV1 ST92F150JDV1 128K 6K 1K ST92F250CV2 256K 8K 2 MFT, 0/2 EFT, 2 MFT, 2 EFT, STIM, WD STIM, WD 1/2 SCI, SPI, I C 2 SCI, SPI, 2 I C 8/16 x 10 bits 16 x 10 bits CAN J1850 2 CAN, J1850 CAN -40 oC to 85o C or -40o C to 125o C P/TQF P100 and TQFP64 PQFP100 P/TQFP100 Rev. 1.1 April 2002 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST92F124/F150/F250 microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for powerefficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt and DMA controller, and the Memory Management Unit. The MMU allows a single linear address space of up to 4 Mbytes. Four independent buses are controlled by the Core: a 22-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. The powerful I/O capabilities demanded by microcontroller applications are fulfilled by the ST92F150/F124 with 48 (64-pin devices) or 77 (100-pin devices) I/O lines dedicated to digital Input/Output and with 80 I/O lines by the ST92F250. These lines are grouped into up to ten 8-bit I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, an address/data bus for interfacing to the external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O. Two memory spaces are available to support this wide range of configurations: a combined Program/ Data Memory Space and the internal Register File, 2/12 9 which includes the control and status registers of the on-chip peripherals. 1.1.2 External Memory Interface 100-pin devices have a 22-bit external address bus allowing them to address up to 4M bytes of external memory. 64-pin devices have an 11-bit external address bus for addressing up to 2K bytes. 1.1.3 On-chip Peripherals Two 16-bit Multifunction Timers, each with an 8 bit Prescaler and 12 operating modes allow simple use for complex waveform generation and measurement, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. On 100-pin devices, two Extended Function Timers provide further timing and signal generation capabilities. A Standard Timer can be used to generate a stable time base independent from the PLL. An I2C interface (two in the ST92F250) provides fast I2C and Access Bus support. The SPI is a synchronous serial interface for Master and Slave device communication. It supports single master and multimaster systems. A J1850 Byte Level Protocol Decoder is available (on some devices only) for communicating with a J1850 network. The bxCAN (basic extended) interface supports 2.0B Active protocol. It has 3 transmit mailboxes, 2 independent receive FIFOs and 8 filters. In addition, there is an 16 channel Analog to Digital Converter with integral sample and hold, fast conversion time and 10-bit resolution. In the 64-pin version only 8 input channels are available. There is one Multiprotocol Serial Communications Interface with an integral generator, asynchronous and synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. On some devices, there is an additional asynchronous Serial Communications interface. Finally, a programmable PLL Clock Generator allows the usage of standard 3 to 5 MHz crystals to obtain a large range of internal frequencies up to 25MHz. Low power Run (SLOW), Wait For Interrupt, low power Wait For Interrupt, STOP and HALT modes are also available. ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 1. ST92F124R9: Architectural Block Diagram FLASH 60 Kbytes AS DS RW WAIT NMI DS2 INT[5:0] WKUP[13:0] RAM 2 Kbytes 256 bytes Register File MEMORY BUS E 3 TM 1 Kbyte Ext. MEM. ADDRESS DATA Port0 A[7:0] D[7:0] Ext. MEM. ADDRESS Port1 A[10:8] Fully Prog. I/Os 8/16 bits CPU Interrupt Management P0[7:0] P1[2:0] P2[7:0] P3[7:4] P4[7:4] P5[7:0] P6[5:2,0] P7[7:0] ST9 CORE STOUT TINPA0 TOUTA0 TINPB0 TOUTB0 TINPA1 TOUTA1 TINPB1 TOUTB1 RCCU I2C BUS ST. TIMER WATCHDOG MF TIMER 0 REGISTER BUS OSCIN OSCOUT RESET CLOCK2/8 INTCLK CK_AF SPI ADC MF TIMER 1 SCI M V REG VOLTAGE REGULATOR SDA SCL WDOUT HW0SW1 MISO MOSI SCK SS AVDD AVSS AIN[15:8] EXTRG TXCLK RXCLK SIN DCD SOUT CLKOUT RTS The alternate functions (Italic characters ) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6 and Port7. 3/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 2. ST92F150C: Architectural Block Diagram FLASH 128 Kbytes INT[5:0] INT6 * WKUP[13:0] WKUP[15:14]* OSCIN OSCOUT RESET CLOCK2/8 INTCLK CK_AF STOUT 256 bytes Register File A[10:8] A[21:11]* Interrupt Management ST9 CORE RCCU I2C BUS ST. TIMER WATCHDOG EF TIMER 0 * ICAPA1 OCMPA1 ICAPB1 OCMPB1 EXTCLK1 EF TIMER 1 * V REG Ext. MEM. ADDRESS Ports 1,9* 8/16 bits CPU ICAPA0 OCMPA0 ICAPB0 OCMPB0 EXTCLK0 TINPA0 TOUTA0 TINPB0 TOUTB0 TINPA1 TOUTA1 TINPB1 TOUTB1 A[7:0] D[7:0] Fully Prog. I/Os REGISTER BUS AS DS RW WAIT NMI DS2 RW* RAM 4 Kbytes MEMORY BUS E 3 TM 1 Kbyte Ext. MEM. ADDRESS DATA Port0 SPI ADC MF TIMER 0 SCI M MF TIMER 1 SCI A VOLTAGE REGULATOR CAN_0 P0[7:0] P1[7:3]* P1[2:0] P2[7:0] P3[7:4] P3[3:1]* P4[7:4] P4[3:0]* P5[7:0] P6[5:2,0] P6.1* P7[7:0] P8[7:0]* P9[7:0]* SDA SCL WDOUT HW0SW1 MISO MOSI SCK SS AVDD AVSS AIN[15:8] AIN[7:0]* EXTRG TXCLK RXCLK SIN DCD SOUT CLKOUT RTS RDI TDO RX0 TX0 * Not available on 64-pin version. The alternate functions (Italic characters ) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7, Port8* and Port9*. 4/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 3. ST92F150J: Architectural Block Diagram FLASH 128 Kbytes AS DS RW WAIT NMI DS2 RW INT[6:0] WKUP[15:0] E3 TM 1K byte RAM 4/6 Kbytes 256 bytes Register File MEMORY BUS FLASH 128 Kbytes A[7:0] D[7:0] Ext. MEM. ADDRES S Ports 1,9 A[21:8] Fully Prog. I/Os 8/16 bit CPU J1850 JBLPD Interrupt Management ST9 CORE I2C BUS RCCU WATCHDOG STOUT ST. TIMER ICAPA0 OCMPA0 ICAPB0 OCMPB0 EXTCLK0 EF TIMER 0 ICAPA1 OCMPA1 ICAPB1 OCMPB1 EXTCLK1 EF TIMER 1 TINPA0 TOUTA0 TINPB0 TOUTB0 MF TIMER 0 TINPA1 TOUTA1 TINPB1 TOUTB1 MF TIMER 1 VREG VOLTAGE REGULATOR REGISTER BUS OSCIN OSCOUT RESET CLOCK2/8 CLOCK2 INTCLK CK_AF Ext. MEM. ADDRE SS DATA Port0 SPI ADC P0[7:0] P1[7:0] P2[7:0] P3[7:1] P4[7:0] P5[7:0] P6[5:0] P7[7:0] P8[7:0] P9[7:0] VPWI VPWO SDA SCL WDOUT HW0SW1 MISO MOSI SCK SS AV DD AV SS AIN[15:0] EXTRG SCI M TXCLK RXCLK SIN DCD SOUT CLKOUT RTS SCI A RDI TDO CAN_0 * RX0 TX0 CAN_1 * RX1 TX1 * Available on ST92F150JDV1 only The alternate functions (Italic characters ) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9. 5/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 4. ST92F250CV2: Architectural Block Diagram FLASH 256 Kbytes AS DS RW WAIT NMI DS2 RW INT[6:0] WKUP[15:0] RAM 8 Kbytes 256 bytes Register File MEMORY BUS E3 TM 1K byte Ext. MEM. ADDRE SS DATA Port0 A[7:0] D[7:0] Ext. MEM. ADDRES S Ports 1,9 A[21:8] Fully Prog. I/Os 8/16 bit CPU Interrupt Management I2C BUS _0 SDA0 SCL0 I2C BUS _1 SDA1 SCL1 ST9 CORE STOUT RCCU ST. TIMER ICAPA0 OCMPA0 ICAPB0 OCMPB0 EXTCLK0 EF TIMER 0 ICAPA1 OCMPA1 ICAPB1 OCMPB1 EXTCLK1 EF TIMER 1 TINPA0 TOUTA0 TINPB0 TOUTB0 MF TIMER 0 TINPA1 TOUTA1 TINPB1 TOUTB1 VREG REGISTER BUS OSCIN OSCOUT RESET CLOCK2/8 CLOCK2 INTCLK CK_AF P0[7:0] P1[7:0] P2[7:0] P3[7:0] P4[7:0] P5[7:0] P6[7:0] P7[7:0] P8[7:0] P9[7:0] WATCHDOG SPI ADC WDOUT HW0SW1 MISO MOSI SCK SS AV DD AV SS AIN[15:0] EXTRG SCI M TXCLK RXCLK SIN DCD SOUT CLKOUT RTS SCI A RDI TDO CAN_0 RX0 TX0 MF TIMER 1 VOLTAGE REGULATOR The alternate functions (Italic characters ) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9. 6/12 1 ST92F124/F150/F250 - GENERAL DESCRIPTION HW0SW1 RESET OSCOUT OSCIN VDD VSS P7.7/AIN15/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8 /CK_AF AVSS AVDD Figure 5. ST92F124/ST92F150: Pin Configuration (Top-view TQFP64) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ST92F124 / ST92F150 N.C P6.5/WKUP10/INTCLK P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS RW TINPA0/P2.0 TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 VSS VDD VREG VTEST A8/P1.0 A9/P1.1 A10/P1.2 TX0*/WAIT/W KUP5/P5.0 RX0*/WKUP6/WDOUT/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/P5.3 TXCLK/CLKOUT/P5.4 RXCL0/WKUP7/P5.5 DCD/WKUP8/P5.6 WKUP9/RTS/P5.7 WKUP4/P4.4 EXTRG/STOUT/P4.5 SDA/P4.6 WKUP1/SCL/P4.7 SS/P3.4 MISO/P3.5 MOSI/P3.6 SCK/WKUP0/P3.7 * Not available on ST92F124 version 7/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION P9.2/A16 P9.1/TDO P9.0/RDI HW0SW1 RESET OSCOUT OSCIN V DD V SS P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8 /CK_AF AV SS AV DD P8.7/AIN7 Figure 6. ST92F150: Pin Configuration (Top-view PQFP100) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 2 79 3 78 4 77 5 76 6 7 75 74 8 9 10 73 72 71 70 69 11 12 13 14 15 16 17 18 19 68 67 66 ST92F150 20 21 22 23 24 25 26 27 65 64 63 62 61 60 59 58 57 56 55 54 28 53 29 52 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 V REG RW TINPA0/P2.0 TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 VSS VDD V REG VTEST A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 **RX1/WKUP6 **TX1 A17/P9.3 A18/P9.4 A19/P9.5 A20/P9.6 A21/P9.7 TX0/WAIT/WK UP5/P5.0 RX0/WKUP6/WDOUT/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/P5.3 TXCLK/CLKOUT/P5.4 RXCLK/WKUP7/P5.5 DCD/WKUP8/P5.6 WKUP9/RTS/P5.7 ICAPA1/P4.0 CLOCK2/P4.1 OCMPA1/P4.2 VSS VDD ICAPB1/OCMPB1/P4.3 EXTCLK1/WKUP4/P4.4 EXTRG/STOUT/P4.5 SDA/P4.6 WKUP1/SCL/P4.7 ICAPB0/P3.1 ICAPA0/OCMPA0/P3.2 OCMPB0/P3.3 EXTCLK0/SS/P3.4 MISO/P3.5 MOSI/P3.6 SCK/WKUP0/P3.7 *On devices without JPBLD peripheral, this pin must not be connected. **On devices without CAN1 peripheral, these pins must not be connected. 8/12 9 P8.6/AIN6 P8.5/AIN5 P8.4/AIN4 P8.3/AIN3 P8.2/AIN2 P8.1/AIN1/WKUP15 P8.0/AIN0/WKUP14 VPWO* P6.5/WKUP10/INTCLK/VPWI P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 V DD V SS P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 ST92F124/F150/F250 - GENERAL DESCRIPTION P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CK_AF AVSS AVDD P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 P7.7/AIN15/7/WKUP13 P9.5/A19 P9.4/A18 P9.3/A17 P9.2/A16 P9.1/TDO P9.0/RDI HW0SW1 RESET OSCOUT OSCIN VDD VSS Figure 7. ST92F150: Pin Configuration (Top-view TQFP100) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A20/P9.6 A21/P9.7 TX0/WAIT/WKUP 5/P5.0 RX0/WKUP6/WDOU T/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/ P5.3 TXCLK/CLKOUT/P5.4 RXCLK/WKUP 7/P5.5 DCD/WKU P8/P5.6 WKUP9/RTS /P5.7 ICAPA1/P4.0 CLOCK2/P4.1 OCMPA1/P4.2 VSS VDD ICAPB1/OCMPB1/P4.3 EXTC LK1/WKUP4/P4.4 EXTRG/STOUT/ P4.5 SDA/P4.6 WKUP1/SCL/P4.7 ICAPB0/P3.1 ICAPA0/OCMPA0/P3.2 OCMPB0/P3.3 EXTCLK0/SS/P3.4 MISO/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ST92F150 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P8.4/AIN4 P8.3/AIN3 P8.2/AIN2 P8.1/AIN1/WKUP15 P8.0/AIN0/WKUP14 VPWO P6.5/WKUP10/INTCLK/VPWI P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 VDD VSS P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS P1.7/A15 MOSI/P3.6 SCK/WKUP0/P3.7 VREG RW TINPA0/P2.0 TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 VSS VDD VREG *VTEST A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 **RX1/WKUP6 **TX1 A12/P1.4 A13/P1.5 A14/P1.6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 * VTEST must be kept low in standard operating mode. **On devices without CAN1 peripheral, these pins must not be connected. 9/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION P9.2/A16 P9.1/TDO P9.0/RDI HW0SW1 RESET OSCOUT OSCIN VDD VSS P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CK_AF AVSS AVDD P8.7/AIN7 Figure 8. ST92F250: Pin Configuration (Top-view PQFP100) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 2 79 3 78 4 5 77 76 75 74 6 7 8 9 10 11 73 72 12 13 14 15 16 17 ST92F250 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 VREG RW TINPA0/P2.0 TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 VSS VDD VREG *VTEST A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 P6.6 P6.7 SDA1/A17/P9.3 SCL1/A18/P9.4 A19/P9.5 A20/P9.6 A21/P9.7 TX0/WAIT/WK UP5/P5.0 RX0/WKUP6/WDOUT/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/P5.3 TXCLK/CLKOUT/P5.4 RXCLK/WKUP7/P5.5 DCD/WKUP8/P5.6 WKUP9/RTS/P5.7 ICAPA1/P4.0 CLOCK2/P4.1 OCMPA1/P4.2 VSS VDD ICAPB1/OCMPB1/P4.3 EXTCLK1/WKUP4/P4.4 EXTRG/STOUT/P4.5 SDA0/P4.6 WKUP1/SCL0/P4.7 ICAPB0/P3.1 ICAPA0/OCMPA0/P3.2 OCMPB0/P3.3 EXTCLK0/SS/P3.4 MISO/P3.5 MOSI/P3.6 SCK/WKUP0/P3.7 * VTEST must be kept low in standard operating mode. 10/12 9 P8.6/AIN6 P8.5/AIN5 P8.4/AIN4 P8.3/AIN3 P8.2/AIN2 P8.1/AIN1/WKUP15 P8.0/AIN0/WKUP14 P3.0 P6.5/WKUP10/INTCLK P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7 V DD V SS P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 ST92F124/F150/F250 - GENERAL DESCRIPTION P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CK_AF AVSS AVDD P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 P7.7/AIN15/7/WKUP13 P9.5/A19 P9.4/A18/SCL1 P9.3/A17/SDA1 P9.2/A16 P9.1/TDO P9.0/RDI HW0SW1 RESET OSCOUT OSCIN VDD VSS Figure 9. ST92F250: Pin Configuration (Top-view TQFP100) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 7877 76 A20/P9.6 A21/P9.7 TX/WAIT/ WKUP5/ P5.0 RX/WK UP6/WDOUT/ P5.1 SIN/WKUP 2/P5.2 WDIN/SOU T/P5.3 TXCLK/CLKOUT/P5.4 RXCLK/WKU P7/P5.5 DCD/WKUP8/ P5.6 WKUP9/RTS /P5.7 ICAPA 1/P4.0 CLOCK2/P4.1 OCMPA1/P4.2 VSS VDD ICAPB1/OCMPB1/P4.3 EXTCLK1/WKUP4/P4.4 EXTRG/STOUT/ P4.5 SDA0/P4.6 WKUP 1/SCL0/P4.7 ICAPB 0/P3.1 ICAPA0/OCMPA0/P3.2 OCMPB0/P3.3 EXTCLK0/SS/P3.4 MISO/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ST92F250 P8.4/AIN4 P8.3/AIN3 P8.2/AIN2 P8.1/AIN1/WKUP 15 P8.0/AIN0/WKUP 14 P3.0 P6.5/WKUP10/INTCLK P6.4/NMI P6.3/INT3/INT 5 P6.2/INT2/INT 4/DS2 P6.1/INT6/RW P6.0/INT0/INT 1/CLOCK2/8 P0.7/A7/D7 VDD VSS P0.6/A6/D6 P0.5/A5/D5 P0.4/A4/D4 P0.3/A3/D3 P0.2/A2/D2 P0.1/A1/D1 P0.0/A0/D0 AS DS P1.7/A15 A12/P1.4 A13/P1.5 A14/P1.6 P6.6 P6.7 MOSI/P3.6 SCK/WKUP0/P3.7 VREG RW TINPA0/P2.0 TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 VSS VDD VREG *VTEST A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 * VTEST must be kept low in standard operating mode. 11/12 9 ST92F124/F150/F250 - GENERAL DESCRIPTION Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2 C Patent. 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