SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMember of the Pin-Compatible
CommsDAC Product Family
D125 MSPS Update Rate
D10-Bit Resolution
DSuperior Spurious Free Dynamic Range
Performance (SFDR) to Nyquist at 40 MHz
Output: 62 dBc
D1 ns Setup/Hold Time
DDifferential Scalable Current Outputs: 2 mA
to 20 mA
DOn-Chip 1.2-V Reference
D3 V and 5 V CMOS-Compatible Digital
Interface
DStraight Binary or Twos Complement Input
DPower Dissipation: 175 mW at 5 V, Sleep
Mode: 25 mW at 5 V
DPackage: 28-Pin SOIC and TSSOP
description
The THS5651A is a 10-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data
transmission in wired and wireless communication systems. The 10-bit DAC is a member of the CommsDAC
series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin
compatible 14-, 12-, 10-, and 8-bit DACs. All devices of fer identical interface options, small outline package and
pinout. The THS5651A offers superior ac and dc performance while supporting update rates up to 125 MSPS.
The THS5651A operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW
ensures that the device is well suited for portable and low-power applications. Lowering the full-scale current
output reduces the power dissipation without significantly degrading performance. The device features a
SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power
consumption for system needs.
The THS5651A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A
current-source-array architecture combined with simultaneous switching shows excellent dynamic
performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference
provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS
logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The
THS5651A supports both a straight binary and twos complement input word format, enabling flexible interfacing
with digital signal processors.
The THS5651A provides a nominal full-scale differential output current of 20 mA and >300 kΩ output
impedance, supporting both single-ended and differential applications. The output current can be directly fed
to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An
accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down
to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB
gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied
in applications using a multiplying DAC. The output voltage compliance range is 1.25 V.
Copyright 2002, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
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9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
NC
NC
CLK
DVDD
DGND
MODE
AVDD
COMP2
IOUT1
IOUT2
AGND
COMP1
BIASJ
EXTIO
EXTLO
SLEEP
SOIC (DW) OR TSSOP (PW) PACKAGE
(TOP VIEW)
NC − No internal connection
CommsDAC is a trademark of Texas Instruments Incorporated.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The THS5651A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for
operation over the industrial temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA28-TSSOP
(PW) 28-SOIC
(DW)
−40°C to 85°C THS5651AIPW THS5651AIDW
functional block diagram
IOUT1
IOUT2
CLK
D[9:0]
EXTLO
DGND
AVDD
EXTIO
COMP2
Current
Source
Array
Output
Current
Switches
AGND
1.2 V
REF
BIASJ
−
+Control
AMP
0.1 µF
2 kΩ
IBIAS
COMP1
Logic
Control
50 Ω
1 nF
DVDD
RBIAS
SLEEP
MODE
RLOAD
RLOAD
CEXT
C1
0.1 µF 0.1 µF
50 Ω
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 20 I Analog ground return for the internal analog circuitry
AVDD 24 I Positive analog supply voltage (4.5 V to 5.5 V)
BIASJ 18 O Full-scale output current bias
CLK 28 I External clock input. Input data latched on rising edge of the clock.
COMP1 19 I Compensation and decoupling node, requires a 0.1 µF capacitor to AVDD.
COMP2 23 I Internal bias node, requires a 0.1 µF decoupling capacitor to AGND.
D[9:0] [1:10] I Data bits 0 through 9.
D9 is most significant data bit (MSB), D0 is least significant data bit (LSB).
DGND 26 I Digital ground return for the internal digital logic circuitry
DVDD 27 I Positive digital supply voltage (3 V to 5.5 V)
EXTIO 17 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal
reference output when EXTLO = AGND, requires a 0.1 µF decoupling capacitor to AGND when used as reference
output
EXTLO 16 O Internal reference ground. Connect to AVDD to disable the internal reference source
IOUT1 22 O DAC current output. Full scale when all input bits are set 1
IOUT2 21 O Complementary DAC current output. Full scale when all input bits are 0
MODE 25 I Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See
timing diagram.
NC [11:14] N No connection
SLEEP 15 I Asynchronous hardware power down input. Active High. Internal pulldown. Requires 5 µs to power down but 3 ms
to power up.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, AVDD (see Note 1) −0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD (see Note 2) −0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AGND and DGND −0.3 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, AVDD to DVDD −6.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK, SLEEP, MODE (see Note 2) −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . .
Digital input D9−D0 (see Note 2) −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . .
IOUT1, IOUT2 (see Note 1) −1 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMP1, COMP2 (see Note 1) −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . .
EXTIO, BIASJ (see Note 1) −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTLO (see Note 1) −0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current (any input) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs) −30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: THS5651AI −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Measured with respect to AGND.
2. Measured with respect to DGND.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)
dc specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 Bits
DC accuracy†
INL Integral nonlinearity
TA = −40°C to 85°C
−1 ±0.5 1 LSB
DNL Differential nonlinearity TA = −40°C to 85°C−0.5 ±0.25 0.5 LSB
Monotonicity Monotonic
Analog output
Offset error 0.02 %FSR
Gain error
Without internal reference 2.3
%FSR
Gain error With internal reference 1.3 %FSR
Full scale output current‡2 20 mA
Output compliance range AVDD = 5 V, IOUTFS = 20 mA −1 1.25 V
Output resistance 300 kΩ
Output capacitance 5 pF
Reference output
Reference voltage 1.18 1.22 1.32 V
Reference output current§100 nA
Reference input
VEXTIO Input voltage range 0.1 1.25 V
Input resistance 1 MΩ
Small signal bandwidth¶Without CCOMP1 1.3 MHz
Input capacitance 100 pF
Temperature coefficients
Offset drift 0
Gain drift
Without internal reference ±40
ppm of
FSR/ C
Gain drift With internal reference ±120
ppm of
FSR/°C
Reference voltage drift ±35
Power supply
AVDD Analog supply voltage 4.5 5 5.5 V
DVDD Digital supply voltage 3 5.5 V
IAVDD
Analog supply current 25 30 mA
IAVDD Sleep mode supply current Sleep mode 3 5 mA
IDVDD Digital supply current#5 6 mA
Power dissipation|| AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA 175 mW
AVDD
Power supply rejection ratio
±0.4
%FSR/V
DVDD Power supply rejection ratio ±0.025 %FSR/V
Operating range −40 85 °C
†Measured at IOUT1 in virtual ground configuration.
‡Nominal full-scale current IOUTFS equals 32X the IBIAS current.
§Use an external buffer amplifier with high impedance input to drive any external load.
¶Reference bandwidth is a function of external cap at COMP1 pin and signal level.
#Measured at fCLK = 50 MSPS and fOUT= 1 MHz.
|| Measured for 50 Ω RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz.
Specifications subject to change
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load
(unless otherwise noted)
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog output
fCLK
Maximum output update rate
DVDD = 4.5 V to 5.5 V 100 125
MSPS
f
CLK
Maximum output update rate
DVDD = 3 V to 3.6 V 70 100 MSPS
ts(DAC) Output settling time to 0.1%†35 ns
tpd Output propagation delay 1 ns
GE Glitch energy‡Worst case LSB transition (code 511 − code 512) 5 pV−s
tr(IOUT) Output rise time 10% to 90%†1 ns
tf(IOUT) Output fall time 90% to 10%†1 ns
Output noise
IOUTFS = 20 mA 15
pA/√HZ
Output noise IOUTFS = 2 mA 10 pA/√HZ
AC linearity§
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C −72
THD
Total harmonic distortion
fCLK = 50 MSPS, fOUT = 1 MHz, TA = −40°C to 85°C −72 −64
dBc
THD Total harmonic distortion fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25°C−70 dBc
fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25°C −70
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C 79
fCLK = 50 MSPS, fOUT= 1 MHz, TA = −40°C to 85°C 66
fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C 77
Spurious free dynamic range to
fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25°C 75
Spurious free dynamic range to
Nyquist
fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25°C 71 dBc
SFDR
Nyquist
fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25°C 58
dBc
SFDR fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25°C 69
fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25°C 61
fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25°C 62
Spurious free dynamic range
fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25°C,1 MHz span 82
Spurious free dynamic range
within a window
fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span 81 dBc
within a window
fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span 78
dBc
†Measured single ended into 50 Ω load at IOUT1.
‡Single-ended output IOUT1, 50 Ω doubly terminated load.
§Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range
from 45%/55% to 55%/45%.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)
digital specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Interface
VIH
High-level input voltage
DVDD = 5 V 3.5 5
V
VIH High-level input voltage DVDD = 3.3 V 2.1 3.3 V
VIL
Low-level input voltage
DVDD = 5 V 0 1.3
V
VIL Low-level input voltage DVDD = 3.3 V 0 0.9 V
IIH
High-level input current
MODE and SLEEP DVDD = 3 V to 5.5 V −15 15
A
IIH High-level input current All other digital pins DVDD = 3 V to 5.5 V −10 10 µA
IIL
Low-level input current
MODE and SLEEP DVDD = 3 V to 5.5 V −15 15
A
IIL Low-level input current All other digital pins DVDD = 3 V to 5.5 V −10 10 µA
CIInput capacitance 1 5 pF
Timing
tsu(D) Input setup time 1 ns
th(D) Input hold time 1 ns
tw(LPH) Input latch pulse high time 4 ns
td(D) Digital delay time 1 clk
Specifications subject to change
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
48
54
60
66
72
78
84
90
0 1020304050
Figure 1
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 0 dBFS
Fout − Output Frequency − MHz
fCLK = 5 MSPS
SFDR − Spurious Free Dynamic Range − dBc
fCLK = 70 MSPS
DVDD = 5 V
fCLK = 25 MSPS
fCLK = 100 MSPS
fCLK = 125 MSPS
fCLK = 50 MSPS
Figure 2
60
66
72
78
84
90
0.0 0.5 1.0 1.5 2.0 2.5
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 5 MSPS
Fout − Output Frequency − MHz
0 dBFS
SFDR − Spurious Free Dynamic Range − dBc
−6 dBFS
−12 dBFS
DVDD = 5 V
60
66
72
78
84
90
024681012
Figure 3
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 25 MSPS
Fout − Output Frequency − MHz
−6 dBFS
SFDR − Spurious Free Dynamic Range − dBc
−12 dBFS
0 dBFS
DVDD = 5 V
48
54
60
66
72
78
0 5 10 15 20 25
Figure 4
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 50 MSPS
Fout − Output Frequency − MHz
−6 dBFS
SFDR − Spurious Free Dynamic Range − dBc
−12 dBFS
0 dBFS
DVDD = 5 V
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
48
54
60
66
72
78
0 10203040
Figure 5
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 70 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
−12 dBFS
−6 dBFS
0 dBFS
DVDD = 5 V
Figure 6
48
54
60
66
72
78
0 1020304050
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 100 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
−12 dBFS
−6 dBFS
0 dBFS
DVDD = 5 V
48
54
60
66
72
78
0 1020304050
Figure 7
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 125 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 5 V
−12 dBFS
−6 dBFS
0 dBFS
42
48
54
60
66
72
78
84
90
0 10203040
Figure 8
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 0 dBFS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 3.3 V
fCLK = 5 MSPS
fCLK = 50 MSPS
fCLK = 25 MSPS
fCLK = 100 MSPS
fCLK = 70 MSPS
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 9
60
66
72
78
84
90
0.0 0.5 1.0 1.5 2.0
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 5 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 3.3 V
−12 dBFS
−6 dBFS
0 dBFS
54
60
66
72
78
84
0246810
Figure 10
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 25 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 3.3 V
−12 dBFS
0 dBFS
−6 dBFS
Figure 11
48
54
60
66
72
78
0 5 10 15 20 25
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 50 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 3.3 V
−12 dBFS
−6 dBFS
0 dBFS
48
54
60
66
72
78
0 10203040
Figure 12
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 70 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 3.3 V
−12 dBFS
−6 dBFS
0 dBFS
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 13
48
54
60
66
72
78
84
−27 −24 −21 −18 −15 −12 −9 −6 −3 0
SPURIOUS FREE DYNAMIC RANGE
vs
AOUT AT FOUT = FCLOCK/11
Aout − dBFS
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 5 V
4.55 MHz @
50 MSPS
9.1 MHz @
100 MSPS
2.27 MHz @ 25 MSPS
6.36 MHz @
70 MSPS
Figure 14
48
54
60
66
72
78
84
−27 −24 −21 −18 −15 −12 −9 −6 −3 0
SPURIOUS FREE DYNAMIC RANGE
vs
AOUT AT FOUT = FCLOCK/5
Aout − dBFS
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 5 V
20 MHz @ 100 MSPS
5 MHz @ 25 MSPS
10 MHz @ 50 MSPS
14 MHz @ 70 MSPS
Figure 15
48
54
60
66
72
78
84
−27 −24 −21 −18 −15 −12 −9 −6 −3 0
DUAL TONE SPURIOUS FREE DYNAMIC RANGE
vs
AOUT AT FOUT = FCLOCK/7
Aout − dBFS
SFDR − Spurious Free Dynamic Range − dBc
DVDD = 5 V
0.675/0.725 MHz @ 5 MSPS
3.38/3.63 MHz @ 25 MSPS
6.75/7.25 MHz @ 50 MSPS
9.67/10.43 MHz @
70 MSPS
13.5/14.5 MHz @ 100 MSPS
Figure 16
70
75
80
85
90
0 20406080100120
TOTAL HARMONIC DISTORTION
vs
CLOCK FREQUENCY AT FOUT = 2 MHZ
Fclock − Clock Frequency − MSPS
2nd Harmonic
THD − Total Harmonic Distortion − dBc
DVDD = 5 V
3rd Harmonic
4th Harmonic
−66
−72
−78
−84
−90
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
42
48
54
60
66
72
78
84
2 4 6 8 101214161820
SFDR − Spurious Free Dynamic Range − dBc
Fout = 10 MHz
DVDD = 5 V
IOUTFS − Full-Scale Output Current − mA
Fout = 28.6 MHz
Figure 17
SPURIOUS FREE DYNAMIC RANGE
vs
FULL-SCALE OUTPUT CURRENT AT 100 MSPS
Fout = 2.5 MHz
Fout = 40 MHz
Figure 18
42
48
54
60
66
72
78
84
0 5 10 15 20 25 30 35 40 45 50
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 100 MSPS
Fout − Output Frequency − MHz
SFDR − Spurious Free Dynamic Range − dBc
DIFF @ −6 dBFS
IOUT1 @ 0 dBFS
DVDD = 5 V
IOUT1 @ −6 dBFS
DIFF @ 0 dBFS
Figure 19
48
54
60
66
72
78
84
−40 −20 0 20 40 60 80
SPURIOUS FREE DYNAMIC RANGE
vs
TEMPERATURE AT 70 MSPS
TA − Temperature − °C
Fout = 2 MHz
SFDR − Spurious Free Dynamic Range − dBc
Fout = 10 MHz
Fout = 25 MHz
DVDD = 5 V
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 20
−0.3
−0.2
−0.1
−0.0
0.1
0 128 256 384 512 640 768 896 1024
INL − Integral Nonlinearity − LSB
Code
INTEGRAL NONLINEARITY
Figure 21
−0.2
−0.1
0.0
0.1
0.2
0 128 256 384 512 640 768 896 1024
DNL − Differential Nonlinearity − LSB
Code
DIFFERENTIAL NONLINEARITY
Figure 22
Amplitude − dBm
SINGLE-TONE OUTPUT SPECTRUM
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 5 10 15 20 25
Fout = 5 MHz at
Fclock = 50 MSPS,
DVDD = 5 V
f − Frequency − MHz
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise
noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 23
Amplitude − dBm
SINGLE-TONE OUTPUT SPECTRUM
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 1020304050
Fout = 10 MHz at
Fclock = 100 MSPS,
DVDD = 5 V
f − Frequency − MHz
Figure 24
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 1020304050
Amplitude − dBm
f − Frequency − MHz
DUAL-TONE OUTPUT SPECTRUM
Fclock = 100 MSPS
Fout1 = 13.2 MHz,
Fout2 = 14.2 MHz,
DVDD = 5 V
Figure 25
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 5 10 15 20 25
Amplitude − dBm
f − Frequency − MHz
FOUR-TONE OUTPUT SPECTRUM
Fclock = 50 MSPS
Fout1 = 6.25 MHz,
Fout2 = 6.75 MHz,
Fout3 = 7.25 MHz,
Fout4 = 7.75 MHz,
DVDD = 5 V
†AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 26
0
5
10
15
20
25
30
2 4 6 8 101214161820
SUPPLY CURRENT
vs
FULL-SCALE OUTPUT CURRENT
IOUTFS − Full-Scale Output Current − mA
I(AVDD) − Supply Current − mA
DVDD = 5 V
Figure 27
0
5
10
15
20
25
0.0 0.1 0.2 0.3 0.4 0.5
DIGITAL SUPPLY CURRENT
vs
RATIO (Fclock/Fout) AT DVDD = 5 V
Ratio − (Fclock/Fout)
100 MSPS
I(DVDD) − Supply Current − mA
70 MSPS
50 MSPS
25 MSPS
5 MSPS
Figure 28
0
2
4
6
8
10
0.0 0.1 0.2 0.3 0.4 0.5
5 MSPS
DIGITAL SUPPLY CURRENT
vs
RATIO (Fclock/Fout) AT DVDD = 3.3 V
Ratio − (Fclock/Fout)
I(DVDD) − Supply Current − mA
25 MSPS
50 MSPS
70 MSPS
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The THS5651A architecture is based on current steering, combining high update rates with low power
consumption. Th e CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed dif ferential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC’s high output impedance of >300 kΩ and fast switching result in excellent dynamic
linearity (spurious free dynamic range SFDR).
The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted
from 20 mA down to 2 mA.
data interface and timing
The THS5651A comprises separate analog and digital supplies, i.e. AVDD and DVDD. The digital supply voltage
can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5651A provides
two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary
input data word format, whereas mode 1 (mode pin connected to DVDD) sets a twos complement input
configuration.
Figure 29 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5651A provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle
will give optimum dynamic performance. Figure 30 shows a schematic of the equivalent digital inputs of the
THS5651A, valid for pins D9−D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic
thresholds of D V DD/2 ±20%. Since the THS5651A is capable of being updated up to 100 MSPS, the quality of
the clock and data input signals are important in achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum setup and hold times of the THS5651A, as well
as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that
satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the
THS5651A with reduced logic swings and a corresponding digital supply (DVDD) will reduce data feed-through.
Note that the update rate is limited to 70 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
CLK
D[9:0]
DAC
Output
(IOUT1 or
IOUT2)
tw(LPH)
td(D)
0.1%
0.1%
50%
th(D)
Valid Data
tsu(D)
tpd ts(DAC)
1/fCLK
50%
tr(IOUT)
90%
10%
50% 50% 50% 50% 50%
Figure 29. Timing Diagram
Table 1. Input Interface Modes
MODE 0 MODE 1
FUNCTION/MODE MODE PIN CONNECTED TO
DGND MODE PIN CONNECTED TO
DVDD
Input code format Binary Twos complement
External
Digital in Internal
Digital in
DVDD
Figure 30. Digital Equivalent Input
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
DAC transfer function
The THS5651A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the
binary input word has the decimal representation 1023. For mode 1, the MSB is inverted (twos complement input
format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0,
straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1 +IOUTFS *IOUT2
where IOUTFS is the full-scale output current. The output currents can be expressed as:
IOUT1 +IOUTFS CODE
1024
IOUT2 +IOUTFS (1023 *CODE)
1024
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads RLOAD or a transformer with equivalent input load resistance RLOAD. This would translate into
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
VOUT1 +IOUT1 RLOAD +CODE
1024 IOUTFS RLOAD
VOUT2 +IOUT2 RLOAD +(1023–CODE)
1024 IOUTFS RLOAD
The differential output voltage VOUTDIFF can thus be expressed as:
VOUTDIFF +VOUT1–VOUT2 +(2CODE–1023)
1024 IOUTFS RLOAD
The latter equation shows that applying the differential output will result in doubling of the signal power delivered
to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and
IOUT2, which would lead to increased signal distortion.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
reference operation
The THS5651A comprises a bandgap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor
RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current
equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as:
IOUTFS +32 IBIAS +32 VEXTIO
RBIAS
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may
hence be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing
the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal
1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak
internal control amplifier may be overridden by an externally applied amplifier with suf ficient drive for the internal
1 nF load, as shown in Figure 31. This provides the user with more flexibility and higher bandwidths, which are
specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to
AGND or left disconnected when an external control amplifier is used.
AVDD
1.2 V
REF
REF AMP
1 nF
+
−
+
−
AVDD
AGND
EXTLO
EXTIO
BIASJ
AVDD
IOUT1 or IOUT2
External
Control AMP
EXT Reference
Voltage
COMP1SLEEP
Current Source Array
REXT
Internal
Control AMP
THS4041
Figure 31. Bypassing the Internal Reference and Control Amplifier
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
analog current outputs
Figure 32 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output
capacitance of 5 pF.
Output nodes IOUT1 and IOUT2 have a negative compliance voltage of −1 V, determined by the CMOS process.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5651A device. The
positive output compliance depends on the full-scale output current IOUTFS and positive supply voltage AVDD.
The positive output compliance equals 1.25 V for AVDD = 5 V and IOUTFS = 20 mA. Exceeding the positive
compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion
performance for a single-ended or dif ferential output is achieved when the maximum full-scale signal at IOUT1
and IOUT2 does not exceed 0.5 V (e.g. when applying a 50-Ω doubly terminated load for 20 mA full-scale output
current). Ap p lications requiring the THS5651A output (i.e., OUT1 and/or OUT2) to extend its output compliance
should size RLOAD accordingly.
AVDD
Current Source Array
IOUT1 IOUT2
RLOAD
RLOAD
Current
Sources
Switches
Figure 32. Equivalent Analog Current Output
Figure 33(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 50 Ω will give a dif ferential output swing of 2 VPP when applying a 20-mA full-scale output
current. The output impedance of the THS5651A depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 33(b) should be chosen.
In this I−V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switched to IOUT2. Note that the INL/DNL specifications for the THS5651A are measured with IOUT1
maintained at virtual ground. The amplifier ’s maximum output swing and the DAC’s full-scale output current
determine the value of the feedback resistor RFB. Capacitor CFB filters the steep edges of the THS5651A current
output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp
should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be
selected if a single-ended unipolar output is desirable.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
IOUT2
IOUT1
IOUT2
IOUT1
VOUT
100 Ω
−
+
RFB
+)
−) VOUT
+)
−)
50 Ω
(a) (b)
50 Ω
CFB
THS4001
THS4011
Figure 33. Differential and Single-Ended Output Configuration
The THS5651A can be easily configured to drive a doubly terminated 50-Ω cable. Figure 34(a) shows the
single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of
25 Ω. Node IOUT2 should be connected to ground or terminated with a resistor of 25 Ω. Differential-to-single
conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as
shown in Figure 34(b). This configuration provides maximum rejection of common-mode noise sources and
even order distortion components, thereby doubling the power to the output. The center tap on the primary side
of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the
ac performance of the THS5651A is optimum and specified using this differential transformer coupled output,
limiting the voltage swing at IOUT1 and IOUT2 to ±0.5 V.
IOUT2
IOUT1
VOUT
IOUT2
IOUT1 VOUT
50 Ω
100 Ω
(a) (b)
25 Ω
50 Ω
50 Ω
50 Ω
50 Ω
1:1
Figure 34. Driving a Doubly Terminated 50 Ω Cable
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
sleep mode
The THS5651A features a power-down mode that turns off the output current and reduces the supply current
to less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode
is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the THS5651A is enabled if the input is left disconnected.
Power-up and power-down activation times depend on the value of external capacitor at node SLEEP. For a
nominal capacitor value of 0.1 µF power down takes less than 5 µs, and approximately 3 ms to power back up.
The SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 22.
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the ef fects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
offset error
Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0.
gain error
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D or SINAD)
S/N+D o r SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
output compliance range
The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the
output stage or breakdown may occur.
settling time
The time required for the output to settle within a specified error band.
glitch energy
The time integral of the analog value of the glitch transient.
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
offset drift
The change in offset error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale
range per °C.
gain drift
The change in gain error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale
range per °C.
reference voltage drift
The change in reference voltage error versus temperature from the ambient temperature (TA = 25°C) in ppm
of full-scale range per °C.
THS5651A evaluation board
An evaluation module (EVM) board for the THS5651A digital-to-analog converter is available for evaluation.
This board allows the user the flexibility to operate the THS5651A in various configurations. Possible output
configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs.
The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven
directly from various pattern generators with the onboard option to add a resistor network for proper load
termination.
See the THS56x1 Evaluation Module User’s Guide for more details (SLAU032).
#111
1
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•23
−5VA
D0 10
D1 9
D2 8
D3 7
D4 6
D5 5
D6 4
D7 3
D8 2
D9 1
CLK 28
MODE 25
DVDD 27
DGND 26
AGND
20
AVDD
24
EXTLO
16
EXTIO
17
BIASJ
18
COMP1
19
COMP2
23
IOUT1
22
IOUT2
21
SLEEP 15
NC1 11
NC2 12
NC3 13
NC4 14
U5
THS5651A
FB3
C12
0.1 µF
+
C18
4.7 µF
+5VA
J8
R24
49.9
J9
R29
49.9
DAC[2..15]
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
DAC9
DAC10
DAC11
DAC12
DAC13
DAC14
DAC15
DSP[2..15]
R4A
R10A
R10B
R10C
R10D
R10E
R10F
R10G
R4B
R10H
R11A
R11B
R11C
R11D
R11E
R11F
R11G
R11H R5G
R5F
R5E
R5H
R4E
R4C
R4D
R4F
R4G
R4H
R5A
R5B
R5C
R5D
T1
T1−1T−KK81
R25
TDB
~OE
A0
A1
R20
10 K
R18
49.9
J5
W5
DSP2
DSP3
DSP4
DVDCC
DSP5
+5VA
DSP6
W3
DSP7
DSP8
DSP9
DSP10
DSP11
DSP12
DSP13
DSP14
CLKOUT
DSP15 1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
J1
C17
0.1 µF
W4
R14
5 K
C13
0.1 µF
C16
0.1 µF
R2
0 Ω
C32
C25
CLKOUT
DSP0
DSP1
~OE
C11
0.1 µF
DVDCC
W2
DVDCC R6
10K
R3
10 K
DVDCC
DSP0
DSP1
DSP2
DSP3
DSP4
DSP5
DSP6
DSP7
DSP8
DSP9
DSP10
DSP11
DSP12
DSP13
DSP14
DSP15
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
DAC9
DAC10
DAC11
DAC12
DAC13
DAC14
DAC15
OE 19
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
12 B8
11
VCC
20
GND
10
U2
SN74LVT245B
OE 19
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
12 B8
11
VCC
20
GND
10 U1
SN74LVT245B
1
3
1
3
R23
100
J6 R12
33
R9
33
R7
33
U6A
SN74ALVC08
5
3
U4
SN74HC1G32
C5
0.1 µF
+C4
10 µFC1
1 µF
C3
0.1 µF
C2
0.01 µF
C23
0.1 µF
+
C24
10 µF
C31
1 µF
C30
0.1 µF
C29
0.01 µF
L1
L3 FB1
FB4 DVDCC
+5VA
C7
0.1 µF
C6
0.1 µF
C10
0.1 µF
C8
0.1 µF
DVDCC
MiscellaniousDigital BypassCaps
1
2
J2
D2
R16
3.0 K
D1
R1
1.5 K
W1
3
2
67
4
U9
THS3001
W6
W7
R30
750
R28
750
R26
750
R27
750
R22
10
J7 A
B
C
D
E
F
I/OSTROBE
PDAC 5
3U3
SN74AHC1G00
DVDCC
DVDCC
C9
0.1 µF+
C15
10 µF
C22
1 µF
C21
0.1 µF
C20
0.01 µF
L2 FB2 −5VA
1
2
3
J4
+5VA
W8
W9
1
2
3
U8
AD1580BRT
R15
2.94 K
R19
33
+C19
4.7 µF
C14
0.01 µF
1
2
3
4
5
6
7
8
9
10
11
12
J3
U6B
U6C
U7
LT1004D
ALTERNATECONFIGURATION
+C35
4.7 µF
C34
0.1 µF
C33
0.01 µF
+5VA
+C28
4.7 µF
C27
0.1 µF
C26
0.01 µF
−5VA
U6D
R13
R8
R17
R21
0 Ω
4.7 µH
4.7 µH
4.7 µH
13
0 Ω
0 Ω
0 Ω
Figure 35. Schematic
APPLICATION INFORMATION
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 36. Board Layout, Layer 1
Figure 37. Board Layout, Layer 2
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 38. Board Layout, Layer 3
Figure 39. Board Layout, Layer 4
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 40. Board Layout, Layer 5
Table 2. Bill of Materials
QTY REF. DES PART NUMBER DESCRIPTION MFG.
3C1, C22, C31 1206ZC105KAT2A Ceramic, 1 µF, 10 V, X7R, 10% AVX
4C18, C19, C28, C35 ECSTOJY475 6.3 V, 4.7 µF, tantalum Panasonic
3C15, C24, C4 ECSTOJY106 6.3 V, 10 µF, tantalum Panasonic
0C25, C32 Ceramic, not installed, 50 V, X7R, 10%
6C14, C2, C20, C26, C29, C33 12065C103KAT2A Ceramic, 0.01 µF, 50 V, X7R, 10% AVX
17 C10, C11, C12, C13, C16,
C17, C21, C23, C27, C3, C30,
C34, C5, C6, C7, C8, C9
12065C104KAT2A Ceramic, 0.1 µF, 50 V, X7R, 10% AVX
2D1, D2 AND/AND5GA or equivalent Green LED, 1206 size SM chip LED
4FB1, FB2, FB3, FB4 27-43-037447 Fair-Rite SM beads #27-037447 FairRite
1 J1 TSW-117-07-L-D or equivalent 34-Pin header for IDC Samtec
1 J2 KRMZ2 or equivalent 2 Terminal screw connector,
2TERM_CON Lumberg
1 J3 TSW-112-07-L-S or equivalent Single row 12-pin header Samtec
1 J4 KRMZ3 or equivalent 3 Terminal screw connector Lumberg
3J5, J6, J7 142-0701-206 or equivalent PCB Mount SMA jack, SMA_PCB_MT Johnson Components
0J8, J9 142-0701-206 or equivalent PCB Mount SMA jack, not installed Johnson Components
3L1, L2, L3 DO1608C-472 DO1608C-series, DS1608C-472 Coil Craft
1 R1 1206 1206 Chip resistor, 1.5K, 1/4 W, 1%
4R10, R11, R4, R5 CTS/CTS766-163-(R)330-G-TR 8 Element isolated resistor pack, 33 Ω
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Bill of Materials (Continued)
QTY REF. DES PART NUMBER DESCRIPTION MFG.
4R12, R19, R7, R9 1206 1206 Chip resistor, 33 Ω, 1/4 W, 1%
5R13, R17. R2, R21, R8 1206 1206 Chip resistor, 0 Ω, 1/4 W, 1%
1 R14 3214W-1-502 E or equivalent 4 mm SM Pot, 5K Bourns
1 R15 1206 1206 Chip resistor, 2.94K, 1/4 W, 1%
1 R16 1206 1206 Chip resistor, 3K, 1/4 W, 1%
3R18, R24, R29 1206 1206 Chip resistor, 49.94K, 1/4 W, 1%
3R20, R3, R6 1206 1206 Chip resistor, 10K, 1/4 W, 1%
1 R22 1206 1206 Chip resistor, 10K, 1/4 W, 1%
1 R23 1206 1206 Chip resistor, 100K, 1/4 W, 1%
1 R25 1206 1206 Chip resistor, TBD, 1/4 W, 1%
4R26, R27, R28, R30 1206 1206 Chip resistor, 750K, 1/4 W, 1%
1 T1 T1-1T-KK81 RF Transformer, T1-1T-KK81 MiniCircuits
2U1, U2 SN74LVT245BDW Octal bus transceiver, 3-state,
SN74LVT245B TI
1 U3 SN74AHCT1G00DBVR/
SN74AHC1G00DBVR Single gate NAND, SN74AHC1G00 TI
1 U4 SN74AHCT1G32DBVR/
SN74AHCC1G32DBVR Single 2 input positive or gate,
SN74AHC1G32 TI
THS5641A THS5641AIDW DAC, 3−5.5 V, 8 Bit, 100 MSPS TI
THS5651A THS5651AIDW DAC, 3−5.5 V, 10 Bit, 125 MSPS TI
THS5661A THS5661AIDW DAC, 3−5.5 V, 12 Bit, 125 MSPS TI
THS5671A THS5647AIDW DAC, 3−5.5 V, 14 Bit, 125 MSPS TI
1 SN74ALVC08 SN74ALVC08D Quad AND gate TI
1 LT1004D LT1004CD-1-2/LT1004ID-1-2 Precision 1.2 V reference TI
0NOT INSTALLED AD1580BRT Precision voltage reference, not installed
1 THS3001 THS3001CD/THS2001ID THS3001 high-speed op amp TI
4 W2 TSW-102-07-L-S or equivalent 2 position jumper_.1’’ spacing, W2 Samtec
3 W3 TSW-102-07-L-S or equivalent 3 position jumper_.1’’ spacing, W3 Samtec
2 2X3_JUMPER TSW-102-07-L-S or equivalent 6-Pin header dual row, 0.025×0.1,
2X3_JUMPER Samtec
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
4040000/E 08/01
Seating Plane
0.400 (10,15)
0.419 (10,65)
0.104 (2,65) MAX
1
0.012 (0,30)
0.004 (0,10)
A
8
16
0.020 (0,51)
0.014 (0,35)
0.291 (7,39)
0.299 (7,59)
9
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
(15,24)
(15,49)
PINS **
0.010 (0,25) NOM
A MAX
DIM
A MIN
Gage Plane
20
0.500
(12,70)
(12,95)
0.510
(10,16)
(10,41)
0.400
0.410
16
0.600
24
0.610
(17,78)
28
0.700
(18,03)
0.710
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
(11,51)
(11,73)
0.453
0.462
18
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°−ā8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS5651AIDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIDWR ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIPW ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIPWR ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS5651AIPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
THS5651AIDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
THS5651AIPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS5651AIDWR SOIC DW 28 1000 346.0 346.0 49.0
THS5651AIPWR TSSOP PW 28 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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