SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 D Member of the Pin-Compatible D D D D D D D D D D CommsDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Superior Spurious Free Dynamic Range Performance (SFDR) to Nyquist at 40 MHz Output: 62 dBc 1 ns Setup/Hold Time Differential Scalable Current Outputs: 2 mA to 20 mA On-Chip 1.2-V Reference 3 V and 5 V CMOS-Compatible Digital Interface Straight Binary or Twos Complement Input Power Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V Package: 28-Pin SOIC and TSSOP SOIC (DW) OR TSSOP (PW) PACKAGE (TOP VIEW) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLK DVDD DGND MODE AVDD COMP2 IOUT1 IOUT2 AGND COMP1 BIASJ EXTIO EXTLO SLEEP NC - No internal connection description The THS5651A is a 10-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data transmission in wired and wireless communication systems. The 10-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package and pinout. The THS5651A offers superior ac and dc performance while supporting update rates up to 125 MSPS. The THS5651A operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW ensures that the device is well suited for portable and low-power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power consumption for system needs. The THS5651A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5651A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors. The THS5651A provides a nominal full-scale differential output current of 20 mA and >300 k output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC. The output voltage compliance range is 1.25 V. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CommsDAC is a trademark of Texas Instruments Incorporated. Copyright 2002, Texas Instruments Incorporated !"# $%!!&# " '%()$"# *"#&+ !*%$# $! # '&$$"# '&! #,& #&! &-" #!%&# #"*"!* ."!!"#/+ !*%$# '!$&0 *& # &$&"!)/ $)%*& #&#0 ")) '"!"&#&!+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 description (continued) The THS5651A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of -40C to 85C. AVAILABLE OPTIONS PACKAGE TA 28-TSSOP (PW) -40C to 85C 28-SOIC (DW) THS5651AIPW THS5651AIDW functional block diagram AVDD C1 SLEEP EXTLO COMP1 0.1 F COMP2 0.1 F 1.2 V REF IOUT1 1 nF EXTIO - CEXT BIASJ 0.1 F + I BIAS 2 k Control AMP Current Source Array 50 Output Current Switches IOUT2 RBIAS DVDD 50 Logic D[9:0] Control MODE CLK DGND 2 RLOAD AGND POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 RLOAD SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 Terminal Functions TERMINAL NAME NO. AGND 20 AVDD BIASJ I/O DESCRIPTION I Analog ground return for the internal analog circuitry 24 I Positive analog supply voltage (4.5 V to 5.5 V) 18 O Full-scale output current bias CLK 28 I External clock input. Input data latched on rising edge of the clock. COMP1 19 I Compensation and decoupling node, requires a 0.1 F capacitor to AVDD. COMP2 23 I Internal bias node, requires a 0.1 F decoupling capacitor to AGND. D[9:0] [1:10] I Data bits 0 through 9. D9 is most significant data bit (MSB), D0 is least significant data bit (LSB). DGND 26 I Digital ground return for the internal digital logic circuitry DVDD 27 I Positive digital supply voltage (3 V to 5.5 V) EXTIO 17 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1 F decoupling capacitor to AGND when used as reference output EXTLO 16 O Internal reference ground. Connect to AVDD to disable the internal reference source IOUT1 22 O DAC current output. Full scale when all input bits are set 1 IOUT2 21 O Complementary DAC current output. Full scale when all input bits are 0 MODE 25 I Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See timing diagram. [11:14] N No connection 15 I Asynchronous hardware power down input. Active High. Internal pulldown. Requires 5 s to power down but 3 ms to power up. NC SLEEP absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 0.5 V Supply voltage range, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6.5 V to 6.5 V CLK, SLEEP, MODE (see Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V Digital input D9-D0 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V IOUT1, IOUT2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to AVDD + 0.3 V COMP1, COMP2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V EXTIO, BIASJ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V EXTLO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 0.3 V Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Operating free-air temperature range, TA: THS5651AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Measured with respect to AGND. 2. Measured with respect to DGND. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted) dc specifications PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 10 UNIT Bits DC accuracy INL Integral nonlinearity DNL Differential nonlinearity TA = -40C to 85C -1 0.5 1 LSB -0.5 0.25 0.5 LSB Monotonicity Monotonic Analog output Offset error Gain error 0.02 Without internal reference 2.3 With internal reference 1.3 Full scale output current Output compliance range 2 AVDD = 5 V, IOUTFS = 20 mA Output capacitance %FSR 20 -1 Output resistance %FSR 1.25 mA V 300 k 5 pF Reference output Reference voltage 1.18 Reference output current 1.22 1.32 100 V nA Reference input VEXTIO Input voltage range 0.1 Input resistance Small signal bandwidth Without CCOMP1 Input capacitance 1.25 V 1 M 1.3 MHz 100 pF Temperature coefficients Offset drift 0 40 Without internal reference Gain drift ppm of FSR/ FSR/C C 120 With internal reference 35 Reference voltage drift Power supply AVDD DVDD Analog supply voltage 4.5 Digital supply voltage Analog supply current IAVDD IDVDD AVDD DVDD Sleep mode supply current Digital supply current# Sleep mode Power dissipation|| AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA 5.5 V 5.5 V 25 30 mA 3 5 mA 5 6 175 %FSR/V 0.025 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 -40 mA mW 0.4 Power supply rejection ratio Operating range Measured at IOUT1 in virtual ground configuration. Nominal full-scale current IOUTFS equals 32X the IBIAS current. Use an external buffer amplifier with high impedance input to drive any external load. Reference bandwidth is a function of external cap at COMP1 pin and signal level. # Measured at fCLK = 50 MSPS and fOUT= 1 MHz. || Measured for 50 RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz. Specifications subject to change 4 5 3 85 C SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load (unless otherwise noted) ac specifications PARAMETER TEST CONDITIONS MIN TYP 100 125 70 100 MAX UNIT Analog output fCLK Maximum output update rate ts(DAC) tpd Output settling time to 0.1% GE Output propagation delay Glitch energy tr(IOUT) tf(IOUT) Output rise time 10% to 90% Output fall time 90% to 10% Output noise DVDD = 4.5 V to 5.5 V DVDD = 3 V to 3.6 V Worst case LSB transition (code 511 - code 512) IOUTFS = 20 mA IOUTFS = 2 mA MSPS 35 ns 1 ns 5 pV-s 1 ns 1 ns 15 pA/HZ 10 AC linearity THD Total harmonic distortion fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25C fCLK = 50 MSPS, fOUT = 1 MHz, TA = -40C to 85C -72 fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25C fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25C -70 fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25C fCLK = 50 MSPS, fOUT= 1 MHz, TA = -40C to 85C Spurious free dynamic range to Nyquist SFDR Spurious free dynamic range within a window -72 -64 dBc -70 79 66 fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25C fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25C 77 fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25C fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25C 71 fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25C fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25C 69 fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25C fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25C,1 MHz span 62 fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span 81 75 dBc 58 61 82 dBc 78 Measured single ended into 50 load at IOUT1. Single-ended output IOUT1, 50 doubly terminated load. Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range from 45%/55% to 55%/45%. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP DVDD = 5 V 3.5 5 DVDD = 3.3 V 2.1 3.3 MAX UNIT Interface VIH High-level input voltage VIL Low-level input voltage IIH High-level input current IIL Low-level input current CI V DVDD = 5 V 0 1.3 DVDD = 3.3 V 0 0.9 V MODE and SLEEP DVDD = 3 V to 5.5 V -15 15 All other digital pins DVDD = 3 V to 5.5 V -10 10 MODE and SLEEP DVDD = 3 V to 5.5 V -15 15 All other digital pins DVDD = 3 V to 5.5 V -10 10 Input capacitance 1 5 tsu(D) th(D) Input setup time 1 ns Input hold time 1 ns tw(LPH) td(D) Input latch pulse high time 4 A A A A pF Timing Digital delay time Specifications subject to change 6 ns 1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 clk SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 0 dBFS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 5 MSPS 90 DVDD = 5 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 90 84 fCLK = 5 MSPS 78 fCLK = 50 MSPS 72 fCLK = 100 MSPS 66 fCLK = 70 MSPS 60 fCLK = 125 MSPS fCLK = 25 MSPS 54 48 0 10 20 30 40 DVDD = 5 V 84 0 dBFS 78 -6 dBFS 72 -12 dBFS 66 60 0.0 50 0.5 Fout - Output Frequency - MHz 1.5 2.0 2.5 Fout - Output Frequency - MHz Figure 1 Figure 2 SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 25 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 50 MSPS 90 78 DVDD = 5 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 1.0 84 0 dBFS 78 -6 dBFS 72 66 -12 dBFS 60 0 2 4 6 8 10 12 DVDD = 5 V -6 dBFS 72 -12 dBFS 66 60 0 dBFS 54 48 0 Fout - Output Frequency - MHz 5 10 15 20 25 Fout - Output Frequency - MHz Figure 3 Figure 4 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 70 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 100 MSPS 78 SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 78 DVDD = 5 V 72 66 -6 dBFS -12 dBFS 60 0 dBFS 54 48 0 10 20 30 DVDD = 5 V -6 dBFS 72 -12 dBFS 66 60 0 dBFS 54 48 40 0 10 Fout - Output Frequency - MHz Figure 5 30 40 SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 0 dBFS 90 SFDR - Spurious Free Dynamic Range - dBc 78 DVDD = 5 V 72 66 -6 dBFS -12 dBFS 60 0 dBFS 54 DVDD = 3.3 V fCLK = 5 MSPS 84 78 fCLK = 50 MSPS 72 66 fCLK = 70 MSPS 60 54 fCLK = 25 MSPS 48 fCLK = 100 MSPS 42 48 0 10 20 30 40 50 0 10 20 30 Fout - Output Frequency - MHz Fout - Output Frequency - MHz Figure 7 Figure 8 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) 8 50 Figure 6 SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 125 MSPS SFDR - Spurious Free Dynamic Range - dBc 20 Fout - Output Frequency - MHz POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 40 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 5 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 25 MSPS 84 DVDD = 3.3 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 90 84 0 dBFS 78 -6 dBFS 72 -12 dBFS 66 60 0.0 0.5 1.0 1.5 DVDD = 3.3 V 78 -6 dBFS 72 66 -12 dBFS 0 dBFS 60 54 2.0 0 2 Fout - Output Frequency - MHz 4 8 10 Fout - Output Frequency - MHz Figure 9 Figure 10 SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 70 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 50 MSPS 78 78 DVDD = 3.3 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 6 -6 dBFS 72 -12 dBFS 66 60 0 dBFS 54 DVDD = 3.3 V 72 -6 dBFS 66 -12 dBFS 60 0 dBFS 54 48 48 0 5 10 15 20 25 0 10 20 30 40 Fout - Output Frequency - MHz Fout - Output Frequency - MHz Figure 11 Figure 12 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/11 SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/5 84 DVDD = 5 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 84 78 2.27 MHz @ 25 MSPS 72 9.1 MHz @ 100 MSPS 66 60 54 6.36 MHz @ 70 MSPS 4.55 MHz @ 50 MSPS 48 -27 -24 -21 -18 -15 -12 -9 -6 -3 DVDD = 5 V 5 MHz @ 25 MSPS 78 14 MHz @ 70 MSPS 72 66 60 10 MHz @ 50 MSPS 20 MHz @ 100 MSPS 54 48 -27 -24 -21 -18 -15 -12 0 Aout - dBFS -3 TOTAL HARMONIC DISTORTION vs CLOCK FREQUENCY AT FOUT = 2 MHZ 84 90 -66 DVDD = 5 V THD - Total Harmonic Distortion - dBc DVDD = 5 V 0.675/0.725 MHz @ 5 MSPS 3.38/3.63 MHz @ 25 MSPS 72 6.75/7.25 MHz @ 50 MSPS 66 60 9.67/10.43 MHz @ 70 MSPS 54 13.5/14.5 MHz @ 100 MSPS 48 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 85 -72 4th Harmonic 3rd Harmonic 80 -78 2nd Harmonic 75 -84 70 -90 0 20 Aout - dBFS 40 60 80 100 Fclock - Clock Frequency - MSPS Figure 15 Figure 16 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) 10 0 Figure 14 DUAL TONE SPURIOUS FREE DYNAMIC RANGE vs AOUT AT FOUT = FCLOCK/7 SFDR - Spurious Free Dynamic Range - dBc -6 Aout - dBFS Figure 13 78 -9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 120 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs FULL-SCALE OUTPUT CURRENT AT 100 MSPS SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY AT 100 MSPS 84 DVDD = 5 V SFDR - Spurious Free Dynamic Range - dBc SFDR - Spurious Free Dynamic Range - dBc 84 Fout = 2.5 MHz 78 72 Fout = 10 MHz Fout = 40 MHz 66 60 Fout = 28.6 MHz 54 48 DVDD = 5 V DIFF @ -6 dBFS 78 72 DIFF @ 0 dBFS 66 60 54 IOUT1 @ 0 dBFS IOUT1 @ -6 dBFS 48 42 42 2 4 0 6 8 10 12 14 16 18 20 IOUTFS - Full-Scale Output Current - mA 5 10 15 20 25 30 35 40 45 50 Fout - Output Frequency - MHz Figure 17 Figure 18 SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE AT 70 MSPS SFDR - Spurious Free Dynamic Range - dBc 84 DVDD = 5 V 78 Fout = 2 MHz 72 66 Fout = 10 MHz 60 54 48 -40 Fout = 25 MHz -20 0 20 40 60 80 TA - Temperature - C Figure 19 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY 0.1 -0.0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 768 896 1024 Code DNL - Differential Nonlinearity - LSB Figure 20 DIFFERENTIAL NONLINEARITY 0.2 0.1 0.0 -0.1 -0.2 0 128 256 384 512 640 Code Figure 21 SINGLE-TONE OUTPUT SPECTRUM 0 Amplitude - dBm -10 Fout = 5 MHz at Fclock = 50 MSPS, DVDD = 5 V -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 f - Frequency - MHz Figure 22 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SINGLE-TONE OUTPUT SPECTRUM 0 Amplitude - dBm -10 Fout = 10 MHz at Fclock = 100 MSPS, DVDD = 5 V -20 -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 f - Frequency - MHz Figure 23 DUAL-TONE OUTPUT SPECTRUM 0 Fclock = 100 MSPS Fout1 = 13.2 MHz, Fout2 = 14.2 MHz, DVDD = 5 V -10 Amplitude - dBm -20 -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 f - Frequency - MHz Figure 24 FOUR-TONE OUTPUT SPECTRUM 0 Fclock = 50 MSPS Fout1 = 6.25 MHz, Fout2 = 6.75 MHz, Fout3 = 7.25 MHz, Fout4 = 7.75 MHz, DVDD = 5 V -10 Amplitude - dBm -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 f - Frequency - MHz Figure 25 AVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated load, TA = 25C (unless otherwise noted.) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FULL-SCALE OUTPUT CURRENT DIGITAL SUPPLY CURRENT vs RATIO (Fclock/Fout) AT DVDD = 5 V 30 25 DVDD = 5 V 100 MSPS 20 I(DVDD) - Supply Current - mA I(AVDD) - Supply Current - mA 25 20 15 10 5 70 MSPS 15 50 MSPS 10 25 MSPS 5 0 2 4 6 8 10 12 14 16 18 5 MSPS 0 0.0 20 0.1 IOUTFS - Full-Scale Output Current - mA 0.2 Ratio - (Fclock/Fout) Figure 27 Figure 26 DIGITAL SUPPLY CURRENT vs RATIO (Fclock/Fout) AT DVDD = 3.3 V I(DVDD) - Supply Current - mA 10 8 70 MSPS 6 50 MSPS 4 25 MSPS 2 5 MSPS 0 0.0 0.1 0.2 0.3 0.4 Ratio - (Fclock/Fout) Figure 28 14 0.3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 0.5 0.4 0.5 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION The THS5651A architecture is based on current steering, combining high update rates with low power consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc offsets, even order distortion components, and increase signal output power by a factor of two. Major advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic performance. The DAC's high output impedance of >300 k and fast switching result in excellent dynamic linearity (spurious free dynamic range SFDR). The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted from 20 mA down to 2 mA. data interface and timing The THS5651A comprises separate analog and digital supplies, i.e. AVDD and DVDD. The digital supply voltage can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5651A provides two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format, whereas mode 1 (mode pin connected to DVDD) sets a twos complement input configuration. Figure 29 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge of the input clock. The THS5651A provides for minimum setup and hold times (> 1 ns), allowing for noncritical external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle will give optimum dynamic performance. Figure 30 shows a schematic of the equivalent digital inputs of the THS5651A, valid for pins D9-D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic thresholds of DVDD/2 20%. Since the THS5651A is capable of being updated up to 100 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the THS5651A, as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the THS5651A with reduced logic swings and a corresponding digital supply (DVDD) will reduce data feed-through. Note that the update rate is limited to 70 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION D[9:0] Valid Data ts(DAC) tpd 0.1% DAC 90% 50% Output 10% (IOUT1 or IOUT2) 0.1% tr(IOUT) th(D) tsu(D) td(D) 1/fCLK CLK 50% 50% 50% 50% 50% 50% tw(LPH) Figure 29. Timing Diagram Table 1. Input Interface Modes MODE 0 MODE 1 FUNCTION/MODE MODE PIN CONNECTED TO DGND MODE PIN CONNECTED TO DVDD Input code format Binary Twos complement DVDD External Digital in Internal Digital in Figure 30. Digital Equivalent Input 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION DAC transfer function The THS5651A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the binary input word has the decimal representation 1023. For mode 1, the MSB is inverted (twos complement input format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as: IOUT1 + IOUT FS * IOUT2 where IOUTFS is the full-scale output current. The output currents can be expressed as: IOUT1 + IOUT FS CODE 1024 IOUT2 + IOUT FS (1023 * CODE) 1024 where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive resistor loads RLOAD or a transformer with equivalent input load resistance RLOAD. This would translate into single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of: VOUT1 + IOUT1 R LOAD + CODE 1024 VOUT2 + IOUT2 R LOAD + IOUT FS (1023-CODE) 1024 R LOAD IOUT FS R LOAD The differential output voltage VOUTDIFF can thus be expressed as: VOUT DIFF + VOUT1-VOUT2 + (2CODE-1023) 1024 IOUT FS R LOAD The latter equation shows that applying the differential output will result in doubling of the signal power delivered to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal distortion. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION reference operation The THS5651A comprises a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as: IOUT FS + 32 I BIAS + 32 V EXTIO R BIAS where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor CEXT of 0.1 F should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence be omitted. Terminal EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal 1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal 1 nF load, as shown in Figure 31. This provides the user with more flexibility and higher bandwidths, which are specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to AGND or left disconnected when an external control amplifier is used. EXT Reference Voltage - External Control AMP THS4041 + AGND AVDD SLEEP AVDD EXTLO EXTIO BIASJ 1.2 V REF COMP1 1 nF AVDD Current Source Array - REF AMP + Internal Control AMP R EXT IOUT1 or IOUT2 Figure 31. Bypassing the Internal Reference and Control Amplifier 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION analog current outputs Figure 32 shows a simplified schematic of the current source array output with corresponding switches. Differential PMOS switches direct the current of each individual PMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches, and is typically >300 k in parallel with an output capacitance of 5 pF. Output nodes IOUT1 and IOUT2 have a negative compliance voltage of -1 V, determined by the CMOS process. Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5651A device. The positive output compliance depends on the full-scale output current IOUTFS and positive supply voltage AVDD. The positive output compliance equals 1.25 V for AVDD = 5 V and IOUTFS = 20 mA. Exceeding the positive compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V (e.g. when applying a 50- doubly terminated load for 20 mA full-scale output current). Applications requiring the THS5651A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size RLOAD accordingly. AVDD Current Sources Switches IOUT1 IOUT2 RLOAD Current Source Array RLOAD Figure 32. Equivalent Analog Current Output Figure 33(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 50 will give a differential output swing of 2 VPP when applying a 20-mA full-scale output current. The output impedance of the THS5651A depends slightly on the output voltage at nodes IOUT1 and IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 33(b) should be chosen. In this I-V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The complementary output should be connected to ground to provide a dc current path for the current sources switched to IOUT2. Note that the INL/DNL specifications for the THS5651A are measured with IOUT1 maintained at virtual ground. The amplifier's maximum output swing and the DAC's full-scale output current determine the value of the feedback resistor RFB. Capacitor CFB filters the steep edges of the THS5651A current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a single-ended unipolar output is desirable. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION CFB RFB 50 IOUT1 100 - IOUT1 +) +) VOUT + VOUT -) IOUT2 IOUT2 THS4001 THS4011 50 (a) -) (b) Figure 33. Differential and Single-Ended Output Configuration The THS5651A can be easily configured to drive a doubly terminated 50- cable. Figure 34(a) shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of 25 . Node IOUT2 should be connected to ground or terminated with a resistor of 25 . Differential-to-single conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as shown in Figure 34(b). This configuration provides maximum rejection of common-mode noise sources and even order distortion components, thereby doubling the power to the output. The center tap on the primary side of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the ac performance of the THS5651A is optimum and specified using this differential transformer coupled output, limiting the voltage swing at IOUT1 and IOUT2 to 0.5 V. 50 50 1:1 VOUT VOUT IOUT1 IOUT1 100 50 50 IOUT2 IOUT2 25 50 (a) (b) Figure 34. Driving a Doubly Terminated 50 Cable 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION sleep mode The THS5651A features a power-down mode that turns off the output current and reduces the supply current to less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal pulldown circuit at node SLEEP ensures that the THS5651A is enabled if the input is left disconnected. Power-up and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal capacitor value of 0.1 F power down takes less than 5 s, and approximately 3 ms to power back up. The SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 22. definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. offset error Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0. gain error Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D or SINAD) S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. output compliance range The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the output stage or breakdown may occur. settling time The time required for the output to settle within a specified error band. glitch energy The time integral of the analog value of the glitch transient. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 offset drift The change in offset error versus temperature from the ambient temperature (TA = 25C) in ppm of full-scale range per C. gain drift The change in gain error versus temperature from the ambient temperature (TA = 25C) in ppm of full-scale range per C. reference voltage drift The change in reference voltage error versus temperature from the ambient temperature (TA = 25C) in ppm of full-scale range per C. THS5651A evaluation board An evaluation module (EVM) board for the THS5651A digital-to-analog converter is available for evaluation. This board allows the user the flexibility to operate the THS5651A in various configurations. Possible output configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs. The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination. See the THS56x1 Evaluation Module User's Guide for more details (SLAU032). 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 J6 J4 C34 0.1 F 4.7 F U9 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 2 1 R25 TDB 0.01 F T1 4.7 F C28 2 3 L2 L3 3 1 R24 49.9 C9 0.1 F C23 0.1 F R23 100 0.1 F 0.01 F C26 -5VA W8 C25 C27 750 R28 750 R30 W9 T1-1T-KK81 + 750 THS3001 4 -5VA R26 6 C33 +5VA 10 R22 + C35 J7 +5VA 750 R27 J8 D E F A B C FB2 + 10 F C15 + C32 C24 10 F 4.7 H R16 3.0 K D2 4.7 H FB4 W7 W6 J9 1 F C22 1 F C31 R29 49.9 0.01 F 0.01 F C20 -5VA 0.1 F C21 R19 C18 4.7 F + J2 W4 C14 0.01 F 2 1 R15 2.94 K C12 0.1 F FB3 +5VA 33 + C19 U7 4.7 F LT1004D C29 +5VA 0.1 F C30 1 +5VA 3 W3 20 23 19 24 R14 5K 18 2 1 10 F 26 27 25 15 28 C3 C7 C6 C10 0.1 F 0.1 F 0.1 F 0.1 F C8 W5 0.01 F C2 DVDCC 1 F 0.1 F C1 C11 0.1 F DVDCC R20 10 K DVDCC DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 DVDCC MiscellaniousDigital Bypass Caps C5 0.1 F FB1 + C4 DGND DVDD MODE SLEEP CLK NC4 NC3 NC2 NC1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 35. Schematic R1 1.5 K D1 4.7 H L1 U8 AD1580BRT 3 U5 THS5651A AGND COMP2 COMP1 AVDD BIASJ EXTIO EXTLO IOUT2 IOUT1 ALTERNATECONFIGURATION C13 0.1 F C16 0.1 F C17 0.1 F 17 16 21 22 SN74ALVC08 U6A 11 12 13 14 15 16 17 18 R11A R11B R11C R11D R11E R11F R11G R11H U6D B8 B7 B6 B5 B4 B3 B2 B1 A8 A7 A6 A5 A4 A3 A2 A1 9 8 7 6 5 4 3 2 B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 DIR W2 3 R18 49.9 3 1 W1 R6 10 K R3 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 J5 CLKOUT PDAC CLKOUT 3 5 0 0 R8 0 R13 0 R17 R21 U3 SN74AHC1G00 A0 A1 I/OSTROBE DVDCC DSP[2..15] R5A R5B R5C R5D R5E R5F R5G R5H ~OE 10K R4H DSP8 R4G DSP9 R4F DSP10 R4E DSP11 R4D DSP12 R4C DSP13 R4B DSP14 R4A DSP15 DVDCC DVDCC U4 SN74HC1G32 5 2 3 4 5 6 7 8 9 1 19 SN74LVT245B 10 GND 18 17 16 15 14 13 12 11 U2 20 VCC OE 1 DIR 20 VCC OE 19 SN74LVT245B DVDCC R10H R10G R10F R10E R10D R10C R10B R10A ~OE DAC[2..15] DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 U1 10 GND U6C U6B 33 R7 33 R9 33 R12 0 R2 DSP15 DSP14 DSP13 DSP12 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 J3 12 11 10 9 8 7 6 5 4 3 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 # 1 1 1 1 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION 23 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 36. Board Layout, Layer 1 Figure 37. Board Layout, Layer 2 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 38. Board Layout, Layer 3 Figure 39. Board Layout, Layer 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION Figure 40. Board Layout, Layer 5 Table 2. Bill of Materials QTY 26 REF. DES PART NUMBER DESCRIPTION MFG. 3 C1, C22, C31 1206ZC105KAT2A Ceramic, 1 F, 10 V, X7R, 10% AVX 4 C18, C19, C28, C35 ECSTOJY475 6.3 V, 4.7 F, tantalum Panasonic 3 C15, C24, C4 ECSTOJY106 6.3 V, 10 F, tantalum Panasonic 0 C25, C32 6 C14, C2, C20, C26, C29, C33 12065C103KAT2A Ceramic, 0.01 F, 50 V, X7R, 10% AVX 17 C10, C11, C12, C13, C16, C17, C21, C23, C27, C3, C30, C34, C5, C6, C7, C8, C9 12065C104KAT2A Ceramic, 0.1 F, 50 V, X7R, 10% AVX 2 D1, D2 AND/AND5GA or equivalent Green LED, 1206 size SM chip LED 4 FB1, FB2, FB3, FB4 27-43-037447 Fair-Rite SM beads #27-037447 FairRite 1 J1 TSW-117-07-L-D or equivalent 34-Pin header for IDC Samtec 1 J2 KRMZ2 or equivalent 2 Terminal screw connector, 2TERM_CON Lumberg 1 J3 TSW-112-07-L-S or equivalent Single row 12-pin header Samtec 1 J4 KRMZ3 or equivalent 3 Terminal screw connector Lumberg 3 J5, J6, J7 142-0701-206 or equivalent PCB Mount SMA jack, SMA_PCB_MT Johnson Components 0 J8, J9 142-0701-206 or equivalent PCB Mount SMA jack, not installed Johnson Components 3 L1, L2, L3 DO1608C-472 DO1608C-series, DS1608C-472 Coil Craft 1 R1 1206 1206 Chip resistor, 1.5K, 1/4 W, 1% 4 R10, R11, R4, R5 CTS/CTS766-163-(R)330-G-TR 8 Element isolated resistor pack, 33 Ceramic, not installed, 50 V, X7R, 10% POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 APPLICATION INFORMATION Table 2. Bill of Materials (Continued) QTY REF. DES PART NUMBER DESCRIPTION MFG. 4 R12, R19, R7, R9 1206 1206 Chip resistor, 33 , 1/4 W, 1% 5 R13, R17. R2, R21, R8 1206 1206 Chip resistor, 0 , 1/4 W, 1% 1 R14 3214W-1-502 E or equivalent 4 mm SM Pot, 5K 1 R15 1206 1206 Chip resistor, 2.94K, 1/4 W, 1% 1 R16 1206 1206 Chip resistor, 3K, 1/4 W, 1% 3 R18, R24, R29 1206 1206 Chip resistor, 49.94K, 1/4 W, 1% 3 R20, R3, R6 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R22 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R23 1206 1206 Chip resistor, 100K, 1/4 W, 1% 1 R25 1206 1206 Chip resistor, TBD, 1/4 W, 1% 4 R26, R27, R28, R30 1206 1206 Chip resistor, 750K, 1/4 W, 1% 1 T1 T1-1T-KK81 RF Transformer, T1-1T-KK81 MiniCircuits 2 U1, U2 SN74LVT245BDW Octal bus transceiver, 3-state, SN74LVT245B TI 1 U3 SN74AHCT1G00DBVR/ SN74AHC1G00DBVR Single gate NAND, SN74AHC1G00 TI 1 U4 SN74AHCT1G32DBVR/ SN74AHCC1G32DBVR Single 2 input positive or gate, SN74AHC1G32 TI THS5641A THS5641AIDW DAC, 3-5.5 V, 8 Bit, 100 MSPS TI THS5651A THS5651AIDW DAC, 3-5.5 V, 10 Bit, 125 MSPS TI THS5661A THS5661AIDW DAC, 3-5.5 V, 12 Bit, 125 MSPS TI Bourns THS5671A THS5647AIDW DAC, 3-5.5 V, 14 Bit, 125 MSPS TI 1 SN74ALVC08 SN74ALVC08D Quad AND gate TI 1 LT1004D LT1004CD-1-2/LT1004ID-1-2 Precision 1.2 V reference TI 0 NOT INSTALLED AD1580BRT Precision voltage reference, not installed 1 THS3001 THS3001CD/THS2001ID THS3001 high-speed op amp TI 4 W2 TSW-102-07-L-S or equivalent 2 position jumper_.1'' spacing, W2 Samtec 3 W3 TSW-102-07-L-S or equivalent 3 position jumper_.1'' spacing, W3 Samtec 2 2X3_JUMPER TSW-102-07-L-S or equivalent 6-Pin header dual row, 0.025x0.1, 2X3_JUMPER Samtec POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0.050 (1,27) 0.016 (0,40) 0- 8 A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / E 08/01 NOTES: A. B. C. D. 28 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLAS260A - FEBRUARY 2000 - REVISED SEPTEMBER 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 PACKAGE OPTION ADDENDUM www.ti.com 3-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS5651AIDW ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIDWG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIDWR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIPW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIPWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS5651AIPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS5651AIDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 THS5651AIPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS5651AIDWR SOIC DW 28 1000 346.0 346.0 49.0 THS5651AIPWR TSSOP PW 28 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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