19-2887; Rev. 2: 7/91 General Description The MAX900-903 high-speed, low-power, single/dual/ quad voltage comparators feature differential ana- log inputs and TTL logic outputs with active internal pull-ups. Fast propagation delay (8ns typ at 5mV overdrive) makes the MAX900-903 ideal for fast A/D converters and sampling circuits, line receivers, V/F converters, and many other data-discrimination ap- plications. All comparators can be powered from separate analog and digital power supplies or from a single combined supply voltage. The analog input common-mode range includes the negative rail, al- MA MAL/SVI High-Speed, Low-Power Voltage Comparators Features @ 8ns Typ Propagation Delay @ 18mW/Comparator Power Consumption (Typ at +5V) @ Separate Analog and Digital Supplies Flexible Analog Supply: +5V to +10V or +5V @ Input Range Includes Negative Supply Rail @ TTL Compatible Outputs # TTL Compatible Latch Inputs (Except MAX901) Ordering information lowing ground sensing when powered from a single PART TEMP. RANGE PIN-PACKAGE supply. The MAX900-903 consume 18mW per com- MAX900ACPP OC to +70C 20 Plastic DIP parator when powered from +5V. MAX900BCPP OC to +70C 20 Plastic DIP The MAX900-903 are equipped with independent MAX900ACWP oC to +70C 20 Wide SO : : rerrJre . ae 2 : TTL compatible latch inputs. The comparator output MAX900BC WP OC to 170C 20 Wide SO states are held when the latch inputs are driven low. L- - - a The MAX901 provides the same performance as the MAX900BC/D OC to +70C Dice MAX900, MAX902, and MAX903 with the exception MAX900AEPP -40C to +85C 20 Plastic DIP of the latches. | MAXSO0BEPP ss -40C to +85C 20 Plastic DIP Applications MAX900AEWP -40C to +85C 20 Wide SO High-Speed A/D Converters MAX900BEWP -40C to +85'C 20 Wide SO igh-Spee anv 9 p MAX900AMJP 55C to +125C 20 CERDIP High-Speed V/F Converters MAX900BMJP 55C to +125C 20 CERDIP Line Receivers Ordering information continued on page 11 Threshold Detectors * Contact factory for dice specifications. Input Trigger Circuitry High-Speed Data Sampling PWM Circuits Pin Configurations TOP VIEW AAAXLAA MAX902 MAAXLIA e _ MAX903 iN-(A) (7 | iN- (0) iN-(A) [1 | fia] vcc** Tw! iN (A) [2] (N+ (D) IN (A) 13] NC Veo" [1 | La | vou" Guo [3] Voc" cno [3] 7 Fa] our(e) Ns BE el Our out (a) [4 | OUT (0) tarcnia) [4], [14] LATCH (B) IN- af [6 | GND out (B) [5] OUT(C) our) [5] ho] Voot** vee [4 | 5 | LATCH vee" [6] Voo""* ne. [6| 9] N+ (B) Ns (B) [7] INe (C) ver [7] 8] IN) DIP/SO IN- (8) [| 9] IN(C) * ANALOG V- AND SUBSTRATE OIP/SO DIP/SO 7 ANALOG V+ Pin Configurations continued on page 12 DIGITAL V+ SVIA KI svi SVIA KI sv Maxim Integrated Products g.54 is aregistered trademark of Maxim Integrated Products. 06/206/1+06/006XUWMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ABSOLUTE MAXIMUM RATINGS (Note 1) Analog Supply Voltage (Vcc to VEE) ....... Digital Supply Voltage (VoD toGND)................-- +7V Differential Input Voltage .......... [VeE-0.2V ] to [Voc+0.2V] Common-Mode Input Voltage ...... [VEE-0.2V ] to [(Vcc+0.2V] Latch Input Voltage (MAX900/902/903 only) -0.2V to [Vop+0.2V] Output Short-Circuit Duration tOGND 0000. 0 eee Indefinite tOVOD 0 eee te eee 1 min Internal Power Dissipation ...............-.-0 0000. 500mWw Derate above +100C 6... eee tOmw/'C Operating Temperature Ranges: MAX900-903_C_ _ beeen e eee ee OC to +70C MAX900-903_E owe ee . -40C to +85C MAX900-903_M.o 8 6... eee -55C to +125C Junction Temperature (Tj). 0.000020. -65C to +160C Storage Temperature Range ............. -65C to +150C Lead Temperature (soldering, 10sec) .............. +300C Note 1: Absolute maximum ratings apply to both packaged parts and dice, unless otherwise noted. Stresses beyond those fisted under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and tu: .ctronal operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vcc = +5V, VEE = -5V, Vpp = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) MAX900A/901A MAX3900B/901B/902/903 PARAMETER SYMBOL| CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Input Offset Voltage Vos yom ny 05 1.0 10 40 mv Input Bias Current lB Jin+ or lIN- 3 6 4 10 pA input Offset Current los | YOM 5% 50-250 100 = 500-| nA Input Voltage Range VcM (Note 2) VeE-0.1 Vec-2.25 | Vee-0.1 Voc-2.25, V -8V<VoM<+2.75 Common-Mode _ , Rejection Ratio CMRR (Note 3). 50 150 75 250 pV/V Power-Supply Rejection Ratio PSRR (Note 3) 50 150 100 250 pV Output High Voltage VoH oA 24 35 24 35 V Output Low Voltage VoL (ema 03 0.4 0.3 0.4 Vv Latch Input Voltage High VLH (Note 4) 1.4 2.0 1.4 2.0 Vv Latch Input Voltage Low VEL (Note 4) 0.8 1.4 0.8 1.4 Vv Latch Input Current High ILH (hithe 4) 1 20 1 20 Latch Input Current Low ILL Note an 1 20 1 20 8-52 SULA XI /VvIHigh-Speed, Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (continued) (Vcc = +5V, VEE = -5V, VoD = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) PARAMETER SYMBOL | CONDITIONS MAXS00B/MAXSO1B MAKo02 ' MAX903 UNITS MIN TYP MAX |MIN TYP MAX | sw TYP MAX Pasitive Analog Supply Current ! tec - {Note 8) 10 15 5 8 [ 9 5 4) mA Negative Analog Supply Current lEE (Note 8) 7 12 3.5 6 | 2 3 mA Digital Supply Current lop {Note 8) 4 6 2 3 . _ 41s] mA Power Dissipation Po | yco=NBD= #8V. L 70 105 3555 L 18 28, mW TIMING CHARACTERISTICS (Voc = +5V, VEE = -5V. Von = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) S| pe poop pe ne a a i MAXSO0A/MAX901 A MAx902 | MAX903 PARAMETER 'SYMBOL| CONDITIONS |MAX900B/MAX901B | UNIT MIN TYP MAX | MIN TYP MAX Vop = 5mv, Input-to-Output High CL = 15pF, Response Time toot lo = 2mA 8 10 8 10 (Note 5) Vopb = 5mv, Input-to-Output Low - Ci = 15pF, | Response Time pa lo = 2mA 8 10 8 10 (Note 5) | _ |_ oo ap Difference in Response Time Between Outputs Mod (Notes 5, 6) 05 20 05 20 Latch Disabie to Output High Delay tpa+(D) | (Notes 4, 7) 10 10 Latch Disable to Output Low Delay tpa(D) | (Notes 4, 7) 12 12 Minimum Setup Time i ts (Notes 4, 7) 2 2 Minimum Hold Time th (Notes 4, 7) 1 1 SH Se | tow(D) | (Notes 4, 7) 10 10 Note 2: The input common-mode voltage and input signal voltages should nat be allowed to go negative by more than 0.2V below VEE. The upper end of the common-mode voltage range is typically Vcc-2V. but either or both inputs can go to a maximum of Vcoc+0.2V without damage. Note 3: +4.75V<Voc<+ 10.5V for single-supply operation with VEE grounded. Note 4: Note 5: Note 6: Note 7: Specification does not apply to MAX901. Guaranteed by design. Times are for 100mvV step inputs (see propagation delay characteristics in Figures 2 and 3) Maximum difference in propagation delay between any of the four comparators in the MAX900/901/902/903 See Timing Diagram (Figure 2). Owing to the difficult and critical nature of switching measurements involving the latch, these Tested for +4.75V<Voc<+5.25V, and -5.25V<VEE<-4.75V with VoD = +5V, although permissible analog power-supply range is parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test-jig Note 8: Icc tested for +4.75V<Vcc<+10.5V with VEE grounded. IEE tested for -5.25V<VeE<-4.75V with Vcc = +5V +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outputs at logic low. MAA KI/VI lob tested for 8-53 06/206/+06/006X UWMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (Voc = +8V, VEE = -SV, Vop = +5V, LE1-LE4 = Logic High; Ta = Full Operating Temperature, unless otherwise noted.) MAX900A/901A MAX900B/901B/902/903 | PARAMETER SYMBOL| CONDITIONS / UNITS MIN TYP MAX MIN TYP MAX | input Offset Voltage Vos vom, i 1 2 2 6 mv Input Bias Current Ip IN of lIN- 4 10 6 15 pA Input Offset Current los | YOM OY 100 500 200 800 -| nA input Voltage Range Vom (Note 2) VeeE-0.1 Vec-2.25| VeE-0.1 Voec-2.25 Vv _| -5V<VCM<+2.75V, i Common-Mode : CMRR Vo = 1.4V 80 250 120 500 VN | Rejection Ratio (Note 3) yu | __--. | Power-Supply Rejection Ratio PSRR (Note 3) 400 250 150 500 HV ~ | | Output High Voltage VOH Ne eso 2.4 35 24 35 i oy Output Low Voltage VoL hN=eoe 0.3 0.4 03 0.4 v { Latch Input Voltage High VLH (Note 8) 1.4 20 14 2.0 Vv | Latch Input Voltage Low VEL (Note 8) 08 1.4 0.8 1.4 Vv Latch Input Current High ILK (Note a 2 20 1 20 pA Latch Input Current Low IL hibte a 2 20 1 20 pA MAX300A/MAX901A MAX902 MAX903 PARAMETER SYMBOL | CONDITIONS | MAX800B/MAXx901B UNITS | MIN TYP MAX |MIN TYP MAX| MIN TYP MAX ' Positive Analog Supply Current Icoc (Note 8) 10 25 5 12 25 6 mA Negative Analog Supply Current lee (Note 8) 7 ~~ 20 35 10 2 5 |} mA Digital Supply Current IDD (Note 8) 4 10 2 5 1 25 mA ; Voc = Vob = +5V, Power Dissipation Po Vee = OV 70 105 35 $5 18 28 mw SMIA XIVHigh-Speed, Low-Power Voltage Comparators TIMING CHARACTERISTICS (Vcc = +5V, Vee = -5V, Vpo = +5V, LE1-LE4 = Logic High, Ta = TMIN to Tmax, unless otherwise noted.) Note 2: The input common-mode voltage or either input signa! voltage should not be allowed to go negative by more than 0.2V below Vee. The upper end of the common-mode voltage range is typically Vcc-2.0V, but either or both inputs can go to a maximum of Vcc +0.2V without damage. Note 3: Tested for +4.75V<Vcc<+5.25V, and -5.25V<VEE<-4.75V with Vop = +5V, although permissible analog power-supply range is +4,.75V<Vcc<+10.5V for single-supply operation with VEE grounded. Note 4: Specification does not apply to MAX901. Note 5: Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3). Note 6: Maximum difference in propagation delay between any of the four comparators in the MAX900/901/902/903. Note 7: See Timing Diagram (Figure 2). Owing to the difficult and critical nature of switching measurements involving the latch, these parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test-jig. Note 8: [cc tested for +4.75V<Vcc<+10.5V with VEE grounded. ice tested for -5.25V<VeE<-4.75V with Vcc = +5V. Ipp tested for +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outputs at logic low. MAX900A/901A MAX9008/901 B/902/903 PARAMETER SYMBOL CONDITIONS UNITS MIN TYP MAX MIN TYP MAX 9 Vop = SmV 8 Input-to-Output High CL = 15pF Response Time tod+ io = 2mA 10 15 10 15 ns S (Note 5) Vop = 5mV o Input-to-Output Low - CL = 15pF Response Time tod lo = 2mA 10 15 10 15 ns = (Note 5) Difference in Response Time Between Outputs Atpd (Notes 5, 6) 1 3 1 3 ns 8 Typical Operating Characteristics INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT LOW VOLTAGE vs. TEMPERATURE ys. TEMPERATURE (VoL) vs. LOAD CURRENT S = o S : 5 so 9 9 : > > Ta = -55C iE 2 : 0.3 a 5 pan ae 5 F g & B ot ta =+128C -40-20 0 20 40 60 80100120 -40-20 0 20 40 60 80 100120 2 4 10 TEMPERATURE (C) TEMPERATURE (C) LOAD CURRENT (ma) MAXISVI 8-55MAX900/901/902/903 High-Speed, Low-Power Voltage Comparators Typical Operating Characteristics (continued) Icc SUPPLY CURRENT INPUT OVERDRIVE vs. INPUT OVERDRIVE vs. (PER COMPARATOR) vs. Vcc UT OVERDRIVE vs. "UT OVERDRIVE SUPPLY VOLTAGE (Von = +5V) tpa+ RESPONS tod- RESPONSE TIME Ww WwW 3 8 z Ta = +125C 5 5 4 E >> >> 3 & Ta = +25C 5 Be 2 a A a FE = > 3 1 3 oo ua 5mV. > 3 3 a - z a a at > 2 92 INPUT OVERDRIVE O- 0 8 5-400 5-100 a a Zz Zz 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 Voc SUPPLY VOLTAGE (V) tpat RESPONSE TIME (ns) tpd- RESPONSE TIME (ns) RESPONSE TIME RESPONSE TIME vs. vs. TEMPERATURE LOAD CAPACITANCE (5mV (5mV OVERDRIVE) OVERDRIVE, Rrioap = 2.4kQ) 6 13 e 12 a = = wo w = = F 1 = w zg 9 % z z a 8 uo a w tpa- a = ? ipa 6 -40-20 0 20 40 60 80 100120 10 20 30 40 50 60 70 80 TEMPERATURE (C) LOAD CAPACITANCE (pF) 8-56 VIA AISsIHigh-Speed, Low-Power Voitage Comparators Pin Descriptions MAX900 MAX901 PIN NAME FUNCTION PIN NAME FUNCTION Negative Input _ Negative Input 4,10.11, 20) IN-(A,B.C,D) | (Channels A, B,C, D) 1.8,9,16 | IN-(AB.C.D) | (Channels A, B, C, D) Positive input Positive input 2,9, 12,19 IN+ (A, B,C, D) (Channels A, B,C, D) 2,7, 10, 15 IN+ (A, B, C, D) (Channels A, B, C, D) 3 GND Ground Terminal 3 GND Ground Terminal Latch Input Output 4,7,14,17 | LATCH (A, B, , D) (Channels A, B, C, D) 4.5,12,13 | OUT(A,8,C, DB) (Channets A, B, C.D) Output Negative Analog Supply 5,6, 15,16 | OUT (A,B,C, D) (Channels A, B.C, D) 6 Vee and Substrate 8 Vi Negative Analog Supply fT] Vop Positive Digital Supply EE and Substrate 14 Vcc Positive Analog Supply 13 VoD Positive Digital Supply 18 Vcc Positive Analog Supply MAX302 MAX903 PIN NAME FUNCTION PIN NAME FUNCTION Negative Input 1 Vcc Positive Analog Supply 1.8 IN-(A, 8) (Channets A, B} 2 IN+ Positive Input Positive Input ro 2,9 IN+ (A, B) (Channels A, B) 3 IN- Negative Input 3 GND Ground Terminal 4 Vee Negative Analog Supply and Substrate Latch Input 411 LATCH (A,B) | Channels A, B) 5 LATCH Latch Input Output 6 GND Ground Terminal 5.12 OUT (A, B) (Channels A. B) 7 OUT Output 6, 13 N.C. No Connect 8 Vop Positive Digital Supply 7 V Negative Analog Supply EE and Substrate 10 Voo Positive Digital Supply 14 Vcc Positive Analog Supply MAAI tI 8-57 = Se 3 > S N S oMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators Applications Information Circuit Layout Because of the large gain-bandwidth transfer function of the MAX900-903, special precautions must be taken to realize their full high-speed capability. A printed circuit board with a good, low-inductance ground plane is man- datory. All decoupling capacitors (the smal! 100nF ce- ramic type is a good choice) should be mounted as close as possible to the power-supply pins. Separate decou- pling capacitors for analog Vcc and for digital Vpp are also recommended. Close attention should be paid to the bandwidth of the decoupling and terminating components. Short lead lengths on the inputs and outputs are essential to avoid unwanted parasitic feedback around the compa- rators. Solider the device directly to the printed circuit board instead of using a socket. Input Slew-Rate Requirements As with all high-speed comparators, the high gain- bandwidth product of the MAX900-903 can create oscil- lation problems when the input traverses the linear region. For clean output switching without oscillation or steps in the output waveform, the inout must meet minimum slew- rate requirements. Oscillation is largely a function of board layout and of coupled source impedance and stray input capacitance. Both poor layout and large source impedance will cause the part to oscillate and increase the minimum slew-rate requirement. In some applica- tions, it may be heipful to apply some positive feedback between the output and + input. This pushes the output through the transition region cleanly, but applies a hys- teresis in threshold seen at the input terminals. TTL Output and Latch Inputs The comparator TTL output stages are optimized for driving low-power Schottky TTL with a fan-out of four. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to changes at the input terminals. When the latch is connected to a TTL low level, the comparator output latches in the same state as at the instant that the latch command is applied, and will not respond to sub- sequent changes at the input. No latch is provided on the MAX901. Power Supplies The MAX900-903 can be powered from separate analog and digital supplies or from a single +5V supply. The analog supply can range from +5V to +10V with VEE grounded for single-supply operation (Figures 1A and 1B) or from asplit+5V supply (Figure 1C). The Voo digital supply always requires +5V In high-speed, mixed-signal applications where a com- mon ground is shared, a noisy digital environment can adversely affect the analog input signal. When set up with separate supplies (Figure 1C), the MAX900-903 isolate analog and digital signals by providing a separate AGND(VEE) and DGND. Typical Power-Supply Alternatives +10V +5V +5V OUT OUT GND GND Vee + BV Figure 1A. Separate Analog Supply, Common Ground Ground 8-58 Figure 1B. Single +5V Supply, Common Figure 1C. Splitt5V Supply, Separate Ground SVIAXISVIHigh-Speed, Low-Power Voltage Comparators Definition of Terms Vos VIN Voo tpd+ tpd+ (D) MAAIsVI Input Offset Voltage: Voltage applied be- tween the two input terminals to obtain TTL logic threshoid (+1.4V) at the output. tnput Voltage Pulse Amplitude: Usually set to 100mV for comparator specifications. Input Voltage Overdrive: Usually set to 5mvV and in opposite polarity to Vin for com- parator specifications. Input to Output High Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output low to high transistion. Input to Output Low Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output high to low transition. Latch Disable to Output High Delay: The propagation delay measured from the latch signat crossing the TTL threshold in a low to high transition to the point of the output cross- ing TTL threshold in a low to high transition. tpd-(D) Latch Disable to Output Low Delay: th tow (D) The propagation delay measured from the latch signal crossing the TTL threshold in a low to high transition to the point of the output crossing TTL threshold in a high to low tran- sition. Minimum Setup Time: The minimum time before the negative transition of the latch sig- nal that an input signal change must be pres- ent in order to be acquired and held at the outputs. Minimum Hold Time: The minimum time after the negative transition of the latch sig- nal that an input signal must remain un- changed in order to be acquired and held at the output. Minimum Latch Disable Pluse Width: The minimum time that the latch signal must re- main high in order to acquire and hold an input signal change. 8-59 : S S M4 QMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators LATCH cgMpane COMPARE ENABLE DIFFERENTAL INPUT VOLTAGE OV OUTPUT ov Vag t s5mV ee ee _- INPUT COMPARATOR 1av U 100rv OUTPUT Sns/DIV Figure 2. MAX900/902/903 Timing Diagram Figure 3. tbat Response Time to 5mV Overdrive INPUT TO 10X Veo +5V V0 +5 Vv SCOPE PROBE (10M, 14pF) >. OUTPUT 7 _ a ~ 1 100nF L PRECISION tk o 2.43k STEP > = GENERATOR ov 10k DUT. OUTPUT TO 10X INPUT 100mV V y SCOPE PROBE oC 4 10MQ, 14pF OFFSET 10 FL! mf) ADJUST _[roone [too [oon Vos = = = = +5mV Vee -5V Sns/OV Figure 4. tpa- Response Time to 5mV Overdrive 8-60 Figure 5. Response-Time Setup MUA AIsviHigh-Speed, Low-Power Voltage Comparators OUTPUT W/DIV INPUT Sns/DIV OUTPUT 1v/DIV INPUT tomv/olv Sns/DIV Figure 6. Response to SOMHz Sine Wave +1 25V VREF AAAXLAN INT" MX7228 VOACI Vourt OCTAL est oF > Na 4 DAC | IN3 wT T, 1N4 iP CONTROL] LOGIC On | Vv = E ING VV VDAC8 IN? 4 Vout8 VY INB MAX901 UNDER LIMIT OVER LIMIT UNDER LIMIT UNDER LIMIT UNDER LIMIT UNDER LIMIT OVER UMIT OVER LIMIT Figure 8. Alarm Circuit Level-Monitors Eight Separate inputs Figure 7. Response to 100MHz sine wave photo Typical Application Programmed, Variable-Alarm Limits By combining two quad analog comparators with an octal, 8-bit D/A converter (the MX7228), several alarm and limit-defect functions can be performed simulta- neously without external adjustments. The MX7228's internal latches allow the system processor to set the limit points for each comparator independently and update them at any time. Set the upper and lower thresholds for a single transducer by pairing the D/A converter and comparator sections. 8-61 MIAXKIZVI 06/206/+06/006XVWMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators _ Ordering Information (continued) Pin Configurations (continued) TOP VIEW In- (A) [4 | IN+ (Ab [2 | GND [3 | LATCH (A}E4 | a OUT (A) [5 |} an saeisan MAX900 our (8) [6 | 5 3 15] OUT (C} LATCH (8) [ 7 | H14] LATCH (C) vee* [8 | 3] Voo*** IN (B) [9 | 12] IN (C) iN- (8) fro] 4] IN-(C) 20) in- (0) Hg] iN+(D) 8] Ves" 7] LATCH (0) 16] OUT (0} DIP/SO ANALOG V- AND SUBSTRATE * ANALOG V+ ** DIGITAL V+ PART TEMP. RANGE PIN-PACKAGE MAX901ACPE OC to +70C 16 Plastic DIP MAX901BCPE OC to +70C 16 Plastic DIP MAX901ACSE OC to +70C 16 Narrow SO MAX901BCSE OC to +70C 16 Narrow SO MAX901BC/D OC to +70C Dice* MAX901AEPE -40C to +85C 16 Plastic DIP MAX901BEPE -40C to +85C 16 Plastic DIP MAX901AESE -40C to +85C 16 Narrow SO MAX901BESE -40C to +85C 16 Narrow SO MAX901AMJE -55C to +125C 16 CERDIP MAX901BMJE -55C to +125C 16 CERDIP MAX902CPD O'C to +70C 14 Plastic DIP MAX302CSD OC to +70C 14 Narrow SO MAX902C/D OC to +70C Dice* MAX902EPD -40C to +85C 14 Plastic DIP MAX902ESD -40C to +85C 14 Narrow SO MAX902MJD -55C to +125C 14 CERDIP MAX903CPA OC to +70C 8 Plastic DIP MAX903CSA OC to +70C 8S0 MAX903C/D OC to +70C Dice* MAX303EPA -40C to +85C 8 Plastic DIP MAX303ESA -40C to +85C 8SO MAX303MJA -55C to + 125C 8 CERDIP * Contact factory for dice specifications. Chip Topography OUT LATCH vec (0) (Cc) (2.18mm) +IN(C) -IN(C) 9 96g" (1.73mm) -IN(B) Note: Substrate connected to Vee. MAX900/901/902/903 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time. 8-62 MIAXKIsI