0.8V Reference Ultra Low Dropout (0.25V@3A) Linear Regulator
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw1
•Ultra Low Dropout
- 0.25V(typical) at 3A Output Current
•Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
•0.8V Reference Voltage
•High Output Accuracy
- ±1.5% over Line, Load and Temperature
•Fast Transient Response
•Adjustable Output Voltage by External
Resistors
•Power-On-Reset Monitoring on Both VCNTL
and VIN Pins
•Internal Soft-Start
•Current-Limit Protection
•Under-Voltage Protection
•Thermal Shutdown with Hysteresis
•Power-OK Output with a Delay Time
•Shutdown for Standby or Suspend Mode
•Simple SOP-8-P Package with Exposed Pad
•Lead Free Available (RoHS Compliant)
Features
The APL5913 is a 3A ultra low dropout linear regulator.
This product is specifically designed to provide well
supply volatage for front-side-bus termination on
motherboards and NB applications. The IC needs two
supply voltages, a control voltage for the circuitry and
a main supply voltage for power conversion, to reduce
power dissipation and provide extremely low dropout.
The APL5913 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages to
prevent wrong operations. A thermal shutdown and
current limit functions protect the device against
thermal and current over-loads. A POK indicates the
output status with time delay which is set internally. It
can control other converter for power sequence. The
APL5913 can be enabled by other power system.
Pulling and holding the EN pin below 0.3V shuts off
the output.
The APL5913 is available in SOP-8-P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance, being applicable
in 2~3W applications.
Applications
Pin Configuration
SOP-8-P (Top View)
General Description
(connected to VIN plane for better heat
dissipation)
= Exposed Pad
1
2
3
4
8
7
6
5
EN
POK
VCNTL
VIN
GND
FB
VOUT
VOUT
VIN
•Front Side Bus VTT (1.2V/3A)
•Note Book PC Applications
•Motherboard Applications
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw2
Package Code
KA : SOP-8-P
Operating Ambient Temp. Range
C : 0 to 70 C
Handing Code
TU : Tube TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
APL5913 -
Handling Code
Temp. Range
Package Code
APL5913
XXXXX
APL5913 KA :XXXXX - Date Code
Lead Free Code
Ordering and Marking Information
°
Block Diagram
GND
VOUT
VINVCNTL
Current
Limit
Thermal
Limit
EN
VREF
0.8V
FB
90%
VREF
Delay
POK
Power-
On-Reset
Soft-Start
and
Control Logic
0.4V
UV
EAMP
POK
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw3
Typical Application Circuit
1. Using an Output Capacitor with ESR≥18mΩ
2. Using an MLCC as the Output Capacitor
VCNTL
+5V
VOUT
+1.2V / 3A
CCNTL
1uF
VIN
+1.5V
GND
VOUT
VCNTL
POK VIN
CIN
100uF
COUT
220uF
EN
Enable EN
POK
R3
1k 5
3
61
8
7
APL5913
R1
1k
C1
33nF (in the range of 12 ~ 48nF)
VOUT 4
FB 2
R2
2k
VCNTL
+5V
VOUT
+1.2V / 3A
CCNTL
1uF
VIN
+1.5V
GND
VOUT
VCNTL
POK VIN
CIN
22uF
COUT
22uF
EN
Enable EN
POK
R3
1k 5
3
61
8
7
APL5913
R1
39k
C1
56pF
VOUT 4
FB 2
R2
78k
VOUT (V) R1 (kΩ) R2 (kΩ) C1 (pF)
1.05 43 137.6 47
1.5 27 30.86 82
1.8 15 12 150
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw4
Absolute Maximum Ratings
Thermal Characteristics
Recommended Operating Conditions
Symbol Parameter Rating Unit
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 3.3 V
VI/O EN and FB to GND -0.3 ~ VCNTL+0.3 V
VPOK POK to GND -0.3 ~ 7 V
PD Average Power Dissipation 3 W
PPEAK Peak Power Dissipation (<20mS) 20 W
TJ Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Soldering Temperature, 10 Seconds 300 oC
VESD Minimum ESD Rating (Human Body Mode) ±2 kV
Symbol Parameter Value Unit
θJA Junction-to-Ambient Thermal Resistance in Free Air (Note) 40 oC/W
Note : θJA is measured with the component mounted on a high effective thermal conductivity test
board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB.
Symbol Parameter Range Unit
VCNTL VCNTL Supply Voltage 3.1 ~ 6 V
VIN VIN Supply Voltage 1.1 ~ 3.3 V
VOUT
Output Voltage
V
CNTL=3.3±5%
V
CNTL=5.0±5%
0.8 ~ 1.2
0.8 ~ VIN-0.2
V
IOUT VOUT Output Current 0 ~ 4 A
TJ Junction Temperature -25 ~ 125 oC
Electrical Characteristics
APL5913
Symbol Parameter Test Conditions Min Typ Max
Unit
SUPPLY CURRENT
ICNTL VCNTL Nominal Supply Current
EN = VCNTL 0.4 1 8 mA
ISD VCNTL Shuntdown Current EN = GND 180 300 µA
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw5
Electrical Characteristics (Cont.)
APL5913
Symbol
Parameter Test Conditions Min
Typ
Max
Unit
POWER-ON-RESET
VCNTL POR Threshold VCNTL Rising 2.7
2.9
3.1
V
VCNTL POR Hysteresis 0.4
V
VIN POR Threshold VIN Rising 0.8
0.9
1.0
VIN POR Hysteresis 0.5
V
OUTPUT VOLTAGE
VREF Reference Voltage FB =VOUT 0.8
V
Output Voltage Accuracy IOUT=0A ~ 5A, TJ= -25 ~125oC -1.5
+1.5
%
Line Regulation VCNTL=3.3 ~ 5V 0.06
0.15
%
Load Regulation IOUT=0A ~ 3A 0.06
0.15
%
DROPOUT VOLTAGE IOUT = 3A, VCNTL=5V, TJ= 25oC 0.17
0.25
V
Dropout Voltage IOUT = 3A, VCNTL=5V, TJ= -50~125oC
0.3
V
PROTECTION
VCNTL=5V, TJ= 25oC 3.8
5 6.2
A
VCNTL=5V, TJ= -25 ~ 125oC 4 A
VCNTL=3.3V, TJ= 25oC 3.8
4.8
5.3
A
ILIM Current Limit
VCNTL=3.3V, TJ= -25 ~ 125oC 3.8
A
TSD Thermal Shutdown Temperature
TJ Rising 150
oC
Thermal Shutdown Hysteresis 50 oC
Under-Voltage Threshold VFB Falling 0.4
V
ENABLE and SOFT-START
EN Logic High Threshold Voltage
VEN Rising 0.3
0.4
0.5
V
EN Hysteresis 30 mV
EN Pin Pull-Up Current EN=GND 10 µA
TSS Soft-Start Interval 2 mS
POWER OK and DELAY
VPOK POK Threshold Voltage for Power
OK VFB Rising 90%
92%
94%
VREF
VPNOK POK Threshold Voltage for Power
Not OK VFB Falling 79%
81%
83%
VREF
POK Low Voltage POK sinks 5mA 0.25
0.4
V
TDELAY
POK Delay Time 1 3 10
mS
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw6
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
-50 -25 025 50 75 100 125
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
50
100
150
200
250
300
350
400
450
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 025 50 75 100 125
Typical Operating Characteristics
VCNTL Supply Current vs. Junction Temperature
VCNTL Supply Current, ICNTL (mA)
Junction Temperature (°C)
VCNTL=3.3V
VCNTL=5V
Current-limit vs. Junction Temperature
Current-limit, ILIM (A)
Junction Temperature (°C)
VCNTL=3.3V
VCNTL=5V
Dropout Voltage vs. Output CurrentDropout Voltage vs. Output Current
Dropout Voltage (mV)
Dropout Voltage (mV)
Output Current, lOUT(A)Output Current, lOUT(A)
VCNTL=3.3V
VOUT=1.2VVCNTL=5V
VOUT=1.2VTJ=125°C
TJ=75°C
TJ=25°C
TJ=0°C
TJ=-25°C
TJ=125°C
TJ=75°C
TJ=25°C
TJ=0°C
TJ=-25°C
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw7
-70
-60
-50
-40
-30
-20
-10
0
100 1000 10000 100000 1000000
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
-50 -25 025 50 75 100 125
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
-50 -25 025 50 75 100 125
Typical Operating Characteristics
Junction Temperature (°C)Junction Temperature (°C)
Reference Voltage vs. Junction Temperature
Referemce Voltage, VREF (mV)
POK Delay Time vs. Junction Temperature
POK Delay Time (ms)
VCNTL=3.3V
VCNTL=5V
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
100 1000 10000 100000 1000000
Frequency (Hz)
Ripple Rejection (dB)
VCNTL PSRR
VCNTL = 4.5V~5.5V
VIN = 1.5V
VOUT = 1.2V
IOUT = 3A
CIN = 100µF
COUT = 330uF(ESR=30mΩ)
Amplitude (dB)
VIN PSRR
Frequency (Hz)
VCNTL = 5V
VIN = 1.5V(lower bound)
VINPK-PK = 100mV
CIN = 47µF
COUT = 330uF(30mΩ)
IOUT = 3A
VOUT = 1.2V
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw8
Operating Waveforms
+5V
C3
1uF C4
470uF x2
C5
1000uF x2
L2
3.3uH
Q1
APM2014N
UGATE
LGATE 4
VCC
5
GND
3
OCSET
7
PHASE 8
Q2
APM2014N
C2
1uF
2
U2
APW7057
FB
6
BOOT 1
D1
1N4148
R7
2k C7
0.1uF
R5
1.75k
R8
8.2k
C6
0.1uF
Q3
Shutdown
R6
0
R4
2.2
C8
470pF
L1
1uH
C9
47uF VCNTL
+5V
VOUT
+1.2V/3A
CVCNTL
1uF
VIN
+1.5V
GND
VOUT
VCNTL
POK
VIN
CIN
100uF
COUT
220uF
EN
Enable EN
POK
R3
1k
7
3
61
8
5
U1
APL5913
R1
1k
C1
33nF
VOUT 4
FB 2
R2
2k
1. Load Transient Response :
1.1 Using an Output Capacitor with ESR≥18mΩ
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µS
IOUT = 10mA -> 3AIOUT = 10mA -> 3A ->10mAIOUT = 3A -> 10mA
VOUT
IOUT
VOUT
IOUT
VOUT
IOUT
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 1A/Div
Time : 2µS/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 1A/Div
Time : 20µS/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 1A/Div
Time : 2µS/Div
R1=1kΩ, R2=2kΩ, C1=33nFR1=1kΩ, R2=2kΩ, C1=33nF
11
22
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw9
Operating Waveforms (Cont.)
2. Power ON / Power OFF :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
Ch1 : VIN,1V/div
Ch2 : VOUT,1V/div
Ch3 : VPOK,1V/div
Ch4 : VCNTL,2V/div
Time : 10ms/div
Power ON
VIN
VOUT
VCNTL
VPOK
Ch1
Ch2
Ch3
Ch4
Ch1 : VIN,1V/div
Ch2 : VOUT,1V/div
Ch3 : VPOK,1V/div
Ch4 : VCNTL,2V/div
Time : 10ms/div
Ch1
Ch2
Ch3
Ch4
Power OFF
VIN
VOUT
VPOK
VCNTL
Ch1
Ch2
Ch3
Ch4
Power OFF
VINVIN
VOUTVOUT
VPOKVPOK
VCNTLVCNTL
1.2 Using an MLCC as the Output Capacitor
- COUT = 22µF/6.3V (ESR = 3mΩ), CIN = 22µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µS
IOUT = 10mA -> 3AIOUT = 10mA -> 3A ->10mAIOUT = 3A -> 10mA
VOUT
IOUT
VOUT
IOUT
VOUT
IOUT
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 1A/Div
Time : 2µS/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 1A/Div
Time : 20µS/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 1A/Div
Time : 2µS/Div
11
22
11
22
11
22
R1=39kΩ, R2=78kΩ
C1=56pF
R1=39kΩ, R2=78kΩ
C1=56pF
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw10
Ch1 : VIN,1V/div
Ch2 : VOUT,1V/div
Ch3 : VPOK,1V/div
Time : 1ms/div
Operating Waveforms (Cont.)
POK Delay
Ch1
Ch2
Ch3
VIN
VOUT
VPOK
POK Delay
Ch1
Ch2
Ch3
VINVIN
VOUTVOUT
VPOKVPOK
4. POK Delay :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
Ch1 : VEN,5V/div
Ch2 : VOUT,1V/div
Ch3 : IOUT,1A/div
Ch4 : VPOK,1V/div
Time : 1ms/div
Ch1 : VEN,5V/div
Ch2 : VOUT,1V/div
Ch3 : IOUT,1A/div
Ch4 : VPOK,1V/div
Time : 1ms/div
Ch1
Ch2
Ch3
Ch4
Shutdown
VEN
VOUT
IOUT
VPOK
Ch1
Ch2
Ch3
Ch4
Shutdown
VENVEN
VOUTVOUT
IOUTIOUT
VPOKVPOK
3. Shutdown and Enable :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
Ch1
Ch2
Ch3
Ch4
Enable
VEN
VOUT
IOUT
VPOK
Ch1
Ch2
Ch3
Ch4
Enable
VENVEN
VOUTVOUT
IOUTIOUT
VPOKVPOK
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw11
Functional Pin Description
GND (Pin 1)
Ground pin of the circuitry. All voltage levels are
measured with respect to this pin.
FB (Pin 2)
Connecting this pin to an external resistor divider
receives the feedback voltage of the regulator. The
output voltage set by the resistor divider is determined
by:
where R1 is connected from VOUT to FB with Kelvin
sensing and R2 is connected from FB to GND. A
bypass capacitor may be connected with R1in parallel
to improve load transient response. The recommended
R2 and R1 are in the range of 100~10kΩ.
VOUT (Pin 3,4)
Output of the regulator. Please connect Pin 3 and 4
together using wide tracks. It is necessary to connect
a output capacitor with this pin for closed-loop
compensation and improving transient responses.
VIN (Pin 5) and Exposed Pad
Main supply input pins for power conversions. The
Exposed Pad provide a very low impedance input path
Functional Description
Power-On-Reset
A Power-On-Reset (POR) circuit monitors both input
voltages at VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
after the two supply voltages exceed their rising POR
threshold voltages during powering on. The POR
function also pulls low the POK pin regardless the
output voltage when the VCNTL voltage falls below it’s
falling POR threshold.
+⋅=R2
R1
10.8 VOUT (V)
for the main supply voltage. Please tie the Exposed
Pad and VIN Pin (Pin 8) together to reduce the dropout
voltage. The voltage at this pins is monitored for Power-
On Reset purpose.
VCNTL (Pin 6)
Power input pin of the control circuitry. Connecting
this pin to a +5V (recommended) supply voltage
provides the bias for the control circuitry. The voltage
at this pin is monitored for Power-On Reset purpose.
POK (Pin 7)
Power-OK signal output pin. This pin is an open-drain
output used to indicate status of output voltage by
sensing FB voltage. This pin is pulled low when the
rising FB voltage is not above the VPOK threshold or
the falling FB voltage is below the VPNOK threshold,
indicating the output is not OK.
EN (Pin 8)
Enable control pin. Pulling and holding this pin below
0.3V shuts down the output. When re-enabled, the IC
undergoes a new soft-start cycle . Left this pin open,
an internal current source 10mA pulls this pin up to
VCNTL voltage, enabling the regulator.
Internal Soft-Start
An internal soft-start function controls rise rate of the
output voltage to limit the current surge at start-up.
The typical soft-start interval is about 2mS.
Output Voltage Regulation
An error amplifier working with a temperature-
compensated 0.8V reference and an output NMOS
regulates output to the preset voltage. The error
amplifier designed with high bandwidth and DC gain
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw12
Functional Description (Cont.)
Application Information
Power Sequencing
The power sequencing of VIN and VCNTL is not necessary
to be concerned. But do not apply a voltage to VOUT
for a long time when the main voltage applied at VIN is
not present. The reason is the internal parasitic diode
from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
Output Capacitor
The APL5913 requires a proper output capacitor to
maintain stability and improve transient response over
temperature and current. The output capacitor selection
is to select proper ESR(equivalent series resistance)
and capacitance of the output capacitor for good stability
and load transient response.
provides very fast transient response and less load
regulation. It compares the reference with the feedback
voltage and amplifies the difference to drive the output
NMOS which provides load current from VIN to VOUT.
Current-Limit
The APL5913 monitors the current via the output
NMOS and limits the maximum current to prevent load
and APL5913 from damages during overload or short-
circuit conditions.
Under-Voltage Protection (UVP)
The APL5913 monitors the voltage on FB pin after
soft-start process is finished. Therefore the UVP is
disable during soft-start. When the voltage on FB pin
falls below the under-voltage threshold, the UVP
circuit shuts off the output immediately. After a while,
the APL5913 starts a new soft-start to regulate output.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature
of APL5913. When the junction temperature exceeds
+150°C, a thermal sensor turns off the output NMOS,
allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start
cycle after the junction temperature cools by 50°C,
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown designed
Output Voltage Regulation (Cont.)with a 50oC hysteresis lowers the average junction
temperature during continuous thermal overload
conditions, extending life time of the device.
For normal operation, device power dissipation should
be externally limited so that junction temperatures will
not exceed +125°C.
Enable Control
The APL5913 has a dedicated enable pin (EN). A logic
low signal (VEN< 0.3V) applied to this pin shuts down
the output. Following a shutdown, a logic high signal
re-enables the output through initiation of a new
softstart cycle. Left open, this pin is pulled up by an
internal current source (10µA typical) to enable
operation. It’s not necessary to use an external transistor
to save cost.
Power-OK and Delay
The APL5913 indicates the status of the output voltage
by monitoring the feedback voltage (VFB) on FB pin.
As the VFB rises and reaches the rising Power-OK
threshold (VPOK), an internal delay function starts to
perform a delay time. At the end of the delay time, the
IC turns off the internal NMOS of the POK to indicate
the output is OK. As the VFB falls and reaches the
falling Power-OK threshold (VPNOK), the IC immediately
turns on the NMOS of the POK to indicate the output
is not OK without a delay time.
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw13
Application Information (Cont.)
Output Capacitor (Cont.)
The APL5913 is designed with a programmable
feedback compensation adjusted by an external
feedback network for the use of wide ranges of ESR
and capacitance in all applications. Ultra-low-ESR
capacitors (such as ceramic chip capacitors), low-ESR
bulk capacitors (such as solid Tantalum, POSCap, and
Aluminum electrolytic capacitors) all can be used as
an output capacitor. The value of the output capacitors
can be increased without limit.
During load transients, the output capacitors,
depending on the stepping amplitude and slew rate of
load current, are used to reduce the slew rate of the
current seen by the APL5913 and help the device to
minimize the variations of output voltage for good
transient response. For the applications with large
stepping load current, the low-ESR bulk capacitors
are normally recommended.
Decoupling ceramic capacitors must be placed at the
load and ground pins as close as possible and the
impedance of the layout must be minimized.
Input Capacitor
The APL5913 requires proper input capacitors to sup-
ply current surge during stepping load transients to
prevent the input rail from dropping . Because the
parasitic inductor from the voltage sources or other
bulk capacitors to the VIN pin limit the slew rate of the
surge currents. More parasitic inductance needs more
input capacitance.
Ultra-low-ESR capacitors, such as ceramic chip
capacitors, are very good for the input capacitors An
aluminum electrolytic capacitor (>100mF, ESR
<300mW) is recommended as the input capacitor. It
is not necessary to use low-ESR capacitors. More
capacitance reduce the variations of the input voltage
of VIN pin.
Feedback Network
Figure 1 shows the feedback network between VOUT,
GND and FB pins. It works with the internal error
amplifier to provide proper frequency response for the
linear regulator. The ESR is the equivalent series
resistance of the output capacitor. The COUT is ideal
capacitance in the output capacitor. The VOUT is the
setting of the output voltage.
VERR VFB
R1
R2
C1
VOUT
FB
VOUT
VREF
EAMP
APL5913
COUT
ESR
Figure 1
The feedback network selection depends on the values
of the ESR and COUT, which has been classified into
three conditions:
• Condition 1 : Large ESR ( ≥18mΩ )
- Select the R1 in the range of 400Ω ~ 2.4kΩ
- Calculate the R2 as the following :
- Calculate the C1 as the following :
• Condition 2 : Middle ESR
- Calculate the R1 as the following:
(1) ..........
0.8-V0.8
R1R2 (V)OUT(V)
(V)
)(k)(k ⋅=ΩΩ
(2) ......
R1
V
40C1
R1
V
10 )(k
OUT(V)
(nF)
)(k
OUT(V)
ΩΩ ⋅≤≤⋅
(3) ......... 15V37.5
ESR
2157
R1 OUT(V)
)(m
)(k +⋅−= Ω
Ω
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw14
Feedback Network (Cont.)
Application Information (Cont.)
Select a proper R1(selected) to be a little larger
than the calculated R1.
- Calculate the C1 as the following :
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation:
Where R1=R1(calculated) from equation (3)
If the C1(calculated) can not meet the equation
(5), please use the Condition 3.
- Use equation (2) to calculate the R2.
• Condition 3 : Low ESR (eg. Ceramic Capacitors)
- Calculate the R1 as the following:
Select a proper R1(selected) to be a little larger
than the calculated R1. The minimum selected
R1 is equal to 1kΩ when the calculated R1 is
smaller than 1k or negative.
- Calculate the C1 as the following :
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (7) must meet
the following equation :
Where R1=R1(calculated) from equation (6)
If the C1(calculated) can not meet the equation (8),
please use the Condition 2.
- Use equation (2) to calculate the R2.
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
[ ]
(4) ........
R1
C
101ESR0.71C1 )(k
OUT(uF)
)(m(pF) Ω
Ω⋅+⋅=
(5) ..
R1V37.5
1
ESR
143
17.2C1 )(k
OUT(V)
)(m
(pF)
⋅
+⋅
+⋅≥ΩΩ
(6) .. V37.5C300)ESR(2.1R1 OUT(V)OUT(uF))(m)(k ⋅−⋅+⋅=ΩΩ
(7) ..
R1V37.5
1C34.2)ESR(0.24C1 )(k
OUT(V)
OUT(uF))(m(pF)
⋅
+⋅⋅+⋅=Ω
Ω
(8) .. CESR
R1V1.25
0.033C1 OUT(uF))(m
)(k
OUT(V)
(pF) ⋅⋅
⋅
+≥ Ω
Ω
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
on the PCB. The main current flow is through the
exposed pad. Refer Figure 3 to make a proximate
topology.
2. Please place the input capacitors for VIN and
VCNTL pins near pins as close as possible.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible.
4. To place APL5913 and output capacitors near the
load is good for performance.
5. The negative pins of the input and output capaci-
tors and the GND pin of the APL5913 are connected
to the ground plane of the load.
6. Please connect PIN 3 and 4 together by a wide
track.
7. Large current paths must have wide tracks.
8. See the Typical Application
(see next page Figure 2)
- Connect the one pin of the R2 to the GND of
APL5913
- Connect the one pin of R1 to the Pin 3 of APL5913
- Connect the one pin of C1 to the Pin 3 of APL5913
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw15
Application Information (Cont.)
PCB Layout Considerations (Cont.)
VCNTL
VOUT
CCNTL
VIN
GND
VOUT
VCNTL VIN
CIN
COUT
APL5913
R1
C1
VOUT
FB
R2
Load
Figure 2
Thermal Considerations
See Figure 3. The SOP-8-P is a cost-effective package
featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The exposed pad must be soldered to
the top VIN plane. The copper of the VIN plane on the
Top layer conducts heat into the PCB and air. Please
enlarge the area to reduce the case-to-ambient resistance
(θCA).
Figure 4
Exposed
Pad
Die Top
V
IN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8-P
5
6
7
8
1
2
3
4
Top
V
OUT
plane
Figure 4
Exposed
Pad
Die Top
V
IN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8-P
5
6
7
8
1
2
3
4
Top
V
OUT
plane
Figure 3
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw16
Packaging Information
HE
e1 e2
0.015X45
D
A
A1
0.004max.
1
L
E1
D1
SOP-8-P pin ( Reference JEDEC Registration MS-012)
Millimeters Inches
Dim Min. Max. Min. Max.
A1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
D4.80 5.00 0.189 0.197
D1 3.00REF 0.118REF
E3.80 4.00 0.150 0.157
E1 2.60REF 0.102REF
H5.80 6.20 0.228 0.244
L0.40 1.27 0.016 0.050
e1 0.33 0.51 0.013 0.020
e2 1.27BSC 0.50BSC
φ 1 8°8°
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw17
Physical Specifications
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
t 25 C to Peak
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Classificatin Reflow Profiles
(mm)
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classificatioon Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw18
Carrier Tape & Reel Dimensions
t
Ao
E
W
Po P
Ko
Bo
D1
D
F
P1
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 SEC
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reliability Test Program
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Table 2. Pb -free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm 3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Classification Reflow Profiles(Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.4 - May., 2005
APL5913
www.anpec.com.tw19
Application Carrier Width Cover Tape Width Devices Per Reel
SOP- 8/-P 12 9.3 2500
Cover Tape Dimensions
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Customer Service
Application
A
B
C
J
T1
T2
W
P
E
330 ± 1
62 +1.5 12.75+ 0.15
2 ± 0.5
12.4 ± 0.2
2 ± 0.2
12±
0. 3
8± 0.1
1.75±0.1
F D D1 Po P1 Ao Bo Ko t
SOP- 8/-P
5.5± 1 1.55 +0.1
1.55+ 0.25
4.0 ± 0.1
2.0 ± 0.1
6.4 ± 0.1
5.2±
0. 1
2.1± 0.1
0.3
±0.013
Carrier Tape & Reel Dimensions(Cont.)
A
J
B
T2
T1
C
(mm)
