MC100EPT21DTG - ON SEMICONDUCTOR

March, 2010 − Rev. 21

1Publication Order Number:

MC100EPT21/D

MC100EPT21

3.3V Differential

LVPECL/LVDS/CML to

LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to

LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),

LVDS, and positive CML input levels and LVTTL/LVCMOS output

levels are used, only +3.3 V and ground are required. The small

outline 8−lead SOIC package makes the EPT21 ideal for applications

which require the translation of a clock or data signal.

The VBB output allows this EPT21 to be cap coupled in either

single−ended or differential input mode. When single−ended cap

coupled, VBB output is tied to the D input and D is driven for a

non−inverting buffer, or VBB output is tied to the D input and D is

driven for an inverting buffer. When cap coupled differentially, VBB

output is connected through a resistor to each input pin. If used, the

VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For

additional information see AND8020/D. For a single−ended direct

connection use an external voltage reference source such as a resistor

divider. Do not use VBB for a single−ended direct connection or port to

another device.

Features

•1.4 ns Typical Propagation Delay

•Maximum Frequency > 275 MHz Typical

•LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs

•24 mA TTL outputs

•Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V

•The 100 Series Contains Temperature Compensation

•VBB Output

•Pb−Free Packages are Available

MARKING

DIAGRAMS*

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

KA21

ALYWG

SO−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

KPT21

ALYW

DFN8

MN SUFFIX

CASE 506AA

(Note: Microdot may be in either location)

3RMG

MC100EPT21

http://onsemi.com

GND

VCC

Figure 1. Logic Diagram and 8−Lead Pinout (Top View)

NCD

VBB

LVTTL

LVPECL

Table 1. PIN DESCRIPTION

D*, D*Differential LVPECL/LVDS/CML Input

FUNCTION

LVTTL/LVCMOS Output

VCC

VBB Output Reference Voltage

Positive Supply

GND Ground

NC No Connect

* Pin will default to 1/2 of VCC when left open.

EP (DFN8 only) Thermal exposed pad must be

connected to a sufficient thermal conduit. Elec-

trically connect to the most negative supply

(GND) or leave unconnected, floating open.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor D 50 kW

Internal Input Pullup Resistor D, D 50 kW

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 1.5 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 81 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Power Supply GND = 0 V 3.8 V

VIN PECL Input Voltage GND = 0 V VI  VCC 0 to 3.8 V

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−8

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SO−841 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−841 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

< 2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

MC100EPT21

http://onsemi.com

Table 4. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 4)

1.2 3.3 1.2 3.3 1.2 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current −150 −150 −150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input parameters vary 1:1 with VCC.

4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the

differential input signal.

Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C

Symbol Characteristic Condition Min Typ Max Unit

VOH Output HIGH Voltage IOH = −3.0 mA 2.4 V

VOL Output LOW Voltage IOL = 24 mA 0.5 V

ICCH Power Supply Current Outputs set to HIGH 5 17 25 mA

ICCL Power Supply Current Outputs set to LOW 8 21 30 mA

IOS Output Short Circuit Current −130 −80 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency

(Figure 2) 275 350 275 350 275 350

MHz

tPLH,

tPHL

Propagation Delay to

Output Differential

800

1200

1400

2050

1800

800

1200

1400

2250

1800

900

1100

1600

1300

2950

1900

tSKEW Duty Cycle Skew (Note 6) 45 50 55 45 50 55 45 50 55 %

tSKPP Part−to−Part Skew (Note 6) 500 500 500 ps

tJITTER Random Clock Jitter (RMS) 3.5 5 3.5 5 3.5 5 ps

VPP Input Voltage Swing

(Differential Configuration)

150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times

(0.8V − 2.0V) Q, Q 250 600 900 250 600 900 250 600 900

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to FIgure 3.

6. Skews are measured between outputs under identical transitions. Duty cycle skew is measured between differential outputs using the

deviations of the sum Tpw− and Tpw+.

MC100EPT21

http://onsemi.com

Figure 2. Fmax

500

1000

1500

2000

2500

3000

0 50 100 150 200 250 300 350 400 450 500 550 600

FREQUENCY (MHz)

VOH

VOL  0.5 V

VOUTpp (mV)

Figure 3. TTL Output Loading Used For Device Evaluation

CHARACTERISTIC TEST

CL*R

AC TEST LOAD

GND

*CL includes

fixture

capacitance

APPLICATION

TTL RECEIVER

MC100EPT21

http://onsemi.com

ORDERING INFORMATION

Device Package Shipping†

MC100EPT21D SOIC−898 Units / Rail

MC100EPT21DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100EPT21DR2 SOIC−82500 / Tape & Reel

MC100EPT21DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT21DT TSSOP−8100 Units / Rail

MC100EPT21DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100EPT21DTR2 TSSOP−82500 / Tape & Reel

MC100EPT21DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT21MNR4 DFN8 1000 / Tape & Reel

MC100EPT21MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100EPT21

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC100EPT21

http://onsemi.com

PACKAGE DIMENSIONS

TSSOP−8

DT SUFFIX

CASE 948R−02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC100EPT21

http://onsemi.com

PACKAGE DIMENSIONS

DFN8 2x2, 0.5P

CASE 506AA−01

ISSUE E

ÇÇÇ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

C0.10

PIN ONE

REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

NOTE 4 A1 SEATING

PLANE

e/2

NOTE 3

0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

L0.25 0.35

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.30

0.50

DIMENSIONS: MILLIMETERS

0.30 PITCH

PACKAGE

OUTLINE

RECOMMENDED

DETAIL A

OPTIONAL

CONSTRUCTIONS

ÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTION

DETAIL B

DETAIL A

L1 −−− 0.10

0.30 REF

0.90

1.30

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC100EPT21/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative