PCA9655EDTR2G - ON Semiconductor L.L.C.

May, 2012 − Rev. 1

1Publication Order Number:

PCA9655E/D

PCA9655E

Remote 16-bit I/O Expander

for I2C Bus with Interrupt

The PCA9655E provides 16 bits of General Purpose parallel Input /

Output (GPIO) expansion through the I2C−bus / SMBus.

The PCA9655E consists of two 8−bit Configuration (Input or

Output selection); Input, Output and Polarity Inversion (active−HIGH

or active−LOW operation) registers. At power on, all I/Os default to

inputs. Each I/O may be configured as either input or output by writing

to its corresponding I/O configuration bit. The data for each Input or

Output is kept in its corresponding Input or Output register. The

Polarity Inversion register may be used to invert the polarity of the

read register. All registers can be read by the system master.

The PCA9655E provides an open−drain interrupt output which is

activated when any input state differs from its corresponding input

port register state. The interrupt output is used to indicate to the system

master that an input state has changed. The power−on reset sets the

registers to their default values and initializes the device state

machine.

Three hardware pins (AD0, AD1, AD2) are used to configure the

I2C−bus slave address of the device. Up to 64 devices are allowed to

share the same I2C−bus / SMBus.

Features

•VDD Operating Range: 1.65 V to 5.5 V

•SDA Sink Capability: 30 mA

•5.5 V Tolerant I/Os

•Polarity Inversion Register

•Active LOW Interrupt Output

•Low Standby Current

•Noise Filter on SCL/SDA Inputs

•No Glitch on Power−up

•Internal Power−on Reset

•64 Programmable Slave Addresses Using Three Address Pins

•16 I/O Pins Which Default to 16 Inputs

•I2C SCL Clock Frequencies Supported:

Standard Mode: 100 kHz

Fast Mode: 400 kHz

Fast Mode +: 1 MHz

•ESD Performance: 2000 V Human Body Model,

200 V Machine Model

•These are Pb−Free Devices

SOIC−24

DW SUFFIX

CASE 751E

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

http://onsemi.com

TSSOP−24

DT SUFFIX

CASE 948H

WQFN24

MT SUFFIX

CASE 485BG

PCA

9655E

ALYWG

PCA96

55EG

AWLYYWW

PCA9655E

AWLYYWWG

XXXX = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

PCA9655E

http://onsemi.com

BLOCK DIAGRAM

Remark: All I/Os are set as inputs at reset.

Figure 1. Block Diagram

Figure 2. Simplified Schematic of I/Os

PCA9655E

POWER−ON

RESET

I2C−BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

IO0_0

VSS

8−bit

write pulse

read pulse

IO0_2

IO0_1

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

INPUT/

OUTPUT

PORTS

IO1_0

8−bit

write pulse

read pulse

IO1_2

IO1_1

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

INT

AD1

AD0

AD2

LP filter

VDD

At power−on reset, all registers return to default values.

VDD

I/O pin

output port

configuration

CK Q

data from

shift register

write

configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

data from

shift register

VSS

to INT

100 kW

PCA9655E

http://onsemi.com

PIN ASSIGNMENT

Figure 3. SOIC24 / TSSOP24 Figure 4. WQFN24

(The exposed thermal pad at the bottom

is not connected to internal circuitry)

VINT DD

SDAAD1

SCLAD2

AD0IO0_0

IO1_7IO0_1

IO1_6IO0_2

IO1_5IO0_3

IO1_4IO0_4

IO1_3IO0_5

IO1_2IO0_6

IO1_1IO0_7

VSS IO1_0

PCA9655E

Transparent top view

IO1_3

IO1_4

IO0_3

IO0_2

IO0_1

AD0IO0_0

IO0_6

IO0_7

VSS

IO1_0

IO1_1

IO1_2

AD2

AD1

INT

VDD

SDA

SCL

terminal 1

index area

6 13

5 14

4 15

3 16

2 17

1 18

PCA9655E

IO0_5

IO0_4

IO1_5

IO1_6

IO1_7

Table 1. PIN DESCRIPTIONS

Symbol

Description

SOIC24, TSSOP24 WQFN24

INT 1 22 Interrupt Output (active−LOW)

AD1 2 23 Address Input 1

AD2 3 24 Address Input 2

IO0_0 4 1 Port 0 I/O 0

IO0_1 5 2 Port 0 I/O 1

IO0_2 6 3 Port 0 I/O 2

IO0_3 7 4 Port 0 I/O 3

IO0_4 9 5 Port 0 I/O 4

IO0_5 9 6 Port 0 I/O 5

IO0_6 10 7 Port 0 I/O 6

IO0_7 11 9Port 0 I/O 7

VSS 12 9 Supply Ground

IO1_0 13 10 Port 1 I/O 0

IO1_1 14 11 Port 1 I/O 1

IO1_2 15 12 Port 1 I/O 2

IO1_3 16 13 Port 1 I/O 3

IO1_4 17 14 Port 1 I/O 4

IO1_5 18 15 Port 1 I/O 5

IO1_6 19 16 Port 1 I/O 6

IO1_7 20 17 Port 1 I/O 7

AD0 21 18 Address Input 0

SCL 22 19 Serial Clock Line

SDA 23 20 Serial Data Line

VDD 24 21 Supply Voltage

PCA9655E

http://onsemi.com

Table 2. MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD DC Supply Voltage −0.5 to +7.0 V

VI/O Input / Output Pin Voltage −0.5 to +7.0 V

IIInput Current $20 mA

IOOutput Current $50 mA

IDD DC Supply Current $100 mA

IGND DC Ground Current $600 mA

PTOT Total Power Dissipation 600 mW

POUT Power Dissipation per Output 200 mW

TSTG Storage Temperature Range −65 to +150 °C

TLLead Temperature, 1 mm from Case for 10 Seconds 260 °C

TJJunction Temperature Under Bias 150 °C

qJA Thermal Resistance (Note 1) SOIC−24

TSSOP−24

WQFN24

°C/W

MSL Moisture Sensitivity Level 1

FRFlammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

VESD ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

> 2000

> 200

ILATCHUP Latchup Performance Above VDD and Below GND at 125°C (Note 4) $300 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.

2. Tested to EIA / JESD22−A114−A.

3. Tested to EIA / JESD22−A115−A.

4. Tested to EIA / JESD78.

Table 3. RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VDD Positive DC Supply Voltage 1.65 5.5 V

VI/O Switch Input / Output Voltage 0 5.5 V

TAOperating Free−Air Temperature −55 +125 °C

Dt / DVInput Transition Rise or Fall Rate 0 5 nS/V

PCA9655E

http://onsemi.com

Table 4. DC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V, unless otherwise specified.

Symbol Parameter Conditions

TA = −555C to +1255C

Unit

Min Typ Max

SUPPLIES

ISTB Standby Current Standby mode; no load;

VI = 0 V; fSCL = 0 Hz; I/O = inputs

VI = VDD; fSCL = 0 Hz; I/O = inputs

1.1

0.25

1.5

VPOR Power−On Reset Voltage

(Note 5)

1.5 1.65 V

INPUT SCL; Input / Output SDA

VIH High−Level Input Voltage 0.7 x VDD V

VIL Low−Level Input Voltage 0.3 x VDD V

IOL Low−Level Output Current VOL = 0.4 V; VDD < 2.3 V 10 mA

VDD w 2.3 V 20

ILLeakage Current VI = VDD or 0 V $1mA

CIInput Capacitance VI = 0 V 4.6 6 pF

I/Os

VIH High−Level Input Voltage 0.7 x VDD V

VIL Low−Level Input Voltage 0.3 x VDD V

IOL Low−Level Output Current

(Note 6)

VOL = 0.5 V; VDD = 1.65 V

VOL = 0.5 V; VDD = 2.3 V

VOL = 0.5 V; VDD = 3.0 V

VOL = 0.5 V; VDD = 4.5 V

IOL(tot) Total Low−Level Output Current

(Note 6)

VOL = 0.5 V; VDD = 4.5 V 400 mA

VOH High−Level Output Voltage IOH = −3 mA; VDD = 1.65 V

IOH = −4 mA; VDD = 1.65 V

IOH = −8 mA; VDD = 2.3 V

IOH = −10 mA; VDD = 2.3 V

IOH = −8 mA; VDD = 3.0 V

IOH = −10 mA; VDD = 3.0 V

IOH = −8 mA; VDD = 4.5 V

IOH = −10 mA; VDD = 4.5 V

1.2

1.1

1.8

1.7

2.6

2.5

4.1

4.0

ILH Input Leakage Current VDD = 5.5 V; VI = VDD 1mA

ILL Input Leakage Current VDD = 5.5 V; VI = 0 V −100 mA

CI/O Input / Output Capacitance

(Note 7)

5.0 6.0 pF

INTERRUPT (INT)

IOL Low−Level Output Current VOL = 0.4 V 6.0 mA

COOutput Capacitance 5.0 5.5 pF

INPUTS AD0, AD1, AD2

VIH High−Level Input Voltage 0.7 x VDD V

VIL Low−Level Input Voltage 0.3 x VDD V

ILLeakage Current VI = VDD or 0 V $1mA

CIInput Capacitance 4.5 5.0 pF

5. The power−on reset circuit resets the I2C bus logic with VDD < VPOR and set all I/Os to logic 1 upon power−up. Thereafter, VDD must be lower

than 0.2 V to reset the part.

6. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal bussing limits.

7. The value is not tested, but verified on sampling basis.

PCA9655E

http://onsemi.com

Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V; TA = −55°C to +125°C, unless otherwise specified.

Symbol Parameter

Standard

Mode Fast Mode Fast Mode +

Unit

Min Max Min Max Min Max

fSCL SCL Clock Frequency 0 0.1 0 0.4 0 1.0 MHz

tBUF Bus−Free Time between a STOP and START

Condition

4.7 1.3 0.5 ms

tHD:STA Hold Time (Repeated) START Condition 4.0 0.6 0.26 ms

tSU:STA Setup Time for a Repeated START Condition 4.7 0.6 0.26 ms

tSU:STO Setup Time for STOP Condition 4.0 0.6 0.26 ms

tHD:DAT Data Hold Time 0 0 0 ns

tVD:ACK Data Valid Acknowledge Time (Note 8) 0.3 3.45 0.1 0.9 0.05 0.45 ms

tVD:DAT Data Valid Time (Note 9) 300 50 50 450 ns

tSU:DAT Data Setup Time 250 100 50 ns

tLOW LOW Period of SCL 4.7 1.3 0.5 ms

tHIGH HIGH Period of SCL 4.0 0.6 0.26 ms

tfFall Time of SDA and SCL (Notes 11 and 12) 300 20 + 0.1Cb

(Note 10)

300 120 ns

trRise Time of SDA and SCL 1000 20 + 0.1Cb

(Note 10)

300 120 ns

tSP Pulse Width of Spikes Suppressed by Input Filter

(Note 13)

50 50 50 ns

PORT TIMING: CL v 100 pF (See Figures 6, 9 and 10)

tV(Q) Data Output Valid Time (VDD = 4.5 V to 5.5 V)

(VDD = 2.3 V to 4.5 V)

(VDD = 1.65 V to 2.3 V)

200

350

550

200

350

550

200

350

550

tSU(D) Data Input Setup Time 100 100 100 ns

tH(D) Data Input Hold Time 1 1 1 ms

INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10)

tV(INT_N) Data Valid Time 4 4 4 ms

tRST(INT_N) Reset Delay Time 4 4 4 ms

8. tVD:ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW.

9. tVD:DAT = minimum time for SDA data out to be valid following SCL LOW.

10.Cb = total capacitance of one bus line in pF.

11. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge

the undefined region SCL’s falling edge.

12. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

the maximum specified tf.

13.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

PCA9655E

http://onsemi.com

Device Address

Before the bus master can access a slave device, it must

send the address of the slave it is accessing and the operation

it wants to perform (read or write) following a START

condition. The slave address of the PCA9655E is shown in

Figure 5. Address pins AD2, AD1, and AD0 choose 1 of 64

slave addresses. To conserve power, no internal pull−up

resistors are provided on AD2, AD1, and AD0.

A logic 1 on the last bit of the first byte selects a read

operation while a logic 0 selects a write operation.

Figure 5. PCA9655E device Address

R/WA6 A5 A4 A3 A2 A1 A0

programmable

slave address

Table 6. PCA9655E ADDRESS MAP

Address Input Slave Address

AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 HEX

GND SCL GND 0 0 1 0 0 0 0 20h

GND SCL VDD 0 0 1 0 0 0 1 22h

GND SDA GND 0 0 1 0 0 1 0 24h

GND SDA VDD 0 0 1 0 0 1 1 26h

VDD SCL GND 0 0 1 0 1 0 0 28h

VDD SCL VDD 0 0 1 0 1 0 1 2Ah

VDD SDA GND 0 0 1 0 1 1 0 2Ch

VDD SDA VDD 0 0 1 0 1 1 1 2Eh

GND SCL SCL 0 0 1 1 0 0 0 30h

GND SCL SDA 0 0 1 1 0 0 1 32h

GND SDA SCL 0 0 1 1 0 1 0 34h

GND SDA SDA 0 0 1 1 0 1 1 36h

VDD SCL SCL 0 0 1 1 1 0 0 38h

VDD SCL SDA 0 0 1 1 1 0 1 3Ah

VDD SDA SCL 0 0 1 1 1 1 0 3Ch

VDD SDA SDA 0 0 1 1 1 1 1 3Eh

GND GND GND 0 1 0 0 0 0 0 40h

GND GND VDD 0 1 0 0 0 0 1 42h

GND VDD GND 0 1 0 0 0 1 0 44h

GND VDD VDD 0 1 0 0 0 1 1 46h

VDD GND GND 0 1 0 0 1 0 0 48h

VDD GND VDD 0 1 0 0 1 0 1 4Ah

VDD VDD GND 0 1 0 0 1 1 0 4Ch

VDD VDD VDD 0 1 0 0 1 1 1 4Eh

GND GND SCL 0 1 0 1 0 0 0 50h

GND GND SDA 0 1 0 1 0 0 1 52h

GND VDD SCL 0 1 0 1 0 1 0 54h

GND VDD SDA 0 1 0 1 0 1 1 56h

VDD GND SCL 0 1 0 1 1 0 0 58h

VDD GND SDA 0 1 0 1 1 0 1 5Ah

VDD VDD SCL 0 1 0 1 1 1 0 5Ch

VDD VDD SDA 0 1 0 1 1 1 1 5Eh

PCA9655E

http://onsemi.com

Table 6. PCA9655E ADDRESS MAP

Slave AddressAddress Input

HEXA0A1A2A3A4A5A6AD0AD1AD2

SCL SCL GND 1 0 1 0 0 0 0 A0h

SCL SCL VDD 1 0 1 0 0 0 1 A2h

SCL SDA GND 1 0 1 0 0 1 0 A4h

SCL SDA VDD 1 0 1 0 0 1 1 A6h

SDA SCL GND 1 0 1 0 1 0 0 A8h

SDA SCL VDD 1 0 1 0 1 0 1 AAh

SDA SDA GND 1 0 1 0 1 1 0 ACh

SDA SDA VDD 1 0 1 0 1 1 1 AEh

SCL SCL SCL 1 0 1 1 0 0 0 B0h

SCL SCL SDA 1 0 1 1 0 0 1 B2h

SCL SDA SCL 1 0 1 1 0 1 0 B4h

SCL SDA SDA 1 0 1 1 0 1 1 B6h

SDA SCL SCL 1 0 1 1 1 0 0 B8h

SDA SCL SDA 1 0 1 1 1 0 1 BAh

SDA SDA SCL 1 0 1 1 1 1 0 BCh

SDA SDA SDA 1 0 1 1 1 1 1 BEh

SCL GND GND 1 1 0 0 0 0 0 C0h

SCL GND VDD 1 1 0 0 0 0 1 C2h

SCL VDD GND 1 1 0 0 0 1 0 C4h

SCL VDD VDD 1 1 0 0 0 1 1 C6h

SDA GND GND 1 1 0 0 1 0 0 C8h

SDA GND VDD 1 1 0 0 1 0 1 CAh

SDA VDD GND 1 1 0 0 1 1 0 CCh

SDA VDD VDD 1 1 0 0 1 1 1 CEh

SCL GND SCL 1 1 1 0 0 0 0 E0h

SCL GND SDA 1 1 1 0 0 0 1 E2h

SCL VDD SCL 1 1 1 0 0 1 0 E4h

SCL VDD SDA 1 1 1 0 0 1 1 E6h

SDA GND SCL 1 1 1 0 1 0 0 E8h

SDA GND SDA 1 1 1 0 1 0 1 EAh

SDA VDD SCL 1 1 1 0 1 1 0 ECh

SDA VDD SDA 1 1 1 0 1 1 1 EEh

PCA9655E

http://onsemi.com

REGISTERS

Command Byte

During a write transmission, the address byte is followed

by the command byte. The command byte determines which

of the following registers will be written or read.

Table 7. COMMAND BYTE

COMMAND REGISTER

0Input Port 0

1Input Port 1

2Output Port 0

3Output Port 1

4Polarity Inversion Port 0

5Polarity Inversion Port 1

6Configuration Port 0

7Configuration Port 1

Registers 0 and 1: Input Port Registers

These registers are input−only. They reflect the incoming

logic levels of the pins, regardless of whether the pin is

defined as an input or an output by Registers 6 or 7. Writes

to these registers have no effect.

The externally−applied logic level determines the default

value ‘X’.

Table 8. INPUT PORT 0 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0

Default X X X X X X X X

Table 9. INPUT PORT 1 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0

Default X X X X X X X X

Registers 2 and 3: Output Port Registers

These registers are output−only. They reflect the outgoing

logic levels of the pins defined as outputs by Registers 6 and

7. Bit values in these registers have no effect on pins defined

as inputs. In turn, reads from these registers reflect the values

that are in the flip−flops controlling the output selection, not

the actual pin values.

Table 10. OUTPUT PORT 0 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0

Default 11111111

Table 11. OUTPUT PORT 1 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0

Default 11111111

PCA9655E

http://onsemi.com

Registers 4 and 5: Polarity Inversion Registers

These registers allow the polarity of the data in the input

port registers to be inverted. The input port data polarity will

be inverted when its corresponding bit in these registers is

set (written with ‘1’), and retained when the bit is cleared

(written with a ‘0’).

Table 12. POLARITY INVERSION PORT 0 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

Default 00000000

Table 13. POLARITY INVERSION PORT 1 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

Default 00000000

Registers 6 and 7: Configuration Registers

The I/O pin directions are configured through the

configuration registers. When a bit in the configuration

registers is set (written with ‘1’), the bit’s corresponding port

pin is enabled as an input with the output driver in

high−impedance. When a bit is cleared (written with ‘0’),

the corresponding port pin is enabled as an output. Note that

there is a high value resistor tied to VDD at each pin. At reset,

the device’s ports are inputs with a pull−up to VDD.

Table 14. CONFIGURATION PORT 0 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

Default 11111111

Table 15. CONFIGURATION PORT 1 REGISTER

Bit 7 6 5 4 3 2 1 0

Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

Default 11111111

Power−on Reset

Upon application of power, an internal Power−On Reset

(POR) holds the PCA9655E in a reset condition while VDD

is ramping up. When VDD has reached VPOR, the reset

condition is released and the PCA9655E registers and

SMBus state machine will initialize to their default states.

The reset is typically completed by the POR and the part

enabled by the time the power supply is above VPOR.

However, when doing a power reset cycle, it is necessary to

lower the power supply below 0.2 V, and then restored to the

operating voltage.

I/O Port (see Figure 2)

When an I/O pin is configured as an input, FETs Q1 and

Q2 are off, creating a high−impedance input with a weak

pull−up (100 kW typ) to VDD. The input voltage may be

raised above VDD to a maximum of 5.5 V.

When the I/O pin is configured as an output, then either Q1

or Q2 is enabled, depending on the state of the Output Port

applied to an I/O configured as an output because of the

low−impedance path that exists between the pin and either

VDD or VSS.

PCA9655E

http://onsemi.com

BUS TRANSACTIONS

Writing to the Port Registers

To transmit data to the PCA9655E, the bus master must

first send the device address with the least significant bit set

to logic 0 (see Figure 5 “PCA9655E device address”). The

command byte is sent after the address and determines

which registers will receive the data following the command

byte.

There are eight registers within the PCA9655E. These

registers are configured to operate as four register pairs:

Input Ports, Output Ports, Polarity Inversion Ports, and

Configuration Ports. Data bytes are sent alternately to each

if one byte is sent to Output Port 1 (register 3), then the next

byte will be stored in Output Port 0 (register 2). There is no

limitation on the number of data bytes sent in one write

transmission. In this way, each 8−bit register may be updated

independently of the other registers.

Figure 6. Write to Output Port Registers

A2 A1 A0 0 AS A6

START condition R/W acknowledge

from slave

SCL

SDA A

write to port

data out

from port 0

tv(Q)

987654321

command byte data to port 0

DATA 0

slave address

STOP

condition

0.00.7

acknowledge

from slave acknowledge

from slave

data to port 1

DATA 1 1.01.7 A

data out

from port 1

tv(Q)

DATA VALID

A5 A4 A3 0 0 0 0 0 1 0

Figure 7. Write to Configuration Registers

A2 A1 A0 0 AS A6

START condition R/W acknowledge

from slave

SCL

SDA AP

98765432

command byte

data to register

DATA 0

slave address

STOP

condition

LSB

MSB

acknowledge

from slave

acknowledge

from slave

data to register

DATA 1

LSB

MSB

AA5 A4 A3 0 0 0 1 1 00

Reading the Port Registers

To read data from the PCA9655E, the bus master must

first send the PCA9655E address with the least significant

bit set to logic 0 (see Figure 5 “PCA9655E device address”).

The command byte is sent after the address and determines

which register will be accessed.

After a restart, the device address must be sent again, but

this time, the least significant bit is set to logic 1. Data from

the register defined by the command byte will then be sent

by the PCA9655E (see Figures 8, 9 and 10). Data is clocked

into the register on the falling edge of the acknowledge clock

pulse. After the first byte is read, additional bytes may be

read but with data alternately coming from each register in

the pair. For example, if you read Input Port 1, then the next

byte read would be Input Port 0. There is no limitation on the

number of data bytes received in one read transmission but

the bus master must not acknowledge the data for the final

byte received.

PCA9655E

http://onsemi.com

Figure 8. Read from Register

Remark: Transfer can be stopped at any time by a STOP condition.

START condition R/W

acknowledge

from slave

acknowledge

from slave

SDA

acknowledge

from master

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

(cont.) A2 A1 A0 1AA6

R/W

acknowledge

from slave

slave address

at this moment master−transmitter becomes master−receiver

and slave−receiver becomes slave−transmitter

no acknowledge

from master

COMMAND BYTE

A2 A1 A0A6 0

data from lower or

upper byte of register

LSB

MSB

DATA (last byte)

data from upper or

lower byte of register

LSB

MSB

A5 A4 A3

Figure 9. Read from Input Port Register, Scenario 1

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).

A2 A1 A0 1 AS A6

START condition R/W

acknowledge

from slave

SCL

SDA A

read from port 0

98765432

I0.xslave address

STOP condition

acknowledge

from master

I1.x

acknowledge

from master

I0.x

acknowledge

from master

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

tv(INT_N) trst(INT_N)

A5A4A3 654 3210 654 3210 654 3210 654 3210

PCA9655E

http://onsemi.com

Figure 10. Read from Input Port Register, Scenario 2

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).

A2 A1 A0 1 AS A6

START condition

R/W

acknowledge

from slave

SCL

SDA A

read from port 0

98765432

I0.xslave address STOP condition

acknowledge

from master

I1.x

acknowledge

from master

I0.x

acknowledge

from master

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

tv(INT_N) trst(INT_N)

21ATAD30ATAD01ATAD00ATAD

DATA 00 DATA 01

th(D)

DATA 02

tsu(D)

DATA 03

tsu(D)

21ATAD11ATAD01ATAD

A5A4 A3

Interrupt Output

The open−drain interrupt output is activated when an I/O

pin configured as an input changes state. The interrupt is

deactivated when the input pin returns to its previous state

or when the Input Port register is read (see Figure 9). A pin

configured as an output cannot cause an interrupt. Since

each 8−bit port is read independently, the interrupt caused by

Port 0 will not be cleared by a read of Port 1 or the other way

around.

Remark: Changing an I/O from an output to an input may

cause a false interrupt to occur if the state of the pin does not

match the contents of the Input Port register.

PCA9655E

http://onsemi.com

APPLICATION INFORMATION

Figure 11. Typical Application

Device address configured as 0100 000xb for this example.

IO0_0, IO0_2, IO0_3 configured as outputs.

IO0_1, IO0_4, IO0_5 configured as inputs.

IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.

PCA9655E

IO0_0

IO0_1

SCL

SDA

VDD

(5 V)

MASTER

CONTROLLER

INT IO0_2

VDD

AD2

AD1

AD0

VDD

GND

INT

10 kW

SUB−SYSTEM 1

(e.g., temp sensor)

IO0_3

INT

SUB−SYSTEM 2

(e.g., counter)

RESET

controlled

switch

(e.g.,7SB or FST)

VDD

ENABLE

SUB−SYSTEM 3

(e.g., alarm system)

ALARM

IO0_4

IO0_5

IO0_6

10 DIGIT

NUMERIC

KEYPAD

VSS

10 kW10 kW2 kW

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

SDA

SCL

Characteristics of the I2C−Bus

The I2C−bus is meant for 2−way, 2−line communication

between different ICs or modules. The two lines are the

serial data line (SDA) and the serial clock line (SCL). Both

lines must be connected to a positive supply via a pull−up

resistor when connected to the output stages of a device.

Data transfer may only be initiated when the bus is not busy.

Bit Transfer

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the HIGH

period of the clock pulse. Changes in the data line during the

HIGH period of the clock pulse will be interpreted as control

signals (see Figure 12).

PCA9655E

http://onsemi.com

Figure 12. Bit Transfer

data line

stable;

data valid

change

of data

allowed

SDA

SCL

START and STOP Conditions

Both data and clock lines remain HIGH when the bus is

not busy. A START condition (S) occurs when there is a

HIGH−to−LOW transition of the data line while the clock is

HIGH. A STOP condition (P) occurs when there is a

LOW−to−HIGH transition of the data line while the clock is

HIGH (see Figure 13).

Figure 13. Definition of START and STOP Conditions

SDA

SCL

STOP condition

SDA

SCL

START condition

System Configuration

A device generating a message is a ‘transmitter’; a device

receiving is the ‘receiver’. The device that controls the

message is the ‘master’ and the devices which are controlled

by the master are the ‘slaves’ (see Figure 14).

Figure 14. System Configuration

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C−BUS

MULTIPLEXER

SLAVE

Acknowledge

The number of data bytes transferred between the START

and the STOP conditions from transmitter to receiver is not

limited. Each 8−bit byte is followed by one acknowledge bit.

The acknowledge bit is a HIGH level put on the bus by the

transmitter, whereas the master generates an extra clock

pulse for the acknowledge bit.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also, a master

must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter. The

device that acknowledges has to pull down the SDA line

during the acknowledge clock pulse, such that the SDA line

is stable LOW during the HIGH period of the acknowledge

clock pulse; set−up time and hold time must be taken into

account.

A master receiver signals an end of data to the transmitter

by not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event, the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

PCA9655E

http://onsemi.com

Figure 15. Acknowledgement of the I2C Bus

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

TIMING AND TEST SETUP

Figure 16. Definition of Timing on the I2C Bus

tSP

tBUF

tHD;STA

PP S

tLOW

tHD;DAT

tHIGH tSU;DAT

tSU;STA

tHD;STA

tSU;STO

SDA

SCL

Figure 17. Test Circuitry for Switching Times

Figure 18. Load Circuit

PULSE

GENERATOR

50 pF

500 W

VDD

DUT

VDD

open

GND

50 pF

500 W

from output under test

2VDD

open

GND

500 W

RL = load resistor.

CL = load capacitance includes jig and probe capacitance.

RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.

PCA9655E

http://onsemi.com

ORDERING INFORMATION

Device Package Shipping†

PCA9655EDWR2G SOIC−24

(Pb−Free)

1000 / Tape & Reel

PCA9655EDTR2G TSSOP−24

(Pb−Free)

2500 / Tape & Reel

PCA9655EMTTXG WQFN24

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

PCA9655E

http://onsemi.com

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

−A−

−B−P12X

D24X

1324

0.010 (0.25) B M

0.010 (0.25) B S

−T−

22X

SEATING

PLANE K

RX 45 _

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A15.25 15.54 0.601 0.612

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.41 0.90 0.016 0.035

G1.27 BSC 0.050 BSC

J0.23 0.32 0.009 0.013

K0.13 0.29 0.005 0.011

M0 8 0 8

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

____

SOIC−24

CASE 751E−04

ISSUE E

PCA9655E

http://onsemi.com

PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A7.70 7.90 0.303 0.311

B4.30 4.50 0.169 0.177

C--- 1.20 --- 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

24X REFK

24 LEAD TSSOP

CASE 948H

ISSUE A

PCA9655E

http://onsemi.com

PACKAGE DIMENSIONS

WQFN24 4x4, 0.5P

CASE 485BG

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

ÇÇÇÇ

C0.15

PIN ONE

REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

C0.15

C0.10

C0.08

A1 SEATING

PLANE

24X

NOTE 3

24X

0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.70 0.80

A1 0.00 0.05

b0.20 0.30

D4.00 BSC

D2 2.00 2.20

E4.00 BSC

E2 2.00 2.20

e0.50 BSC

K0.20 −−−

L0.30 0.50

24X

0.50

PITCH

4.30

0.63

4.30

DIMENSIONS: MILLIMETERS

0.30

24X

A3 0.20 REF

MOUNTING FOOTPRINT*

NOTE 4

DETAIL B

2.26

PACKAGE

OUTLINE

DETAIL A

e/2

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

L1 0.00 0.15

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PCA9655E/D

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative