NMC9314B National Semiconductor NMC9314B 1024-Bit Serial Electrically Erasable Programmable Memory General Description Features 10,000 erase/write cycles 10 year data retention The NMC9314B is a 1024-bit non-volatile, sequential E2PROM, fabricated using advanced N-channel E2PROM technology. It is an external memory with the 1024 bits of read/write memory divided into 64 registers of 16 bits each. Each register can be serially read or written by a COP400 controller, or a standard microprocessor. Written intorma- tion is stored in a floating gate cell until updated by an erase and write cycle. The NMC9314B has been designed for ap- plications requiring up to 104 erase/write cycles per regis- ter. A power-down mode is provided by CS to reduce power consumption by 75 percent. Low cost Single supply read/write/erase operations (5V + 10%) TTL compatibte 64 x 16 serial read/write memory MICROWIRE compatible serial 1/O Simple interfacing Low standby power Non-volatile erase and write Reliable floating gate technology Self-timed programming cycle Device status signal during programming Block and Connection Diagrams R/W AMPS DATA REGISTER {17 BITS) INSTRUCTION REGISTEA (9 BITS) INSTRUCTION DECODE, CONTROL, AND CLOCK GENERATOR TL/D/9144-1 Dual-In-Line Package (N) cst UY s}vee SKed 2 7 NC i43 6 -ne poj 4 5 pGND TL/D/9144-2 Top View Order Number NMC9314N See NS Package NOSE Pin Names cs Chip Select SK Serial Data Clock DI Serial Data input DO Serial Data Output Voc Power Supply GND Ground NC Not Connected 2-46Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Ambient Storage Temp. 66C to + 125C Lead Temperature (Soldering, 10 seconds) 300C Office/Distributers for availability and specifications. ESD Rating > 2000V Voltage Relative to GND +6V to 0.3V Ambient Operating Temperature 0OC to + 70C DC and AC Electrical Characteristics oc<1,<70C, Voc=5V + 10% unless specified Symbol Parameter Conditions Min Max Units Voc Operating Voltage 45 5.5 Vv | Operating Current Veco =5.5V, CS=1, SK=1 17 mA oct Erase/Write Operating Current Vec=5.5V 17 mA loce Standby Current Voc =5.5V, CS=0 5 mA Input Voltage Levels Vit -0.1 0.8 v Vin 2.0 Vecot0.5 Vv Output Voltage Levels Voi lop=2.1 mA 0.4 Vv Vou lon= 400 pA 2.4 V Is Input Leakage Current Vin = 5.5V 10 pA ILo Output Leakage Current VouTt= 5.5V, CS=0 10 pA SK Frequency 0 200 kHz tskH SK High Time (Note 2) 3 ps tsKL SK Low Time (Note 2) 2 ps Inputs toss cs 0.2 ps icsH 0 -* ps tois DI 0.4 ps tolH 0.4 ps Output CL= 100 pF toatl DO Vo_=0.8V, VoH=2.0V 2 BS tpg Vit = 0.45V, Vip =2.40V 2 ps tesw Self-Timed Program Cycle 15 ms tos Min CS Low Time (Note 3} 1 ps tsy Rising Edge of CS to Status Valid CL= 100 pF 1 ps ton, ty Falling Edge of CS to DO TRI-STATE 0.4 ps Note 1: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devica reliability. Note 2: The SK frequency spac. specifies a minimum SK clock period of 5 44s, therefore in an SK clock cycle tsk} + tsq_ must be greater than or equal to 5 us. 6.g., if tsxk_ = 2 2s then the minimum tsk} = 3 Ss in order to meet the SK frequency specification. Note 3: CS must be brought low for a minimum of 1 4s (icg) between consecutive instruction cycles. Instruction Set for NMC9314B instruction | SB | Op Code Address Data Comments READ 1 10 A5SA4A3A2A1A0 Read register ASA4A3A2A1 A0 WRITE 1 01 A5A4A3A2A1A0 | D15-D0 | Write register ASA4A3A2A1A0 ERASE 1 11 A5A4A3A2A1A0 Erase register ASA4A3A2A1A0 EWEN 1 00 1 100K Erase/write enable EWDS 1 00 O0wox Erase/write disable ERAL 1 00 1 Ox00xx Erase ali registers WRAL 1 00 OFKXxx D15-D0 | Write all registers NMC93146 has 7 instructions as shown. Note that the MSB of any given instruction is a 1 and is viewed as a start bit in the interface sequence. The next 8 bits carry the op code and the 6-bit address for 1 of 64, 16-bit registers. 2-49 rl 6OWNNMC9314B Functional Description The NMC9314B is a smail peripheral memory intended for use with COPS controllers and other nonvolatile memory applications. Its organization is sixty-four registers and each register is sixteen bits wide. The input and output pins are controlled by separate serial formats. Seven 9-bit instruc- tions can be executed. The instruction format has a logical 1 as a start bit, two bits as an op code, and six bits of address. The programming cycle is self-timed, with the data out (DO) pin indicating the ready/busy status of the chip. The on-chip programming voltage generator allows the user to use a single power supply (Vcc). It only generates high voltage during the programming modes (write, erase, chip erase, chip write), The DO pin is valid as data out during the read mode, and if initiated, as a ready/busy status indicator during a programming cycle. During all other modes the DO pin is in TRI-STATE, eliminating bus contention. READ The read instruction is the only instruction which outputs serial data on the DO pin. After a read instruction is re- ceived, the instruction and address are decoded, followed by data transfer from the memory register into a 16-bit seri- al-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. ERASE/WRITE ENABLE AND DISABLE When Vcc is applied to the part it powers up in the pregram- ming disable (EWDS) state, programming must be preceded by a programming enable (EWEN) instruction. Programming remains enabled until a programming disable (EWDS) in- struction is executed or Vcc is removed from the part. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruc- tion is independent of both EWEN and EWDS instructions. ERASE (Note 4) Like most E2PROMs, the register must first be erased (all bits set to logical 1) before the register can be written (cer- tain bits set to logical 0). After an erase instruction is input, CS is dropped low. This falling edge of CS determines Timing Diagrams the start of the self-timed programming cycle. If CS is brought high subsequently (after observing the tcs specifi- cation), the DO pin will indicate the ready/busy status of the chip. The DO pin will go low if the chip is still programming. The DO pin will go high when all bits of the register at the address specified in the instruction have been set to a logi- cal 1. The part is now ready for the next instruction se- quence. WRITE (Note 4) The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data (DO) is put on the data in (DI) pin CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. Like all programming modes, DO indicates the ready/busy status of the chip if CS is brought high after a minimum of 1 1S (tes). DO= logical 0 indicates that programming is still in prog- ress. DO= logical 1 indicates that the register at the ad- dress specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. The register to be written into must have been previously erased. CHIP ERASE (Note 4) Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in the memory ar- ray have each bit set to a logical 1. Each register is then ready for a write instruction. The chip erase cycle is identical to the erase cycle except for the different op code. CHIP WRITE (Note 4) All registers must be erased before a chip write operation. The chip write cycle is identical to the write cycie except for the different op code. All registers are simultaneously writ- ten with the data pattern specified in the instruction. Note 4: During a programming mode (write, erase, chip erase, chip write), SK clock is only needed while the actual instruction, i.e., start bit, op code, address and data, is being input. It can remain deactivated during the self- timed programming cycle and status check. Synchronous Data Timing Win f cs a Ss > on Vor < 00 VN SY You ___. *This is the minimum SK period. TL/D/9144-3 2-50NMC9314B Timing Diagrams (Continued) v-PPl6s/OIL bo= Tavsid b= 71eWN scams = / $9 %, 00 = a 7 TAVIS TH oa XXX KEKE KOS NLS suis fs JTLOLOLALLO LLLP Leper yy alVLS-1L Hy CK = XXX Kyo ama r DODO sons Jr AFLAC LLL LeeLee rrr Buywy | uoyonsjsul SIWLS-1UL Hh) Hay aU 2-51S-PrL6/O/IL SIVAS-HL Timing Diagrams (Continued) OX RIZE | * o0\tS ia Wom Tw AGONWLS SNLWLS 93H we / $3 PLU LLL LILLY LLY LL = as SIVLS-TL Aaval asna _.| L_ BAVIS-1HL oa Ima Ay \ av tv w Xx sv Kt l L ia XO XX / - AGONVLS SNLVLS 93H9 L f $9 Burw, ucyonsysul GP LE6OWN 2-52