SLLZ015C − DECEMBER 2002 − REVISED MARCH 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SILICON
ERRATA ID PROBLEM DESCRIPTION RESOLUTION / WORK-AROUNDS
3. Missing subaction
gap issue When nonroot 1394b nodes request transactions and do not receive an
Ack (missing-Ack timeout occurs) the 1394b link layer is only sent an
arbitration reset gap indicator rather than a both the Subaction gap and
arbitration reset gap indicators. Some LLC hang if the Subaction gap
indicator is not received.
Instruct the LLC to use 1394a
mode for the PHY-Link interface.
4. Cycle start
concatenation issue When the PHY-Link interface is in the 1394a mode (BMODE terminal is
logic 0) cycle start concatenation only works at S100. Furthermore, only
one Isoch packet per Iso interval is allowed unless all Isoch packets are
S100.
Configure the LLC to only transmit
one Isoch packet per Iso interval
and do one (or both) of the
following:
A. Disable cycle-start packet
concatenation in the LLC.
B. Clear the EAA and EMC CFR
register bits in the TSB81BA3.
These bits are cleared by chip
reset (default).
5. 1394b Loop
Prevention algorithm
may cause bus resets
in early production
devices
Symptom
The TSB81BA3 may cause bus resets during its 1394b mode loop
prevention algorithm. This is a result of a Loop-test packet (LTP) collision
with a cycle start packet or other 1394b subaction transaction
completion, causing slow loop detection processing. Although the bus
resets will eventually stop, multiple bus resets may occur.
Occurrences
This issue only occurs in early production devices. These devices are
identified in software by reading the Product_ID from the TSB81BA3
vendor identification registers. Problem devices have a Product_ID of
83_13_01h. Good devices, with a Product_ID of 83_13_04h (or greater)
do not have this issue.
Software must tolerate multiple bus
resets spaced closely together.
Software must wait until the bus
reset process is complete (receipt
of a subaction gap status) prior to
enabling cycle master processing
or queuing packet requests.
6. Legacy node
maximum speed
incorrectly reported in
early production
devices
Symptom
The TSB81BA3 incorrectly calculates the Max Legacy SPD value (stored
in the base register configuration area) if another device on the bus has
four or more ports and is a lower node number.
Occurrences
This issue only occurs in early production devices. These devices are
identified in software by reading the Product_ID from the TSB81BA3
vendor identification registers. Problem devices (early production) have a
Product_ID of 83_13_01h. Good devices, with a Product_ID of
83_13_04h (or greater) do not have this issue.
The Max_legacy_path_speed field
is a new CFR addition in the IEEE
Std 1394b-2002.
It is strongly recommended that
software not utilize this register
field but rather determine node
speeds by a try-and-see method. In
this method legacy packets are
sent at the fastest speed and then
at successively slower speeds until
success or failure is determined.
7. Disappearing IDLE
in a Beta system Symptom
In Beta systems with more than four cable hops, unwanted bus resets
may occur.
Cause
A short IDLE between a data packet and an arbitration grant disappears.
As signals propagate across the 1394 network, the IDLE between a data
packet and an arbitration grant shortens since the time needed to repeat
a data packet is longer than the time needed to repeat a grant.
A. Force all 1394B connections to
S400B and add a 1394A PHY to
the system to force legacy gap
timing on the 1394 bus.
B. Add a 1394A connection every
fifth cable hop in the system.