LMV751
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SNOS468E –AUGUST 1999–REVISED MARCH 2013
LMV751 Low Noise, Low Vos, Single Op Amp
Check for Samples: LMV751
1FEATURES DESCRIPTION
The LMV751 is a high performance CMOS
2• Low Noise 6.5nV/√Hz operational amplifier intended for applications
• Low VOS (0.05mV typ.) requiring low noise and low input offset voltage. It
• Wideband 4.5MHz GBP typ. offers modest bandwidth of 4.5MHz for very low
supply current and is unity gain stable.
• Low Supply Current 500uA typ.
• Low Supply Voltage 2.7V to 5.0V The output stage is able to drive high capacitance, up
to 1000pF and source or sink 8mA output current.
• Ground-Referenced Inputs It is supplied in the space saving SOT-23-5 Tiny
• Unity Gain Stable package.
• Small Package The LMV751 is designed to meet the demands of
APPLICATIONS small size, low power, and high performance required
by cellular phones and similar battery operated
• Cellular Phones portable electronics.
• Portable Equipment
• Radio Systems
Connection Diagram
Figure 1. SOT-23-5 Top View
Figure 2. Voltage Noise Figure 3. Gain/Phase
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMV751
SNOS468E –AUGUST 1999–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
ESD Tolerance (3)
Human Body Model 2000V
Machine Model 200V
Differential Input Voltage ±Supply Voltage
Supply Voltage (V+- V−) 5.5V
Lead Temperature (Soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to 150°C
Junction Temperature (TJ)(4) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when
operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩin series with 100pF. Machine model, 200Ωin series with 1000pF.
(4) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Recommended Operating Conditions
Supply Voltage 2.7V to 5.0V
Temperature Range −40°C ≤TJ≤85°C
Thermal Resistance (θJA)(1)
DBV-5 Package, SOT-23-5 274°C/W
(1) All numbers are typical, and apply to packages soldered directly onto PC board in still air.
2.7V Electrical Characteristics
V+= 2.7V, V−= 0V, VCM = 1.35V, TA= 25°C unless otherwise stated. Boldface limits apply over the Temperature Range.
Typ Limit
Symbol Parameter Condition Units
(1) (2)
VOS Input Offset Voltage 0.05 1.0 mV
1.5 max
VCM Input common-Mode Voltage Range For CMRR ≥50dB 0 V
min
1.4 1.3 V
max
CMRR Common Mode Rejection Ratio 0V < VCM < 1.3V 100 85 dB
70 min
PSRR Power Supply Rejection Ratio V+= 2.7V to 5.0V 107 85 dB
70 min
ISSupply Current 0.5 0.8 mA
0.85 max
IIN Input Current 1.5 100 pA
max
IOS Input Offset Current 0.2 pA
AVOL Voltage Gain RL= 10k Connect to V+/2 120 110
VO= 0.2V to 2.2V 95 dB
min
RL= 2k Connect to V+/2 120 100
VO= 0.2V to 2.2V 85
(1) Typical values represent the most likely parametric norm.
(2) All limits are ensured by testing or statistical analysis
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2.7V Electrical Characteristics (continued)
V+= 2.7V, V−= 0V, VCM = 1.35V, TA= 25°C unless otherwise stated. Boldface limits apply over the Temperature Range.
Typ Limit
Symbol Parameter Condition Units
(1) (2)
VOPositive Voltage Swing RL= 10k Connect to V+/2 2.62 2.54
2.52 V
min
RL= 2k Connect to V+/2 2.62 2.54
2.52
VONegative Voltage Swing RL= 10k Connect to V+/2 78 140
160 mV
max
RL= 2k Connect to V+/2 78 160
180
IOOutput Current Sourcing, VO= 0V 12 6.0
VIN (diff) = ±0.5V 1.5 mA
min
Sinking, VO= 2.7V 11 6.0
VIN (diff) = ±0.5V 1.5
en(10Hz) Input Referred Voltage Noise 15.5 nV/√Hz
en(1kHz) Input Referred Voltage Noise 7 nV/√Hz
en(30kHz) Input Referred Voltage Noise 7 10 nV/√Hz max
IN(1kHz) Input Referred Current Noise 0.01 pA/√Hz
GBW Gain-Bandwidth Product 4.5 2 MHZ
min
SR Slew Rate 2 V/µs
5.0V Electrical Characteristics
V+= 5.0V, V−= 0V, VCM = 2.5V, TA= 25°C unless otherwise stated.Boldface limits apply over the Temperature Range.
Typ Limit
Symbol Parameter Units
(1) (2)
VOS Input Offset Voltage 0.05 1.0 mV
1.5 max
CMRR Common Mode Rejection Ratio 0V < VCM < 3.6V 103 85 dB
70 min
VCM Input Common-Mode Voltage Range For CMRR ≥50dB 0 V
min
3.7 3.6 V
max
PSRR Power Supply Rejection Ratio V+= 2.7V to 5.0V 107 85 dB
70 min
ISSupply Current 0.6 0.9 mA
0.95 max
IIN Input Current 1.5 100 pA
max
IOS Input offset Current 0.2 pA
AVOL Voltage Gain RL= 10k Connect to V+/2 120 110 db
VO= 0.2V to 4.5V 95 min
RL= 2k Connect to V+/2 120 100
VO= 0.2V to 4.5V 85
VOPositive Voltage Swing RL= 10k Connect to V+/2 4.89 4.82
4.80 V
min
RL= 2k Connect to V+/2 4.89 4.82
4.80
VONegative Voltage Swing RL= 10k Connect to V+/2 86 160
180 mV
max
RL= 2k Connect to V+/2 86 180
200
(1) Typical values represent the most likely parametric norm.
(2) All limits are ensured by testing or statistical analysis
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5.0V Electrical Characteristics (continued)
V+= 5.0V, V−= 0V, VCM = 2.5V, TA= 25°C unless otherwise stated.Boldface limits apply over the Temperature Range.
Typ Limit
Symbol Parameter Units
(1) (2)
IOOutput Current Sourcing, VO= 0V 15 8.0
VIN (diff) = ±0.5V 2.5 mA
min
Sinking, VO= 5V 20 8.0
VIN (diff) = ±0.5V 2.5
en(10Hz) Input Referred Voltage Noise 15 nV/ √Hz
en(1kHz) Input Referred Voltage Noise 6.5 nV/ √Hz
en(30kHz) Input Referred Voltage Noise 6.5 10 nV/ √Hz
max
IN(1kHz) Input Referred Current Noise 0.01 pA/√Hz
GBW Gain-Bandwidth Product 5 2 MHz
min
SR Slew Rate 2.3 V/µs
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SNOS468E –AUGUST 1999–REVISED MARCH 2013
Typical Performance Characteristics
VOS
Supply Current vs.
vs.
Voltage VCM, V+= 2.7V
Figure 4. Figure 5.
VOS Source Current
vs. vs.
VCM, V+= 5.0V Out, V+= 2.7V
Figure 6. Figure 7.
Source Current
vs.
VOUT, V+= 5.0V Gain/Phase
Figure 8. Figure 9.
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Typical Performance Characteristics (continued)
Sinking Current Sinking Current
vs. vs.
VOUT, V+= 2.7V VOUT, V+= 5.0V
Figure 10. Figure 11.
VOS VIN
vs. vs.
V+VOUT, V+= 2.7V, RL= 2k
Figure 12. Figure 13.
VIN Input Bias
vs. vs.
VOUT, V+= 5.0V, RL= 2k VCM, TA= 25°C
Figure 14. Figure 15.
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Typical Performance Characteristics (continued)
Input Bias
vs.
VCM, TA= 85°C PSRR +
Figure 16. Figure 17.
PSRR −Voltage Noise
Figure 18. Figure 19.
CMRR
Figure 20.
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APPLICATION HINTS
Noise
There are many sources of noise in a system: thermal noise, shot noise, 1/f, popcorn noise, resistor noise, just to
name a few. In addition to starting with a low noise op amp, such as the LMV751, careful attention to detail will
result in the lowest overall noise for the system.
To invert or not invert?
Both inverting and non-inverting amplifiers employ feedback to stabilize the closed loop gain of the block being
designed. The loop gain (in decibels) equals the algebraic difference between the open loop and closed loop
gains. Feedback improves the Total Harmonic Distortion (THD) and the output impedance. The various noise
sources, when input referred, are amplified, not by the closed loop gain, but by the noise gain. For a non-
inverting amplifier, the noise gain is equal to the closed loop gain, but for an inverting amplifier, the noise gain is
equal to the closed loop gain plus one. For large gains, e.g., 100, the difference is negligible, but for small gains,
such as one, the noise gain for the inverting amplifier would be two. This implies that non-inverting blocks are
preferred at low gains.
Source impedance
Because noise sources are uncorrelated, the system noise is calculated by taking the RMS sum of the various
noise sources, that is, the square root of the sum of the squares. At very low source impedances, the voltage
noise will dominate; at very high source impedances, the input noise current times the equivalent external
resistance will dominate. For a detailed example calculation, refer to Note 1.
Bias current compensation resistor
In CMOS input op amps, the input bias currents are very low, so there is no need to use RCOMP (see Figure 21
and Figure 22) for bias current compensation that would normally be used with early generation bipolar op amps.
In fact, inclusion of the resistor would act as another thermal noise source in the system, increasing the overall
noise.
Figure 21. Bias Current Compensation Resistor
Figure 22. Bias Current Compensation Resistor
Resistor types
Thermal noise is generated by any passive resistive element. This noise is "white"; meaning it has a constant
spectral density. Thermal noise can be represented by a mean-square voltage generator eR2in series with a
noiseless resistor, where eR2is given by: Where:
eR2= 4K TRB (volts)2
where
• T = temperature in °K
• R = resistor value in ohms
• B = noise bandwidth in Hz
• K = Boltzmann's constant (1.38 x 10-23 W-sec/°K) (1)
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Actual resistor noise measurements may have more noise than the calculated value. This additional noise
component is known as excess noise. Excess noise has a 1/f spectral response, and is proportional to the
voltage drop across the resistor. It is convenient to define a noise index when referring to excess noise in
resistors. The noise index is the RMS value in uV of noise in the resistor per volt of DC drop across the resistor
in a decade of frequency. Noise index expressed in dB is:
NI = 20 log ((EEX/VDC) x 106) db
where
• EEX = resistor excess noise in uV per frequency decade
• VDC = DC voltage drop across the resistor (2)
Excess noise in carbon composition resistors corresponds to a large noise index of +10 dB to -20 dB. Carbon
film resistors have a noise index of -10 dB to -25 dB. Metal film and wire wound resistors show the least amount
of excess noise, with a noise index figure of -15 dB to -40 dB.
Other noise sources:
As the op amp and resistor noise sources are decreased, other noise contributors will now be noticeable. Small
air currents across thermocouples will result in low frequency variations. Any two dissimilar metals, such as the
lead on the IC and the solder and copper foil of the pc board, will form a thermocouple. The source itself may
also generate noise. An example would be a resistive bridge. All resistive sources generate thermal noise based
on the same equation listed above under "resistor types". (2)
Putting it all together
To a first approximation, the total input referred noise of an op amp is:
Et2= en2+ ereq2+ (in*Req)2
where
• Req is the equivalent source resistance at the inputs (3)
At low impedances, voltage noise dominates. At high impedances, current noise dominates. With a typical noise
current on most CMOS input op amps of 0.01 pA/√Hz, the current noise contribution will be smaller than the
voltage noise for Req less than one megohm.
Other Considerations
Comparator operation
Occasionally operational amplifiers are used as comparators. This is not optimum for the LMV751 for several
reasons. First, the LMV751 is compensated for unity gain stability, so the speed will be less than could be
obtained on the same process with a circuit specifically designed for comparator operation. Second, op amp
output stages are designed to be linear, and will not necessarily meet the logic levels required under all
conditions. Lastly, the LMV751 has the newer PNP-NPN common emitter output stage, characteristic of many
rail-to-rail output op amps. This means that when used in open loop applications, such as comparators, with very
light loads, the output PNP will saturate, with the output current being diverted into the previous stage. As a
result, the supply current will increase to the 20-30 mA. range. When used as a comparator, a resistive load
between 2kΩand 10kΩshould be used with a small amount of hysteresis to alleviate this problem. When used
as an op amp, the closed loop gain will drive the inverting input to within a few millivolts of the non-inverting
input. This will automatically reduce the output drive as the output settles to the correct value; thus it is only when
used as a comparator that the current will increase to the tens of milliampere range.
Rail-to-Rail
Because of the output stage discussed above, the LMV751 will swing “rail-to-rail” on the output. This normally
means within a few hundred millivolts of each rail with a reasonable load. Referring to the Electrical
Characteristics table for 2.7V to 5.0V, it can be seen that this is true for resistive loads of 2kΩand 10kΩ. The
input stage consists of cascoded P-channel MOSFETS, so the input common mode range includes ground, but
typically requires 1.2V to 1.3V headroom from the positive rail. This is better than the industry standard LM324
and LM358 that have PNP input stages, and the LMV751 has the advantage of much lower input bias currents.
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Loading
The LMV751 is a low noise, high speed op amp with excellent phase margin and stability. Capacitive loads up to
1000 pF can be handled, but larger capacitive loads should be isolated from the output. The most straightforward
way to do this is to put a resistor in series with the output. This resistor will also prevent excess power dissipation
if the output is accidentally shorted.
General Circuits
With the low noise and low input bias current, the LMV751 would be useful in active filters, integrators, current to
voltage converters, low frequency sine wave generators, and instrumentation amplifiers. (3)
NOTE
1. Sherwin, Jim “Noise Specs Confusing?” AN-104 (SNVA515), Texas Instruments.
2. Christensen, John, “Noise-figure curve ease the selection of low-noise op amps”, EDN, pp 81-
84, Aug. 4, 1994.
3. “Op Amp Circuit Collection”, AN-31 (SNLA140), Texas Instruments.
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV751M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A32A
LMV751M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A32A
LMV751M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A32A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Oct-2017
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV751M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV751M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV751M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV751M5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV751M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV751M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
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PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
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Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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