LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 LMV751 Low Noise, Low Vos, Single Op Amp Check for Samples: LMV751 FEATURES DESCRIPTION * * * * * * * * The LMV751 is a high performance CMOS operational amplifier intended for applications requiring low noise and low input offset voltage. It offers modest bandwidth of 4.5MHz for very low supply current and is unity gain stable. 1 2 Low Noise 6.5nV/Hz Low VOS (0.05mV typ.) Wideband 4.5MHz GBP typ. Low Supply Current 500uA typ. Low Supply Voltage 2.7V to 5.0V Ground-Referenced Inputs Unity Gain Stable Small Package APPLICATIONS * * * Cellular Phones Portable Equipment Radio Systems The output stage is able to drive high capacitance, up to 1000pF and source or sink 8mA output current. It is supplied in the space saving SOT-23-5 Tiny package. The LMV751 is designed to meet the demands of small size, low power, and high performance required by cellular phones and similar battery operated portable electronics. Connection Diagram Figure 1. SOT-23-5 Top View Figure 2. Voltage Noise Figure 3. Gain/Phase 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated LMV751 SNOS468E - AUGUST 1999 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 2000V Machine Model 200V Differential Input Voltage Supply Voltage Supply Voltage (V+ - V-) 5.5V Lead Temperature (Soldering, 10 sec.) 260C -65C to 150C Storage Temperature Range Junction Temperature (TJ) (1) (4) 150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device beyond its rated operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 1.5k in series with 100pF. Machine model, 200 in series with 1000pF. The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/JA. All numbers apply for packages soldered directly into a PC board. (2) (3) (4) Recommended Operating Conditions Supply Voltage 2.7V to 5.0V -40C TJ 85C Temperature Range Thermal Resistance (JA) (1) DBV-5 Package, SOT-23-5 (1) 274C/W All numbers are typical, and apply to packages soldered directly onto PC board in still air. 2.7V Electrical Characteristics V+ = 2.7V, V- = 0V, VCM = 1.35V, TA = 25C unless otherwise stated. Boldface limits apply over the Temperature Range. Symbol Parameter VOS Input Offset Voltage VCM Input common-Mode Voltage Range Condition Typ Limit (2) Units 0.05 1.0 1.5 mV max 0 V min 1.4 1.3 V max (1) For CMRR 50dB CMRR Common Mode Rejection Ratio 0V < VCM < 1.3V 100 85 70 dB min PSRR Power Supply Rejection Ratio V+ = 2.7V to 5.0V 107 85 70 dB min IS Supply Current 0.5 0.8 0.85 mA max IIN Input Current 1.5 100 pA max IOS Input Offset Current AVOL Voltage Gain (1) (2) 2 0.2 pA RL = 10k Connect to V+/2 VO = 0.2V to 2.2V 120 110 95 RL = 2k Connect to V+/2 VO = 0.2V to 2.2V 120 100 85 dB min Typical values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 2.7V Electrical Characteristics (continued) V+ = 2.7V, V- = 0V, VCM = 1.35V, TA = 25C unless otherwise stated. Boldface limits apply over the Temperature Range. Symbol VO Positive Voltage Swing VO Negative Voltage Swing IO Typ Limit RL = 10k Connect to V+/2 2.62 2.54 2.52 RL = 2k Connect to V+/2 2.62 2.54 2.52 RL = 10k Connect to V+/2 78 140 160 RL = 2k Connect to V+/2 78 160 180 Sourcing, VO = 0V VIN (diff) = 0.5V 12 6.0 1.5 Sinking, VO = 2.7V VIN (diff) = 0.5V 11 6.0 1.5 Parameter Output Current Condition (1) (2) Units V min mV max mA min en (10Hz) Input Referred Voltage Noise 15.5 nV/Hz en (1kHz) Input Referred Voltage Noise 7 nV/Hz en (30kHz) Input Referred Voltage Noise 7 IN(1kHz) Input Referred Current Noise 0.01 GBW Gain-Bandwidth Product 4.5 SR Slew Rate 10 nV/Hz max pA/Hz 2 2 MHZ min V/s 5.0V Electrical Characteristics V+ = 5.0V, V- = 0V, VCM = 2.5V, TA = 25C unless otherwise stated.Boldface limits apply over the Temperature Range. Symbol Parameter Typ Limit (2) Units 0.05 1.0 1.5 mV max 103 85 70 dB min 0 V min 3.7 3.6 V max 107 85 70 dB min (1) VOS Input Offset Voltage CMRR Common Mode Rejection Ratio 0V < VCM < 3.6V VCM Input Common-Mode Voltage Range For CMRR 50dB V+ = 2.7V to 5.0V PSRR Power Supply Rejection Ratio IS Supply Current 0.6 0.9 0.95 mA max IIN Input Current 1.5 100 pA max IOS Input offset Current AVOL Voltage Gain VO VO (1) (2) Positive Voltage Swing Negative Voltage Swing 0.2 pA RL = 10k Connect to V+/2 VO = 0.2V to 4.5V 120 110 95 RL = 2k Connect to V+/2 VO = 0.2V to 4.5V 120 100 85 RL = 10k Connect to V+/2 4.89 4.82 4.80 RL = 2k Connect to V+/2 4.89 4.82 4.80 RL = 10k Connect to V+/2 86 160 180 RL = 2k Connect to V+/2 86 180 200 db min V min mV max Typical values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 3 LMV751 SNOS468E - AUGUST 1999 - REVISED MARCH 2013 www.ti.com 5.0V Electrical Characteristics (continued) V+ = 5.0V, V- = 0V, VCM = 2.5V, TA = 25C unless otherwise stated.Boldface limits apply over the Temperature Range. Symbol IO Typ Limit Sourcing, VO = 0V VIN (diff) = 0.5V 15 8.0 2.5 Sinking, VO = 5V VIN (diff) = 0.5V 20 8.0 2.5 Parameter Output Current (1) en (10Hz) Input Referred Voltage Noise 15 en (1kHz) Input Referred Voltage Noise 6.5 en (30kHz) Input Referred Voltage Noise 6.5 IN (1kHz) Input Referred Current Noise 0.01 GBW Gain-Bandwidth Product SR Slew Rate 4 5 2.3 Submit Documentation Feedback (2) Units mA min nV/ Hz nV/ Hz 10 nV/ Hz max pA/Hz 2 MHz min V/s Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 Typical Performance Characteristics Supply Current vs. Voltage VOS vs. VCM, V+ = 2.7V Figure 4. Figure 5. VOS vs. VCM, V+ = 5.0V Source Current vs. Out, V+ = 2.7V Figure 6. Figure 7. Source Current vs. VOUT, V+ = 5.0V Gain/Phase Figure 8. Figure 9. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 5 LMV751 SNOS468E - AUGUST 1999 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Sinking Current vs. VOUT, V+ = 2.7V Sinking Current vs. VOUT, V+ = 5.0V Figure 10. Figure 11. VOS vs. V+ VIN vs. VOUT, V+ = 2.7V, RL = 2k Figure 12. Figure 13. VIN vs. VOUT, V = 5.0V, RL = 2k Input Bias vs. VCM, TA = 25C Figure 14. Figure 15. + 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Input Bias vs. VCM, TA = 85C PSRR + Figure 16. Figure 17. PSRR - Voltage Noise Figure 18. Figure 19. CMRR Figure 20. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 7 LMV751 SNOS468E - AUGUST 1999 - REVISED MARCH 2013 www.ti.com APPLICATION HINTS Noise There are many sources of noise in a system: thermal noise, shot noise, 1/f, popcorn noise, resistor noise, just to name a few. In addition to starting with a low noise op amp, such as the LMV751, careful attention to detail will result in the lowest overall noise for the system. To invert or not invert? Both inverting and non-inverting amplifiers employ feedback to stabilize the closed loop gain of the block being designed. The loop gain (in decibels) equals the algebraic difference between the open loop and closed loop gains. Feedback improves the Total Harmonic Distortion (THD) and the output impedance. The various noise sources, when input referred, are amplified, not by the closed loop gain, but by the noise gain. For a noninverting amplifier, the noise gain is equal to the closed loop gain, but for an inverting amplifier, the noise gain is equal to the closed loop gain plus one. For large gains, e.g., 100, the difference is negligible, but for small gains, such as one, the noise gain for the inverting amplifier would be two. This implies that non-inverting blocks are preferred at low gains. Source impedance Because noise sources are uncorrelated, the system noise is calculated by taking the RMS sum of the various noise sources, that is, the square root of the sum of the squares. At very low source impedances, the voltage noise will dominate; at very high source impedances, the input noise current times the equivalent external resistance will dominate. For a detailed example calculation, refer to Note 1. Bias current compensation resistor In CMOS input op amps, the input bias currents are very low, so there is no need to use RCOMP (see Figure 21 and Figure 22) for bias current compensation that would normally be used with early generation bipolar op amps. In fact, inclusion of the resistor would act as another thermal noise source in the system, increasing the overall noise. Figure 21. Bias Current Compensation Resistor Figure 22. Bias Current Compensation Resistor Resistor types Thermal noise is generated by any passive resistive element. This noise is "white"; meaning it has a constant spectral density. Thermal noise can be represented by a mean-square voltage generator eR2 in series with a noiseless resistor, where eR2 is given by: Where: eR2 = 4K TRB (volts)2 where * * * * 8 T = temperature in K R = resistor value in ohms B = noise bandwidth in Hz K = Boltzmann's constant (1.38 x 10-23 W-sec/K) Submit Documentation Feedback (1) Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 Actual resistor noise measurements may have more noise than the calculated value. This additional noise component is known as excess noise. Excess noise has a 1/f spectral response, and is proportional to the voltage drop across the resistor. It is convenient to define a noise index when referring to excess noise in resistors. The noise index is the RMS value in uV of noise in the resistor per volt of DC drop across the resistor in a decade of frequency. Noise index expressed in dB is: NI = 20 log ((EEX/VDC) x 106) db where * * EEX = resistor excess noise in uV per frequency decade VDC = DC voltage drop across the resistor (2) Excess noise in carbon composition resistors corresponds to a large noise index of +10 dB to -20 dB. Carbon film resistors have a noise index of -10 dB to -25 dB. Metal film and wire wound resistors show the least amount of excess noise, with a noise index figure of -15 dB to -40 dB. Other noise sources: As the op amp and resistor noise sources are decreased, other noise contributors will now be noticeable. Small air currents across thermocouples will result in low frequency variations. Any two dissimilar metals, such as the lead on the IC and the solder and copper foil of the pc board, will form a thermocouple. The source itself may also generate noise. An example would be a resistive bridge. All resistive sources generate thermal noise based on the same equation listed above under "resistor types". (2) Putting it all together To a first approximation, the total input referred noise of an op amp is: Et2 = en2 + ereq2 + (in*Req)2 where * Req is the equivalent source resistance at the inputs (3) At low impedances, voltage noise dominates. At high impedances, current noise dominates. With a typical noise current on most CMOS input op amps of 0.01 pA/Hz, the current noise contribution will be smaller than the voltage noise for Req less than one megohm. Other Considerations Comparator operation Occasionally operational amplifiers are used as comparators. This is not optimum for the LMV751 for several reasons. First, the LMV751 is compensated for unity gain stability, so the speed will be less than could be obtained on the same process with a circuit specifically designed for comparator operation. Second, op amp output stages are designed to be linear, and will not necessarily meet the logic levels required under all conditions. Lastly, the LMV751 has the newer PNP-NPN common emitter output stage, characteristic of many rail-to-rail output op amps. This means that when used in open loop applications, such as comparators, with very light loads, the output PNP will saturate, with the output current being diverted into the previous stage. As a result, the supply current will increase to the 20-30 mA. range. When used as a comparator, a resistive load between 2k and 10k should be used with a small amount of hysteresis to alleviate this problem. When used as an op amp, the closed loop gain will drive the inverting input to within a few millivolts of the non-inverting input. This will automatically reduce the output drive as the output settles to the correct value; thus it is only when used as a comparator that the current will increase to the tens of milliampere range. Rail-to-Rail Because of the output stage discussed above, the LMV751 will swing "rail-to-rail" on the output. This normally means within a few hundred millivolts of each rail with a reasonable load. Referring to the Electrical Characteristics table for 2.7V to 5.0V, it can be seen that this is true for resistive loads of 2k and 10k. The input stage consists of cascoded P-channel MOSFETS, so the input common mode range includes ground, but typically requires 1.2V to 1.3V headroom from the positive rail. This is better than the industry standard LM324 and LM358 that have PNP input stages, and the LMV751 has the advantage of much lower input bias currents. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 9 LMV751 SNOS468E - AUGUST 1999 - REVISED MARCH 2013 www.ti.com Loading The LMV751 is a low noise, high speed op amp with excellent phase margin and stability. Capacitive loads up to 1000 pF can be handled, but larger capacitive loads should be isolated from the output. The most straightforward way to do this is to put a resistor in series with the output. This resistor will also prevent excess power dissipation if the output is accidentally shorted. General Circuits With the low noise and low input bias current, the LMV751 would be useful in active filters, integrators, current to voltage converters, low frequency sine wave generators, and instrumentation amplifiers. (3) NOTE 1. Sherwin, Jim "Noise Specs Confusing?" AN-104 (SNVA515), Texas Instruments. 2. Christensen, John, "Noise-figure curve ease the selection of low-noise op amps", EDN, pp 8184, Aug. 4, 1994. 3. "Op Amp Circuit Collection", AN-31 (SNLA140), Texas Instruments. 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 LMV751 www.ti.com SNOS468E - AUGUST 1999 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LMV751 11 PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV751M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A32A LMV751M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A32A LMV751M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A32A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMV751M5 SOT-23 DBV 5 1000 178.0 8.4 LMV751M5/NOPB SOT-23 DBV 5 1000 178.0 LMV751M5X/NOPB SOT-23 DBV 5 3000 178.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV751M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV751M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV751M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LMV751M5 LMV751M5/NOPB LMV751M5X LMV751M5X/NOPB