General Description
The MAX9248/MAX9250 digital video serial-to-parallel
converters deserialize a total of 27 bits during data and
control phases. In the data phase, the LVDS serial input
is converted to 18 bits of parallel video data and in the
control phase, the input is converted to 9 bits of parallel
control data. The separate video and control phases take
advantage of video timing to reduce the serial-data rate.
The MAX9248/MAX9250 pair with the MAX9247 serializer
to form a complete digital video transmission system. For
operating frequencies less than 35MHz, the MAX9248/
MAX9250 can also pair with the MAX9217 serializer.
The MAX9248 features spread-spectrum capability, allow-
ing output data and clock to spread over a specified fre-
quency range to reduce EMI. The data and clock outputs
are programmable for a spectrum spread of ±4% or ±2%.
The MAX9250 features output enable input control to
allow data busing.
Proprietary data decoding reduces EMI and provides DC
balance. The DC balance allows AC-coupling, providing
isolation between the transmitting and receiving ends of
the interface. The MAX9248/MAX9250 feature a select-
able rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
Contact Discharge and ±30kV Air-Gap Discharge.
The MAX9248/MAX9250 operate from a +3.3V ±10%
core supply and feature a separate output supply for
interfacing to 1.8V to 3.3V logic-level inputs. These
devices are available in a 48-lead LQFP package and are
specified from -40°C to +85°C or -40°C to +105°C.
Applications
●Navigation System Displays
●In-Vehicle Entertainment Systems
●Video Cameras
●LCD Displays
Benets and Features
●Programmable ±4% or ±2% Spread-Spectrum
Output for Reduced EMI (MAX9248)
●Proprietary Data Decoding for DC Balance and
Reduced EMI
●Control Data Deserialized During Video Blanking
●Five Control Data Inputs are Single-Bit-Error Tolerant
●Output Transition Time is Scaled to Operating
Frequency for Reduced EMI
●Staggered Output Switching Reduces EMI
●Output Enable Allows Busing of Outputs (MAX9250)
●Clock Pulse Stretch on Lock
●Wide ±2% Reference Clock Tolerance
●Synchronizes to MAX9247 Serializer Without
External Control
●ISO 10605 and IEC 61000-4-2 Level 4 ESD
Protection
●Separate Output Supply Allows Interface to 1.8V
to 3.3V Logic
●+3.3V Core Power Supply
●Space-Saving LQFP Package
●-40°C to +85°C and -40°C to +105°C Operating
Temperature Ranges
Ordering Information appears at end of data sheet.
19-3943; Rev 5; 6/17
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
EVALUATION KIT AVAILABLE
VCC_ to _GND ......................................................-0.5V to +4.0V
Any Ground to Any Ground .................................. -0.5V to +0.5V
IN+, IN- to LVDSGND ...........................................-0.5V to +4.0V
IN+, IN- Short Circuit to LVDSGND or VCCLVDS ......Continuous
(R/F, OUTEN, RNG_, REFCLK, SS
PWRDWN) to GND .............................. -0.5V to (VCC + 0.5V)
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to VCCOGND ...........................-0.5V to (VCCO + 0.5V)
Continuous Power Dissipation (TA = +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....1739mW
ESD Protection
Machine Model (RD = 0Ω, CS = 200pF)
All Pins to GND ..........................................................±200V
Human Body Model (RD = 1.5kΩ, CS = 100pF)
All Pins to GND ............................................................±2kV
ISO 10605 (RD = 2kΩ, CS = 330pF)
Contact Discharge (IN+, IN-) to GND ............................±10kV
Air-Gap Discharge (IN+, IN-) to GND ............................±30kV
IEC 61000-4-2 (RD = 330Ω, CS = 150pF)
Contact Discharge (IN+, IN-) to GND ............................±10kV
Air-Gap Discharge (IN+, IN-) to GND ............................±15kV
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature ...................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage │VID│ = 0.05V to 1.2V, input common-mode voltage
VCM = │VID/2│ to VCC - │VID/2│, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN, SS)
High-Level Input Voltage VIH 2.0 VCC + 0.3 V
Low-Level Input Voltage VIL -0.3 +0.8 V
Input Current IIN
PWRDWN =
high or low
VIN = -0.3V to 0
(MAX9248/MAX9250ECM),
VIN = -0.15V to 0
(MAX9248/MAX9250GCM),
-100 +20 µA
VIN = 0 to (VCC + 0.3V) -20 +20
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
High-Level Output Voltage VOH
IOH = -100µA VCCO - 0.1
VIOH = -2mA, RNG1 = high VCCO - 0.35
IOH = -2mA, RNG1 = low VCCO - 0.4
Low-Level Output Voltage VOL
IOL = 100µA 0.1
VIOL = 2mA, RNG1 = high 0.3
IOL = 2mA, RNG1 = low 0.35
High-Impedance Output
Current IOZ
PWRDWN = low or OUTEN = low,
VO = -0.3V to (VCCO + 0.3V) -10 +10 µA
Output Short-Circuit Current IOS
RNG1 = high, VO = 0 -10 -50 mA
RNG1 = low, VO = 0 -7 -40
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
│
2
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage │VID│ = 0.05V to 1.2V, input common-mode voltage
VCM = │VID/2│ to VCC - │VID/2│, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVDS INPUT (IN+, IN-)
Differential Input High
Threshold VTH (Note 3) 50 mV
Differential Input Low Threshold VTL (Note 3) -50 mV
Input Current IIN+, IIN- PWRDWN = high or low (Note 3) -40 +40 µA
Input Bias Resistor (Note 3) RIB
PWRDWN =
high or low
MAX9248/MAX9250ECM 42 60 78
kΩ
MAX9248/MAX9250GCM 42 60 88
VCC_ =
0 or open,
PWRDWN
= 0 or open,
Figure 1
MAX9248/MAX9250ECM 42 60 78
MAX9248/MAX9250GCM 42 60 88
Power-Off Input Current IINO+, IINO-
VCC_ = 0 or open,
PWRDWN = 0 or open (Note 3) -60 +60 µA
POWER SUPPLY
Worst-Case Supply Current
MAX9250
CL = 8pF,
worst-case
pattern,
Figure 2
RNG1 = low
RNG0 = high
5MHz 28
10MHz 49
RNG1 = high
RNG0 = low
10MHz 33
20MHz 59
RNG1 = high
RNG0 = high
20MHz 45
42MHz 89
MAX9248
CL = 8pF,
worst-case
pattern,
Figure 2
RNG1 = low
RNG0 = high
5MHz 40
10MHz 70
RNG1 = high
RNG0 = low
10MHz 49
20MHz 87
RNG1 = high
RNG0 = high
20MHz 68
35MHz 100
42MHz 120
Power-Down Supply Current ICCZ (Note 4) 50 µA
Electrical Characteristics (continued)
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
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(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage │VID│ = 0.1V to 1.2V, input common-mode voltage
VCM = │VID /2│ to VCC - │VID /2│, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFCLK TIMING REQUIREMENTS
Period tt
MAX9248/MAX9250ECM 23.8 200 ns
MAX9248/MAX9250GCM 28.6 200
Frequency fCLK
MAX9248/MAX9250ECM 5 42.0 MHz
MAX9248/MAX9250GCM 5 35.0
Frequency Variation ΔfCLK
REFCLK to serializer PCLK_IN,
worst-case output pattern (Figure 2)-2.0 +2.0 %
Duty Cycle DC 40 50 60 %
Transition Time tTRAN 20% to 80% 6 ns
SWITCHING CHARACTERISTICS
Output Rise Time tRFigure 3
RNG1 = high
MAX9248/
MAX9250ECM 2.2 4.6
ns
MAX9248/
MAX9250GCM 2.2 4.9
RNG1 = low
MAX9248/
MAX9250ECM 2.8 5.2
MAX9248/
MAX9250GCM 2.8 6.1
Output Fall Time tRFigure 3
RNG1 = high MAX9248/
MAX9250ECM 1.9 4.0
ns
RNG1 = low
MAX9248/
MAX9250ECM 2.3 4.3
MAX9248/
MAX9250GCM 2.3 5.2
PCLK_OUT High Time tHIGH Figure 4 0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
PCLK_OUT Low Time tLOW Figure 4 0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
Data Valid Before PCLK_OUT tDVB Figure 5
0.35
x t
T
0.4 x
t
T
ns
Data Valid After PCLK_OUT tDVA Figure 5
0.35
x t
T
0.4 x
t
T
ns
PLL Lock to REFCLK tPLLREF
MAX9248, Figure 8 33,600 x tTns
MAX9250, Figure 7 16,928 x tT
AC Electrical Characteristics
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
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(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage │VID│ = 0.1V to 1.2V, input common-mode voltage
VCM = │VID /2│ to VCC - │VID /2│, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 3, 5)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static.
Note 5: CL includes probe and test jig capacitance.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Spread-Spectrum Output
Frequency (MAX9248) fPCLK_OUT
SS = high,
Figure 11
Maximum output
frequency
fREFCLK
+ 3.6%
fREFCLK
+ 4.0%
fREFCLK
+ 4.4%
MHz
Minimum output
frequency
fREFCLK
- 4.4%
fREFCLK
- 4.0%
fREFCLK
- 3.6%
SS = low,
Figure 11
Maximum output
frequency
fREFCLK
+ 1.8%
fREFCLK
+ 2.0%
fREFCLK
+ 2.2%
Minimum output
frequency
fREFCLK
- 2.2%
fREFCLK
- 2.0%
fREFCLK
- 1.8%
Spread-Spectrum Modulation
Frequency fSSM Figure 11
fREFCLK
+ 3.6% kHz
Power-Down Delay tPDD Figures 7, 8100 ns
SS Change Delay tΔSSPLL MAX9248, Figure 17 32,800 x tTns
Output Enable Time tOE MAX9250, Figure 8 10 30 ns
Output Disable Time tOZ MAX9250, Figure 9 10 30 ns
AC Electrical Characteristics (continued)
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
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(VCC_ = +3.3V, CL = 8pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
MAX9248/50 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
35305 10 15 20 25
10
20
30
40
50
60
70
0
0 40 45
MAX9248
MAX9250
OUTPUT POWER SPECTRUM vs.
FREQUENCY
(REFCLK = 42MHz, NO SPREAD,
4%, AND 2% SPREAD)
MAX9248/50 toc04
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
43 44424140
-30
-20
-10
-60
-50
-40
0
-70
39 45
NO SPREAD
RESOLUTION BW = 30kHz
VIDEO BW = 100kHz
2% SPREAD
4% SPREAD
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO
)
MAX9248/50 toc02
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
3.02.72.42.1
1
2
3
4
5
6
0
1.8 3.3
RNG1 = HIGH
tR
tF
BIT-ERROR RATE vs. CABLE LENGTH
MAX9248/50 toc05
CAT5 CABLE LENGTH (m)
BIT-ERROR RATE
8 10642
1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
0 12
REFCLK = 42MHz
840Mbps DATA RATE
FOR CABLE LENGTH < 10m
BER < 10-12
CAT5 CABLE
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
CCO)
MAX9248/50 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
3.02.72.42.1
4
5
6
1
2
3
7
8
9
10
0
1.8 3.3
RNG1 = LOW
tR
tF
CABLE LENGTH vs. FREQUENCY
BIT-ERROR RATE < 10-9
MAX9248/50 toc06
CABLE LENGTH (m)
FREQUENCY (MHz)
25
30
10
15
20
35
40
45
5
181614121086420 20
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
Maxim Integrated
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PIN NAME FUNCTION
MAX9248 MAX9250
1 1 R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_
OUT for latching data into the next chip. Set R/F = high for a rising latch edge.
Set R/F = low for a falling latch edge. Internally pulled down to GND.
2 2 RNG1 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer
parallel clock input frequency. Internally pulled down to GND.
3 3 VCCLVDS
LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel
as close to the device as possible, with the smallest value capacitor closest to the supply pin.
4 4 IN+ Noninverting LVDS Serial-Data Input
5 5 IN- Inverting LVDS Serial-Data Input
6 6 LVDSGND LVDS Supply Ground
7 7 PLLGND PLL Supply Ground
8 8 VCCPLL
PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
9 9 RNG0 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internal pulldown to GND.
10 10 GND Digital Supply Ground
11 11 VCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to
GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible
with the smallest value capacitor closest to the supply pin.
12 12 REFCLK LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of
the serializer PCLK_IN frequency. Internally pulled down to GND.
Pin Description
Pin Conguration
RGB_OUT7
RGB_OUT6
RGB_OUT5
RGB_OUT4
RGB_OUT3
RGB_OUT2
RGB_OUT1
RGB_OUT0
PCLK_OUT
LOCK
VCCO
VCCOGND
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
PWRDWN
SS (OUTEN)
CNTL_OUT0
CNTL_OUT1
CNTL_OUT2
CNTL_OUT3
CNTL_OUT4
CNTL_OUT5
CNTL_OUT6
CNTL_OUT7
CNTL_OUT8
DE_OUT
LQFP
MAX9248
MAX9250
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
RGB_OUT17
RGB_OUT16
RGB_OUT15
RGB_OUT14
RGB_OUT13
RGB_OUT12
RGB_OUT11
RGB_OUT10
RGB_OUT9
RGB_OUT8
VCCO
VCCOGND
R/F
RNG1
VCCLVDS
IN+
IN-
LVDSGND
PLLGND
VCCPLL
RNG0
GND
VCC
REFCLK
TOP VIEW
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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PIN NAME FUNCTION
MAX9248 MAX9250
13 13 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
14 — SS
LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of
PCLK_OUT and output data relative to PCLK_IN. Drive SS high for 4% spread and
pull low for 2% spread.
15–23 15–23 CNTL_OUT0–
CNTL_OUT8
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip
on the rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low,
and are held at the last state when DE_OUT is high.
24 24 DE_OUT LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active.
Low indicates CNTL_OUT[8:0] are active.
25, 37 25, 37 VCCOGND Output Supply Ground
26, 38 26, 38 VCCO
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
27 27 LOCK LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28 28 PCLK_OUT LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge
selected by R/F.
29–36,
39–48
29–36,
39–48
RGB_OUT0–
RBG_OUT7,
RGB_OUT8–
RGB_OUT17
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs.
RGB_OUT[17:0] are latched into the next chip on the edge of PCLK_OUT selected by
R/F when DE_OUT is high, and are held at the last state when DE_OUT is low.
— 14 OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs.
Driving low places the single-ended outputs in high impedance except LOCK.
Internally pulled down to GND.
Pin Description (continued)
Functional Diagram
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
SSPLL
FIFO
RNG[0:1]
R/F
RNG[0:1]
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
R/F
MAX9250
MAX9248
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
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Figure 1. LVDS Input Bias
Figure 5. Synchronous Output Timing
Figure 6. Deserializer Delay
Figure 3. Output Rise and Fall Times
Figure 2. Worst-Case Output Pattern
Figure 4. High and Low Times
LVDS
RECEIVER
1.2V
IN+
RIB
RIB
IN-
PCLK_OUT
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
RISING LATCH EDGE SHOWN (R/F = HIGH).
DE_OUT
LOCK
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.9 x VCCO
0.1 x VCCO
tF
tR
PCLK_OUT
tLOW
tHIGH
2.0V
0.8V
PCLK_OUT
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
tDVB tDVA
2.0V
2.0V2.0V
0.8V
0.8V
0.8V
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
IN+, IN-
PCLK_OUT
CNTL_OUT
RGB_OUT
20 SERIAL BITS
SERIAL-WORD N SERIAL-WORD N + 1
PARALLEL-WORD N - 1 PARALLEL-WORD N
tDELAY
PCLK_OUT SHOWN FOR R/F = HIGH
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250
Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
tPLLREF TRANSITION
WORD
FOUND
RECOVERED CLOCK
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
tPDD
0.8V
2.0V
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
tPLLREF TRANSITION
WORD
FOUND
OUTPUT CLOCK SPREAD
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
tPDD
0.8V
2.0V
288 CLOCK CYCLES
OUTPUT DATA SPREAD
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Figure 9. Output Enable Time
Figure 11. Simplified Modulation Profile
Figure 10. Output Disable Time
OUTEN
ACTIVEHIGH IMPEDANCE
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
tOE
0.8V MAX9250
FREQUENCY
TIME
fRxCLKOUT (MAX)
fRxCLKIN
fRxCLKOUT (MIN)
1 / fSSM
OUTEN
HIGH IMPEDANCEACTIVE
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
tOZ
2.0V
MAX9250
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Detailed Description
The MAX9248/MAX9250 DC-balanced deserializers
operate at a 5MHz-to-42MHz parallel clock frequency,
deserializing video data to the RGB_OUT[17:0] outputs
when the data-enable output DE_OUT is high, or control
data to the CNTL_OUT[8:0] outputs when DE_OUT is
low. The outputs on the MAX9248 are programmable
for ±2% or ±4% spread relative to the LVDS input clock
frequency, while the MAX9250 has no spread, but has
an output-enable input that allows output busing. The
video phase words are decoded using two overhead
bits (EN0 and EN1). Control phase words are decoded
with one overhead bit (EN0). Encoding, performed by
the MAX9247 serializer, reduces EMI and maintains DC
balance across the serial cable. The serial-input word
formats are shown in Table 1 and Table 2.
Control data inputs C0 to C4, each repeated over three
serial bit times by the serializer, are decoded using major-
ity voting. Two or three bits at the same state determine
the state of the recovered bit, providing single bit-error
tolerance for C0 to C4. The state of C5 to C8 is determined
by the level of the bit itself (no voting is used).
AC-Coupling Benets
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two capaci-
tors are sufficient for isolation, but four capacitors—two at
the serializer output and two at the deserializer input—
provide protection if either end of the cable is shorted to
a high voltage. AC-coupling blocks low-frequency ground
shifts and common-mode noise.
The MAX9247 serializer can also be DC-coupled to the
MAX9248/MAX9250 deserializers. Figure 12 and Figure
14 show the AC-coupled serializer and deserializer with
two capacitors per link, and Figure 13 and Figure 15
show the AC-coupled serializer and deserializer with four
capacitors per link.
Applications Information
Selection of AC-Coupling Capacitors
See Figure 16 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequency.
The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1μF capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through 42kΩ (min) to provide biasing for
AC-coupling (Figure 1). Assuming 100Ω interconnect,
the LVDS input can be terminated with a 100Ω resistor.
Match the termination to the differential impedance of the
interconnect.
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For interconnect
with 100Ω differential impedance, pull each LVDS line up to
VCC with 130Ω and down to ground with 82Ω at the dese-
rializer input (Figure 12 and Figure 15 ). This termination
provides both differential and common-mode termination.
The impedance of the Thevenin termination should be half
the differential impedance of the interconnect and provide
a bias voltage of 1.2V.
Table 1. Serial Video Phase Word Format
Table 2. Serial Control Phase Word Format
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
Figure 13. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
VCC
130Ω
IN
OUT
82Ω82Ω
RNG1
RNG0
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE
*CAPACITORS CAN BE AT EITHER END.
*
*
R/F
CMF
PRE
MAX9250
MAX9247
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
VCC
130Ω
IN
OUT
82Ω82Ω
RNG1
RNG0
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE
CMF
PRE R/F
MAX9250
MAX9247
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
Figure 15. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link
PAR-TO-SER
TIMING AND
CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
VCC
130Ω
IN+
IN-
OUT
82Ω82Ω
CMF
PRE
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE
PLL
*
*
*CAPACITORS CAN BE AT EITHER END.
SSPLL
FIFO
RNG[0:1]
R/F
MAX9248
MAX9247
PAR-TO-SER
TIMING AND
CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
VCC
130Ω
IN+
IN-
OUT
82Ω82Ω
CMF
PRE
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE
PLL SSPLL
FIFO
RNG[0:1]
R/F
MAX9248
MAX9247
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Input Frequency Detection
A frequency-detection circuit detects when the LVDS input
is not switching. When not switching, all outputs except
LOCK are low, LOCK is high, and PCLK_OUT follows
REFCLK. This condition occurs, for example, if the serial-
izer is not driving the interconnect or if the interconnect
is open.
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency range
of the MAX9248/MAX9250 and the transition time of the
outputs. Select the frequency range that includes the
MAX9247 serializer PCLK_IN frequency. Table 3 shows
the selectable frequency ranges and the corresponding
data rates and output-transition times.
Power Down
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ VCC - 0.3V, the supply
current is reduced to less than 50μA. Driving PWRDWN
high initiates lock to the local reference clock (REFCLK)
and afterwards to the serial input.
Lock and Loss-of-Lock (LOCK)
When PWRDWN is driven high, the PLL begins lock-
ing to REFCLK, drives LOCK from high impedance to
high, and the other outputs from high impedance to low,
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Lock to REFCLK takes a
maximum of 16,928 REFCLK cycles for the MAX9250.
The MAX9248 has an additional spread-spectrum PLL
(SSPLL) that also begins locking to REFCLK. Locking
both PLLs to REFCLK takes a maximum of 33,600
REFCLK cycles for the MAX9248.
When the MAX9248/MAX9250 complete their lock to
REFCLK, the serial input is monitored for a transition word.
When a transition word is found, LOCK output is driven
low, indicating valid output data and the parallel rate clock
recovered from the serial input is output on PCLK_OUT.
The MAX9248 SSPLL waits an additional 288 clock cycles
after the transition word is found before LOCK is driven low
and sequence takes effect. PCLK_OUT is stretched on the
change from REFCLK to recovered clock (or vice versa) at
the time when the transition word is found.
If a transition word is not detected within 222 cycles
of PCLK_OUT, LOCK is driven high; the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for the
MAX9250 and Figure 8 for the MAX9248 regarding the
synchronization timing diagram.
The MAX9248 input-to-output delay can be as low as
(4.5tT + 8.0)ns or as high as (36tT + 16)ns due to spread-
spectrum variations (see Figure 6).
The MAX9250 input-to-output delay can be as low as
(3.575tT + 8)ns or as high as (3.725tT + 16)ns.
Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
Table 3. Frequency Range Programming
RNG1 RNG0
PARALLEL
CLOCK
(MHz)
SERIAL-
DATA RATE
(Mbps)
OUTPUT-
TRANSITION
TIME
0 0 Do not use Slow
0 1 5 to 10 100 to 200
1 0 10 to 20 200 to 400 Fast
1 1 20 to 42 400 to 840
PARALLEL CLOCK FREQUENCY (MHz)
CAPACITOR VALUE (nF)
21 24 27 33 36 3930
120
80
60
40
20
100
140
0
18 42
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Spread-Spectrum Selection
The MAX9248 single-ended data and clock outputs are
programmable for a variation of ±2% or ±4% around the
LVDS input clock frequency. The modulation rate of the
frequency variation is 32kHz for a 33MHz LVDS clock
input and scales linearly with the clock frequency (see
Table 4). The output spread is controlled through the SS
input (see Table 5). Driving SS high spreads all data and
clock outputs by ±4%, while pulling low spreads ±2%.
Any spread change causes a delay time of 32,000 x tT
before output data is valid. When the spread amount
is changed from ±2% to ±4% or vice versa, the data
outputs go low for one tΔSSPLL delay (see Figure 17). The
data outputs stay low, but are not valid when the spread
amount is changed.
Output Enable (OUTEN) and Busing Outputs
The outputs of two MAX9250s can be bused to form a 2:1
mux with the outputs controlled by the output enable. Wait
30ns between disabling one deserializer (driving OUTEN
low) and enabling the second one (driving OUTEN high)
to avoid contention of the bused outputs. OUTEN controls
all outputs except LOCK.
Rising or Falling Output Latch Edge (R/F)
The MAX9248/MAX9250 have a selectable rising or
falling output-latch edge through a logic setting on R/F.
Driving R/F high selects the rising output-latch edge,
which latches the parallel output data into the next chip on
the rising edge of PCLK_OUT. Driving R/F low selects the
falling output-latch edge, which latches the parallel output
data into the next chip on the falling edge of PCLK_OUT.
The MAX9248/MAX9250 output-latch-edge polarity does
not need to match the MAX9247 serializer input-latch-
edge polarity. Select the latch-edge polarity required by
the chip being driven by the MAX9248/MAX9250.
Table 4. Modulation Rate
Table 5. SS Function
Figure 17. Output Waveforms when Spread Amount is Changed
fPCLK_IN fM(kHz) = fPCLK_IN/1024
8 7.81
10 9.77
16 15.63
32 31.25
40 39.06
42 41.01
SS INPUT LEVEL OUTPUT SPREAD
High Data and clock output spread ±4%
relative to REFCLK
Low Data and clock output spread ±2%
relative to REFCLK
t∆SSPLL (32,800 x tT)
±4% OR ±2% SPREAD±4% OR ±2% SPREAD
LOW
SS
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT8:0]
LOCK
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Staggered and Transition Time
Adjusted Outputs
RGB_OUT[17:0] are grouped into three groups of six, with
each group switching about 1ns apart in the video phase
to reduce EMI and ground bounce. CNTL_OUT[8:0]
switch during the control phase. Output transition time
is slower in the 5MHz to 10MHz range and faster in the
10MHz to 20MHz and 20MHz to 42MHz ranges.
Data-Enable Output (DE_OUT)
The MAX9248/MAX9250 deserialize video and control
data at different times. Control data is deserialized during
the video blanking time. DE_OUT high indicates that video
data is being deserialized and output on RGB_OUT[17:0].
DE_OUT low indicates that control data is being deserial-
ized and output on CNTL_OUT[8:0]. When outputs are
not being updated, the last data received is latched on the
outputs. Figure 18 shows the DE_OUT timing.
Power-Supply Sequencing of the MAX9247
and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can
be powered up in several ways. The best approach is to
keep both MAX9247 and MAX9248 powered down while
supplies are ramping up and PCLK_IN of the
MAX9247 and REFCLK of the MAX9248/MAX9250 are
stabilizing. After all the power supplies of the MAX9247 and
MAX9248/MAX9250 are stable, including PCLK_IN and
REFCLK, do the following:
●Power up the MAX9247 first wiith high-transition
density data (e.g., PRBS, checkboard)
●Wait for at least tLOCK of MAX9247 (or 17100 x tT)
to get activity on the link
●Power up the MAX9248
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital
circuits and LVTTL/LVCMOS inputs (VCC supply and GND),
outputs (VCCO supply and VCCOGND), PLL (VCCPLL
supply and PLLGND), and the LVDS input (VCCLVDS
supply and LVDSGND). The grounds are isolated by
diode connections. Bypass each VCC, VCCO, VCCPLL,
and VCCLVDS pin with high-frequency, surface-mount
ceramic 0.1μF and 0.001μF capacitors in parallel as close
to the device as possible, with the smallest value capacitor
closest to the supply pin. The outputs are powered from
VCCO, which accepts a 1.71V to 3.6V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
Figure 18. Output Timing
PCLK_OUT
CNTL_OUT
DE_OUT
RGB_OUT
= OUTPUT DATA HELD
CONTROL DATA CONTROL DATAVIDEO DATA
PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE)
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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Cables and Connectors
Interconnect for LVDS typically has a differential
impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable, and
tend to generate less EMI due to magnetic field-canceling
effects. Balanced cables pick up noise as common mode,
which is rejected by the LVDS receiver.
Board Layout
Separate the LVTTL/LVCMOS outputs and LVDS inputs
to prevent crosstalk. A four-layer PCB with separate
layers for power, ground, and signals is recommended.
ESD Protection
The MAX9248/MAX9250 ESD tolerance is rated for
Human Body Model, Machine Model, IEC 61000-4-2,
and ISO 10605. The ISO 10605 and IEC 61000-4-2
standards specify ESD tolerance for electronic systems.
All LVDS inputs on the MAX9248/MAX9250 meet ISO
10605 ESD protection at ±30kV Air-Gap Discharge
and ±10kV Contact Discharge and IEC 61000-4-2 ESD
protection at ±15kV Air-Gap Discharge and ±10kV
Contact Discharge. All other pins meet the Human Body
Model ESD tolerance of ±2kV. The Human Body Model
discharge components are CS = 100pF and RD = 1.5kΩ
(Figure 19). The IEC 61000-4-2 discharge components
are CS = 150pF and RD = 330Ω (Figure 20). The ISO
10605 discharge components are CS = 330pF and RD =
2kΩ (Figure 21). The Machine Model discharge compo-
nents are CS = 200pF and RD = 0Ω (Figure 22).
Figure 19. Human Body ESD Test Circuit
Figure 21. ISO 10605 Contact Discharge ESD Test Circuit
Figure 20. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 22. Machine Model ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩ
RD
1.5kΩ
CS
100pF
CS
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
R2
330Ω
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
2kΩ
CS
330pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
0Ω
CS
200pF
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
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+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 LQFP C48+3 21-0054 90-0093
PART TEMP RANGE PIN-PACKAGE
MAX9248ECM+ -40°C to +85°C 48 LQFP
MAX9248ECM/V+ -40°C to +85°C 48 LQFP
MAX9248GCM+ -40°C to +105°C 48 LQFP
MAX9248GCM/V+ -40°C to +105°C 48 LQFP
MAX9250ECM+ -40°C to +85°C 48 LQFP
MAX9250ECM/V+ -40°C to +85°C 48 LQFP
MAX9250GCM+ -40°C to +105°C 48 LQFP
MAX9250GCM/V+ -40°C to +105°C 48 LQFP
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: CMOS
Ordering Information
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
www.maximintegrated.com Maxim Integrated
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19
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 5/08 Replaced TQFP and TQFN packages with LQFP package, changed temperature
limits for +105°C part, and added Machines Model ESD text and diagram 1–5, 7, 16–19
3 4/09 Added /V parts in the Ordering Information table and added new Power-Supply
Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section 1, 17
4 7/14 Claried denition of test conditions and updated Package Information 4, 17, 19
5 6/17 Removed low-speed operation 1–20
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX9248/MAX9250 27-Bit, 5MHz to 42MHz
DC-Balanced LVDS Deserializers
© 2017 Maxim Integrated Products, Inc.
│
20
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