oa NATL SEMICOND (MEMORY) NMC9314B ALE D ME 6501126 0063486 7 National Semiconductor FH613 229 NMC9314B 1024-Bit Serial Electrically E Erasable Programmable Memory General Description The NMC9314B Is a 1024-bit non-volatile, sequential E2PROM, fabricated using advanced N-channel E2PROM technology. It isan external memory with the 1024 bits of read/write memory divided into 64 registers of 16 bits each. Each register can be serially read or written by a COP400 controller, or a standard microprocessor. Written informa- tlon Is stored in a floating gate cell until updated by an erase and write cycle. The NMC9314B has been designed for ap- plications requiring up to 104 erase/write cycles per regis- ter. A power-down mode Is provided by CS to reduce power consumption by 75 percent. Features 10,000 erase/write cycles mw 10 year data retention m@ Low cost m. Single. supply read/write/erase operations (ov10%) m TTL compatible . @ 64x 16 serial read/write memory m NICROWIRE compatible serial vo & Simple interfacing m Low standby power eg .2oc47 @ Non-volatile erase and write @ Reliable floating gate technology - _m Self-timed programming cycle Poa nG Device status signal during programming = =: . . Block and Connection Diagrams Wr / We DATA REGISTER (17 81T8} INSTRUCTION REGISTER (8 818) INSTRUCTION, DECODE, CONTROL, AND CLOCK GENERATOR Dual-In-Line Package (N) cit VY 8 vee node . Thwe* as ne no4 5 }cno . Tuo/9144-2 = Top View . Order Number NMC9314N See NS Package NOSE Pin Names - : = CS. Chip Sefect Sang SK - Serial Data Clock. _ os DI Serial Data {input ~ - po pO Serial Data Output Veco Power Supply Jose GND Ground - oF NC - Not Connected - TL/D/9144-4: 2-48NATL SEMICOND (MEMORY) 31E D MM 6501126 0063489 95 om avLesOWN eke Mavi a -46-13-27 Absolute Maximum Ratings (note 1) T-40-18 cee ON (f Military/Aerospace specified devices are required, - Ambient Storage Temp. ~65C to.+ 125C please contact the National Semiconductor Sales Lead Temperature (Soldering, 10 sconds) 300C Office/Distributors for avallabillty and specifications. ESD Rating : >2000V Voltage Relative to GND | +6V to 0.3V . oo Ambient Operating Temperature ~ 0C to +70C oo / DC and AC Electrical Characteristics o-c<1,<70c, Voo=5V+10% unless specified Symbol Parameter ; Conditions - Min Max Units Veo _ Operating Voltago : ., 45 5.5 Vv lect | Operating Current Voco=5.6V, CS=1,SK=1- |. 17 mA- CCl | Erase/Write Operating Current Voco=5.5V an P47 mA loca | Standby Current Voo=5.5V, CS=0 6" mA * Input Voltage Levels - ot . Vit , 0.1 0.8 Vv Vin | . 2.0 Voo+0.5 ve Output Voltage Levels : _ _ 4 Vou . lo.=2.1 mA 04 --] Vv. Vou. : | > lon=400 pA 2.4 : M Iu Input Leakage Current Vin=5.5V 10 pA ILo Output Leakage Current VouT=5.5V, CS=0 ; 10 pA : SK Frequency 0 -= 200 kHz tsKH SK High Time (Note 2) 3 : -| BS tone SK Low Time (Note 2) 2 ps Inputs : sO tags cs 0.2 . BS tosH 0 BS tos Dl 0.4 ps tol = 4 0.4 BS Output C= 100 pF toatl DO ; : " - Vo_=0.8V, Voy=2.0V 2 ps tog . Vit = 0.45V, Vin =2.40V _ 2. BS teyw Seif-Timed Program Cycle - 15 ms tes Min CS Low Time (Note 3) ; 1 BS _tey Rising Edg of CS to Status Valid * OL= 100 pF 1 ps: torn try Falling Edge of CS to DO TRI-STATE 0.4) ps Note 1: Stress abova those listed under Absolute Maximum Ratings" may causs pormanent damage {o the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated In the operational sections of the specification Is not implied. Exposure to absolute maximum rating conditions for extended: periods may affect device reliability. Note 2: The SK frequency spec. specifies a minimum SK clock period of 5 p23, therefore in an SK clee 6g, Iftgx_ = 2 ys then the minimum text = 3 ys In order to meet the SK frequency specification, Note 3; CS must be brought low for a minimum of 1 us (tes) between consecutive instruction cycles. Instruction Set for NMC9314B Instruction | SB | Op Code Address ; Data - Comments _ , | -READ 1 10. | ASA4A3A2A1A0 __ | Read register ASA4A3A2A1A0 WRITE 1 | _0t | asaaasazatao | 015-0 | Write register ASA4A3A2A1A0 ERASE 1 11 ABA4ASA2A1A0 5 Erase. register ASA4A8A2A1A0 EWEN 1 00 112000 Erase/write enable EWDS 1 00 |. O0wox Erase/write disable ERAL 1 00 10x _- | Erase all registers WRAL 1 00 ~ O1n0x D15-D0 | Write all registers NMC9314B has 7 instructions as shown. Note that the MSB8 of any given Instruction Is a "1" and Is viewed as a start bit in the Interface sequence. The next 8 bits carry the op code and the 6-bit address for 1 of 64, 16-bit registers. K cycle tsxH + tsKL must be greater than or equal to 5 ps. 2-49"elect pean NATL SEMICOND (MEMORY) 31LE NMC9314B D mi &5011e6b oob3490 5 = Functional Description The NMG9314B6 Is a small peripheral memory intended for use with COPSTM controllers and other nonvolatita memory . applications. {ts. organization is sixty-four registers and each register Is sixteen bits wide. The {input and output pins are controlled by separate serial formats. Seven 9-bit instruc: tlons cari be executed. The instruction format has a logical 1 as a start bit, two bits as-an op code, and: six bits of address. The programming cyele Is self-timed, with the data out (DO) pin indicating the ready/busy status of the chip. The on-chip programming voltage generator allows the user to use-a single. power supply (Vgc). It only generates high voltage during the programming modes (write, erase, chip erase, chip write). The DO pin is valid as data out during the tead mode, and if Initiated, as a ready/busy status indicator during a programming cycle. During all other modes the DO pin is in TRI-STATE, eliminating bus contention, READ The read Instruction Is the only instruction which outputs. serlal data on the DO pin. After a read instruction is re- ceived, the Instruction and address are decoded, followed by data transfer from the memory register into a 16-bit seri- al-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. ERASE/WRITE ENABLE AND DISABLE When Voc Is applied to the part it powers up in the program- ming disable (EWDS) state, programming must be preceded. - by a programming enable (EWEN) instruction. Programming remains enabled until a programming disable (EWDS) in- struction is executed or Vcc.is removed from the part. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruc- ton Is independent of both EWEN and EWDS instructions. ERASE (Note 4) Like most E2PROMs, the register must first be erased (all bits set to. logical 1") before the register can be written (cer- tain bits set to logical 0'), After an erase instruction is input, CS is dropped low. This falling edge of CS determines Timing Diagrams Synchronous Data Timing SK cg 0 *Thig Is the minimum SK period. , T- 46- 13-27. the start of the self: timed programming cycle. If CS is brought high subsequently (after observing. the tos specitt- cation), the DO pin will indicate the ready/busy status of the chip. The DO pin will go tow if the chip.is still programming. The. DO pin will go high when all bits of the register at the - address specified in the instruction have been set to a logl- cal 1. The part is now ready for the. next {instruction se- quence. ~ WRITE (Note 4) The write instruction is followed by 16 bits of data to be written into-the specified address. After the last bit of data (D0) is put on the data in (Dl) pin CS: must be brought tow ~ before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. Like all programming modes, DO Indicates the ready/busy status of the chip if CS Is brought high after a minimum of-1 2S (tes). DO=logical 0 indicates that programming is still in prog- ress, DO=logical 1 indicates that the register at the ad- dress specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. The register to be written into must | have been previously erased. ps CHIP ERASE (Note 4) , a ' Entire. chip erasing is provided for ease of programming: Erasing the chip means that all registers in the memory ar- ray have each bit set to a logical 1. Each register is then ready for a write instruction. The chip erase cycle is identical _ to the erase cycle except for the different op code. CHIP WRITE (Note 4) a All registers must b erased before a chip write operation. The chip write.cycle is identical to the write cycle except for the different op code. Alt registers are simultaneously writ- .ten with the. data pattern specified in the instruction. Note 4: During a programming mode (write, erase, chip erase, chip write), SK clock ts only needed while the actual instruction, ie., start bit, op code, address and data, Is being Input. It can rentain deactivated during the self- timed programming cycle and status check. tow toln O.4ys 04 TL/D/9144~3 2-50mm &S01l12b OOL349L 7 JLE D NATL SEMICOND (MEMORY) NMC9314B Timing Diagrams (Continued) +~prie/ariL po=318vsI0 bmg SIVIS-THE o X YuYuyX KRAK*KLAM J \ 1 f to Buju uoponaysuy oA VIS-TUL J*. WX XKeXe Xe Vf fo 2-51ME LS0112b 0063492 9 31E D . SPeLB/OsIL Timing Diagrams (continued Vo X Xe XX tf BONIS x SMIVAS OIHI a #* / $3 LOU cnr | Buju, uoponysuy 2.52 NATL SEMICOND (MEMORY) PlLE6DWN