August 2015
DocID027849 Rev 3
1/43
This is information on a product in full production.
www.st.com
VNI8200XP-32
Octal high-side smart power solid-state relay with serial/parallel
selectable interface on-chip
Datasheet - production data
Features
Type
RDS(on)(1)
IOUT(1)
VCC
VNI8200XP-32
VCC-45 V
0.11 Ω
1 A
45 V
Notes:
(1)Per channel
Output current: 1 A per channel
Serial/parallel selectable interface
Short-circuit protection
8-bit and 16-bit SPI interface for IC
command and control diagnostic
Channel overtemperature detection and
protection
Thermal independence of separate channels
All type of loads (resistive, capacitive,
inductive load) are driven
Loss of GND protection
Power Good diagnostic
Undervoltage shutdown with hysteresis
Overvoltage protection (VCC clamping)
Very low supply current
Common fault open drain output
IC warning temperature detection
Channel output enable
100 mA high efficiency step-down switching
regulator with integrated boot diode
Adjustable regulator output
Switching regulator disable
5 V and 3.3 V compatible I/Os
Channel output status LED driving 4x2
multiplexed array
Fast demagnetization of inductive loads
ESD protection
Designed to meet IEC61131-2,
IEC61000-4-4 and IEC61000-4-5
Applications
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Table 1: Device summary
Order code
Package
Packing
VNI8200XP-32
PowerSSO-36
Tube
VNI8200XPTR-32
Tape and
reel
PowerSSO-36 package
with exposed pad down (EPD)
Contents
VNI8200XP-32
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DocID027849 Rev 3
Contents
1 Description....................................................................................... 6
2 Block diagram .................................................................................. 7
3 Pin connection ................................................................................. 8
4 Maximum ratings ........................................................................... 10
5 Electrical characteristics .............................................................. 12
5.1 Power section .................................................................................. 12
5.2 SPI characteristics .......................................................................... 13
5.3 Switching ......................................................................................... 13
5.4 Logic inputs ..................................................................................... 14
5.5 Protection and diagnostic ................................................................ 14
5.6 Step-down switching regulator ........................................................ 16
5.7 LED driving array ............................................................................ 16
6 Reverse polarity protection .......................................................... 17
7 Demagnetization energy ............................................................... 18
8 Truth table ...................................................................................... 19
9 Pin function description................................................................ 20
9.1 SPI/parallel selection mode (SEL2) ................................................. 20
9.2 Serial data in (SDI) .......................................................................... 20
9.3 Serial data out (SDO) ...................................................................... 20
9.4 Serial data clock (CLK) ................................................................... 20
9.5 Slave select ..................................................................................... 21
9.6 8/16-bit selection (SEL1) ................................................................. 21
9.7 Output enable (OUT_EN) ................................................................ 21
9.8 IC warning case temperature detection ........................................... 22
9.9 Fault indication ................................................................................ 22
9.10 Power Good ( PG ) ........................................................................ 23
9.11 Programmable watchdog counter reset (WD) ................................. 23
10 SPI operation (SEL2 = H) .............................................................. 25
10.1 8-bit SPI mode (SEL1 = L) .............................................................. 25
10.2 16-bit SPI mode (SEL1 = H) ............................................................ 25
11 LED driving array .......................................................................... 27
VNI8200XP-32
Contents
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12 Step-down switching regulator .................................................... 28
13 Typical circuits and conventions ................................................. 29
14 Thermal management ................................................................... 32
14.1 Thermal behavior ............................................................................ 33
15 Interface timing diagram ............................................................... 34
16 Switching parameter test conditions ........................................... 35
17 Package information ..................................................................... 36
17.1 PowerSSO-36 package information ................................................ 36
17.2 Packing information ......................................................................... 39
18 Revision history ............................................................................ 42
List of tables
VNI8200XP-32
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DocID027849 Rev 3
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description .............................................................................................................................. 8
Table 3: Absolute maximum ratings ......................................................................................................... 10
Table 4: Thermal data ............................................................................................................................... 11
Table 5: Power section ............................................................................................................................. 12
Table 6: SPI characteristics ...................................................................................................................... 13
Table 7: Switching ..................................................................................................................................... 13
Table 8: Logic inputs ................................................................................................................................. 14
Table 9: Protection and diagnostic ........................................................................................................... 14
Table 10: Step-down switching regulator.................................................................................................. 16
Table 11: LED driving array ...................................................................................................................... 16
Table 12: Truth table ................................................................................................................................. 19
Table 13: Pin function description ............................................................................................................. 20
Table 14: Programmable watchdog time .................................................................................................. 23
Table 15: Command 8-bit frame (master-to-slave) ................................................................................... 25
Table 16: Fault 8-bit frame (slave-to-master) ........................................................................................... 25
Table 17: Command 16-bit frame (master-to-slave) ................................................................................. 25
Table 18: Fault 16-bit frame (slave-to-master) ......................................................................................... 26
Table 19: PowerSSO-36 mechanical data................................................................................................ 38
Table 20: PowerSSO-36 tube shipment mechanical data ........................................................................ 39
Table 21: PowerSSO-36 tape dimension mechanical data ...................................................................... 40
Table 22: PowerSSO-36 reel dimension mechanical data ....................................................................... 41
Table 23: Document revision history ........................................................................................................ 42
VNI8200XP-32
List of figures
DocID027849 Rev 3
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List of figures
Figure 1: Block diagram .............................................................................................................................. 7
Figure 2: Pin connection (top view) ............................................................................................................ 8
Figure 3: Reverse polarity protection ........................................................................................................ 17
Figure 4: Maximum demagnetization energy vs. load current, typical values .......................................... 18
Figure 5: SPI mode diagram ..................................................................................................................... 21
Figure 6: Output channel enable/disable behavior ................................................................................... 22
Figure 7: Power Good diagnostic ............................................................................................................. 23
Figure 8: Watchdog reset ......................................................................................................................... 24
Figure 9: LED driving array ....................................................................................................................... 27
Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V ............................................................. 29
Figure 11: Typical circuit for switching regulation VDC-out = 5 V ................................................................ 30
Figure 12: SPI directional logic convention............................................................................................... 31
Figure 13: PowerSSO-36 thermal impedance vs. time ............................................................................ 32
Figure 14: Thermal behavior ..................................................................................................................... 33
Figure 15: Serial timing ............................................................................................................................. 34
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions ........................................................ 35
Figure 17: td(ON) and td(OFF) time diagram test conditions ........................................................................... 35
Figure 18: PowerSSO-36 package outline ............................................................................................... 36
Figure 19: PowerSSO-36 package outline details .................................................................................... 37
Figure 20: PowerSSO-36 package outline details (section B-B) .............................................................. 37
Figure 21: PowerSSO-36 tube shipment outline ...................................................................................... 39
Figure 22: PowerSSO-36 tape dimension outline .................................................................................... 40
Figure 23: PowerSSO-36 reel shipment outline ....................................................................................... 41
Description
VNI8200XP-32
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DocID027849 Rev 3
1 Description
The VNI8200XP-32 is a monolithic 8-channel driver featuring a very low supply current,
with integrated SPI interface and high efficiency 100 mA micropower step-down switching
regulator peak current control loop mode. The IC, realized in STMicroelectronics
VIPower™ technology, is intended to drive any kind of load with one side connected to
ground.
Active channel current limitation combined with thermal shutdown, independent for each
channel, and automatic restart, protect the device against overload.
Additional embedded functions are: loss of GND protection that automatically turns off the
device outputs in case of ground disconnection, undervoltage shutdown with hysteresis,
Power Good diagnostic for valid supply voltage range recognition, output enable function
for immediate power outputs ON/OFF, and programmable watchdog function for
microcontroller safe operation; case overtemperature protection to control the IC case
temperature.
The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations;
through a select pin the device can also operate with a parallel interface.
Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection.
The SPI interface allows command of the output driver by enabling or disabling each
channel featuring, in 16-bit format, a parity check control for communication robustness. It
also allows the monitoring of the status of the IC signaling Power Good, overtemperature
condition for each channel, IC pre-warning temperature detection.
Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In
overload condition, the channel turns OFF and ON again automatically after the IC
temperature decreases below a threshold fixed by a temperature hysteresis so that junction
temperature is controlled. If this condition makes case temperature reaching case
temperature limit, TCSD, overloaded channels are turned OFF and restart, non-
simultaneously, when case and junction temperature decrease below their own reset
threshold. If the case of thermal reset, the channels loaded are not switched on until the
junction temperature reset event. Non-overloaded channels continue to operate normally.
Case temperature above TCSD is reported through the TWARN open drain pin.
An internal circuit provides a not latched common FAULT indicator reporting if one of the
following events occurs: channel OVT (overtemperature), parity check fail. The Power
Good diagnostic warns the controller that the supply voltage is below a fixed threshold.
The watchdog function is used to detect the occurrence of a software fault of the host
controller. The watchdog circuitry generates an internal reset on expiry of the internal
watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse
on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This
pin also allows the programming of a wide range of watchdog timings.
An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status
of the single outputs. An integrated step-down voltage regulator provides supply voltage to
the internal LED matrix driver and logic output buffers and can be used to supply the
external optocouplers if the application requires isolation. The regulator is protected against
short-circuit or overload conditions thanks to pulse-by-pulse current limit with a peak
current control loop.
VNI8200XP-32
Block diagram
DocID027849 Rev 3
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2 Block diagram
Figure 1: Block diagram
DCVDD
Vcc
clamp
DC-DC
converter
SPI Logic
Clamppower
Undervoltageand
Power Good
LED
drivng
detection
Currentlimiter
FB
SEL1/IN1
WD_EN/IN2
OUT_EN/IN3
WD/IN4
SDI/IN5
CLK/IN6
SS/IN7
SDO/IN8
SEL2
VREG
ROW0
ROW1
ROW2
ROW3
COL0
COL1
FAULT
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
PHASE
BOOT
VREF
PG
VCC
Pull-down
resistor
TWARN
Case temp.
Junction temp.
detection
GIPG020420151244LM
Pin connection
VNI8200XP-32
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DocID027849 Rev 3
3 Pin connection
Figure 2: Pin connection (top view)
Table 2: Pin description
Pin
Name
Type
Description
1
SEL2
Logic input
SPI/parallel selection mode
2
SEL1/IN1
Logic input
8/16-bit SPI selection mode/channel 1 input
3
WD_EN/ IN2
Logic/analog
input
Watchdog enable_setting/channel 2 input
4
OUT_EN /IN3
Logic input
Output enable/channel 3 input
5
WD/IN4
Logic input
Watchdog input. The internal watchdog counter is
cleared on the falling edges/channel 4 input
6
SDI/IN5
Logic input
Serial data input/channel 5 input
7
CLK/IN6
Logic input
Serial clock/channel 6 input
8
SS /IN7
Logic input
Slave select/channel 7 input
9
SDO/IN8
Logic
input/output
Serial data output/channel 8 input
10
VREG
Power supply
SPI/inputs/LED supply voltage
11
COL0
Open source
output
LED source output
12
COL1
Open source
output
LED source output
13
DCVDD
Analog output
Internally generated DC-DC low voltage supply (to
be connected to external 10 nF capacitor)
SEL2
1
SEL1/IN1
2
WD_EN/IN2
3
OUT_EN/IN3
4
WD/IN4
SDI/IN5
6
CLK/IN6
7
SS/IN7
8
9
VREG
10
COL0
11
COL1
12
DCVDD
13
VREF
14
ROW0
15
ROW1
16
ROW2
17
ROW3
18 PG 19
FAULT 20
TWARN 21
FB
23
GND
22
PHASE 24
BOOT 25
NC 26
OUT8 27
OUT7 28
OUT6 29
OUT5 30
OUT4 31
OUT3 32
OUT2 33
OUT1 34
NC 35
NC 36
SDO/IN8TAB=Vcc
5
GIPG020420151249LM
VNI8200XP-32
Pin connection
DocID027849 Rev 3
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Pin
Name
Type
Description
14
VREF
Analog output
Internally generated DC-DC voltage reference (to be
connected to external 10 nF capacitor)
15
ROW0
Open drain
output
Status channel 1-2
16
ROW1
Open drain
output
Status channel 3-4
17
ROW2
Open drain
output
Status channel 5-6
18
ROW3
Open drain
output
Status channel 7-8
19
PG
Open drain
output
Power Good diagnostic, active low
20
FAULT
Open drain
output
Fault indication, active low
21
TWARN
Open drain
output
IC case warning temperature detection, active low
22
FB
Analog input
Step-down feedback input. The output voltage,
directly connected to this pin, results in an output
voltage of 3.3 V. An external resistor divider is
required for higher output voltages
23
GND
Ground
24
PHASE
Power output
Step-down output
25
BOOT
Power output
Step-down bootstrap voltage. Used to provide a
drive voltage, higher than the supply voltage, to
power the switch of the step-down regulator
26
NC
Not connected
27
OUT8
Power output
Channel 8 power output
28
OUT7
Power output
Channel 7 power output
29
OUT6
Power output
Channel 6 power output
30
OUT5
Power output
Channel 5 power output
31
OUT4
Power output
Channel 4 power output
32
OUT3
Power output
Channel 3 power output
33
OUT2
Power output
Channel 2 power output
34
OUT1
Power output
Channel 1 power output
35
NC
Not connected
36
NC
Not connected
TAB
TAB
Power supply
Exposed tab internally connected to VCC
Maximum ratings
VNI8200XP-32
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DocID027849 Rev 3
4 Maximum ratings
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Power supply voltage
45
V
-VCC
Reverse supply voltage
-0.3
V
VREG
Logic supply voltage
-0.3 to +6
V
VFAULT
VTWARN
VPG
Voltage range on pins TWARN , FAULT , PG
-0.3 to +6
V
VBOOT
Bootstrap peak voltage VPHASE = VCC
VCC+6
V
VROW
Voltage range on ROW pins
-0.3 to +6
V
VCOL
Voltage range on COL pins
-0.3 to +6
V
VIN
Voltage level range on logic input pins
-0.3 to +6
V
IOUT
Output current (continuous)
Internally limited(1)
A
IR
Reverse output current (per channel)
-5
A
IGND
DC ground reverse current
-250
mA
IREG
VREG input current
-1/10
mA
IFAULT
ITWARN,
IPG
Current range on pins TWARN , FAULT , PG
-1 to +10
mA
IIN
Input current range
-1 to +10
mA
IROW
Current range on ROW pins (ROW in ON-state)
+20
mA
Current range on ROW pins (ROW in OFF-state)
-1 to +10
mA
ICOL
Current range on COL pins (COL in ON-state)
-10
mA
Current range on COL pins (COL in OFF-state)
-1 to +10
mA
VESD
Electrostatic discharge (R = 1.5 kΩ; C = 100 pF)
2000
V
EAS
Single pulse avalanche energy per channel not
simultaneously @Tamb = 125 °, IOUT = 0.5 A
3
J
PTOT
Power dissipation at TC = 25 °C
Internally limited (1)
W
TJ
Junction operating temperature
Internally limited
°C
TSTG
Storage temperature
-55 to 150
°C
Notes:
(1)Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous
operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime.
VNI8200XP-32
Maximum ratings
DocID027849 Rev 3
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Table 4: Thermal data
Symbol
Parameter
Value
Unit
Rth(JC)
Thermal resistance junction-case (1)
Max.
2
°C/W
Rth(JA)
Thermal resistance junction-ambient (2)
Max.
15
°C/W
Notes:
(1)Per channel.
(2)PowerSSO-36 mounted on a four-layer FR4, with 8 cm2 for each layer, Cu thickness = 35 µm
Electrical characteristics
VNI8200XP-32
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DocID027849 Rev 3
5 Electrical characteristics
5.1 Power section
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 5: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC
Supply voltage
10.5
36
V
VCC
clamp
Clamp on VCC
Current 20 mA
45
50
52
V
RDS(on)
On-state
resistance
IOUT = 0.5 A at TJ = 25 °C
0.11
Ω
IOUT = 0.5 A at TJ = 125 °C
0.2
IS
VCC supply
current
All channels in OFF-state,
DC-DC in OFF-state,
VREG=5 V, SPI OFF (1)
0.65
1
1.1
mA
All channels in ON-state,
DC-DC in ON-state VREG = 5
V, SPI ON (2)
5.3
mA
All channels in ON-state,
DC-DC in OFF-state
VREG = 5 V, SPI ON (3)
3.5
5.2
mA
IDS
VREG supply
current
DC-DC OFF VREG = 5 V SPI
OFF WD_EN = 0
200
µA
DC/DC OFF VREG = 5 V SPI
ON WD_EN = VREG
250
µA
ILGND
Output current at
GND
disconnection
All pins at 0 V except
VOUT = 24 V
0.5
mA
VOUT(OFF)
OFF-state output
voltage
VIN = 0 V, IOUT = 0 A
1
V
IOUT(OFF)
OFF-state output
current
VIN = VOUT = 0 V
0
2
µA
FCP
Charge pump
frequency
Channel in ON-state (4)
1.45
MHz
Notes:
(1) SS signal high, no communication.
(2) SS signal low, communication ON.
(3) SS signal low, communication ON.
(4)To cover EN55022 class A and class B normative.
VNI8200XP-32
Electrical characteristics
DocID027849 Rev 3
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5.2 SPI characteristics
10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 <Tj <125 °C; unless otherwise specified
Table 6: SPI characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
fCLK
SPI clock frequency
-
5
MHz
tr(CLK),
tf(CLK)
SPI clock rise/fall time
-
20
ns
tsu(SS )
SS setup time
120
-
ns
th(SS )
SS hold time
120
-
ns
tw(CLK)
CLK high time
80
-
ns
tsu(SDI)
Data input setup time
100
-
ns
th(SDI)
Data input hold time
100
-
ns
ta(SDO)
Data output access time
-
100
ns
tdis(SDO)
Data output disable time
-
200
ns
tv(SDO)
Data output valid time
-
100
ns
th(SDO)
Data output hold time
0
-
ns
VSDO
Voltage on serial data
output
ISDO =15 mA
VREG-0.8
-
V
ISDO =-4 mA
-
0.8
V
5.3 Switching
VCC = 24 V; -40 °C < TJ < 125 °C
Table 7: Switching
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(ON)
Turn-on delay time
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
5
-
µs
tr
Rise time
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
5
-
µs
td(OFF)
Turn-off delay time
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
10
-
µs
tf
Fall time
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
5
-
µs
dV/dt(ON)
Turn-on voltage
slope
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
3
-
V/µs
dV/dt(off)
Turn-off voltage
slope
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs
-
4
-
V/µs
Electrical characteristics
VNI8200XP-32
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DocID027849 Rev 3
5.4 Logic inputs
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 8: Logic inputs
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIL
Input low level
voltage
0.8
V
VIH
Input high level
voltage
2.20
V
VI(HYST)
Input hysteresis
voltage
0.15
V
IIN
Input current
VIN = 5 V
8
µA
5.5 Protection and diagnostic
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 9: Protection and diagnostic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VPGH1
Power Good
diagnostic ON
threshold
16.5
17.5
18.4
V
VPGH2
Power Good
diagnostic OFF
threshold
15.2
16.5
17.4
VPGHYS
Power Good
diagnostic hysteresis
1
VUSD
Undervoltage ON
protection
9.5
10
V
Undervoltage OFF
protection
8.4
9
V
VUSDHYS
Undervoltage
hysteresis
0.4
0.5
V
Vdemag
Output voltage at
turn-OFF
IOUT = 0.5 A;
LLOAD ≥ 1 mH
VCC-52
VCC-50
VCC-45
V
VTWARN
TWARN pin low-
state output voltage
ITWARN = 3 mA (active
condition)
0.6
V
VFAULT
FAULT pin low-
state output voltage
IFAULT = 3 mA (fault
condition)
0.6
V
VPG
PG pin low-state
output voltage
IPG = 3 mA (active
condition)
VREG = 3.3 V VCC = 0
0.7
V
IPEAK
Maximum DC output
current before
limitation
2.2
A
ILIM
Short-circuit current
limitation per channel
RLOAD = 0 VCC = 24 V
TJ = 25 °C
1.1
1.9
2.7
A
VNI8200XP-32
Electrical characteristics
DocID027849 Rev 3
15/43
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Hyst
ILIM tracking limits
RLOAD = 0
0.3
A
ILFAULT
FAULT leakage
current
Vpin = 5 V
2
μA
ITWARN
TWARN leakage
current
IPG
PG leakage current
TTSD
Junction shutdown
temperature
160
180
°C
TR
Junction reset
temperature
160
°C
THIST
Junction thermal
hysteresis
20
°C
TCSD
Case shutdown
temperature
115
130
155
°C
TCR
Case reset
temperature
110
°C
TCHYST
Case thermal
hysteresis
20
°C
tWD
Watchdog hold time
See Figure 8:
"Watchdog reset"
50
ns
tWM
Watchdog time
See Table 14:
"Programmable
watchdog time" and
Figure 8: "Watchdog
reset"
tOUT_EN
OUT_EN pin
propagation delay (1)
VCC= 24 V IOUT 72 mA
10
us
tres
OUT_EN hold time
50
ns
tWO
Watchdog timeout (2)
tWM +
td(off)
ms
Notes:
(1)Time from reset active low and power out disable.
(2)The time from tWM elapsed to power out disable.
Electrical characteristics
VNI8200XP-32
16/43
DocID027849 Rev 3
5.6 Step-down switching regulator
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 10: Step-down switching regulator
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VDC_out
Regulated output voltage
IREG from 0 to 100 mA
VREG 3.3 V, see Figure
10: "Typical circuit for
switching regulation
VDC-out = 3.3 V"
3.1
3.3
3.5
V
IREG from 0 to 100 mA
VREG 5 V, see Figure 11:
"Typical circuit for
switching regulation
VDC-out = 5 V"
5
VFB
Voltage feedback
3.1
3.3
3.5
V
RDS(on)
MOSFET on-resistance
1.5
Ω
Ilim
Limitation current
0.55
0.9
A
Iqop
Total operating quiescent
current
0.6
mA
Iqst-by
Total standby quiescent
current
Regulator standby
15.8
µA
fs
Switching frequency
400
kHz
Dmax
Maximum duty cycle
80%
%
Tonmin
Minimum on-time
150
ns
fsc
Frequency in short-circuit
condition
50
kHz
5.7 LED driving array
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 11: LED driving array
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCOL
Output source
voltage on COL
pins
Output current 0
to 7 mA
VREG-0.3
VREG-0.2
V
VROW
Open drain voltage
on ROW pins
Output current 0
to 15 mA
0.2
0.3
V
Fsw
Row refresh
frequency with
duty=25%
780
Hz
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Reverse polarity protection
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6 Reverse polarity protection
Reverse polarity protection can be implemented on board using two different solutions:
1. Placing a resistor (RGND) between IC GND pin and load GND
2. Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the
following equation:
RGND ≥ VCC / IGND
where IGND is the DC reverse ground pin current and can be found in Section 4: "Maximum
ratings" of this datasheet.
Power dissipated by RGND (when VCC < 0: during reverse polarity situations) is:
PD = (VCC)2/RGND
If option 2 is selected, the diode has to be chosen by taking into account VRRM >|VCC| and
its power dissipation capability:
PD ≥ IS*VF
In normal conditions (no reverse polarity), due to the diode, there is a voltage drop
between GND of the device and GND of the system.
Figure 3: Reverse polarity protection
This schematic can be used with any type of load.
Demagnetization energy
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7 Demagnetization energy
Figure 4: Maximum demagnetization energy vs. load current, typical values
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8 Truth table
Table 12: Truth table
Condition
Input
Output
SPI
status bit
FAULT
TWARN
PG
Normal operation
High
On
Reset
High
High
High
Low
Off
Reset
High
High
High
Junction overtemperature
High
Off
Set
Low
X
X
Low
Off
Set(1)
High
X
X
Case overtemperature
High
Off
Set(1)
X
Low
X
Low
Off
Set(1)
X
Low (1)
X
Undervoltage
High
Off
Reset
X
X
X
Low
Off
Reset
X
X
X
Power Good
High
On
Set (2)
High
High
Low
Low
Off
Set(2)
High
High
Low
Notes:
(1)This signal becomes high after the temperature falls below the reset threshold.
(2)If fault expires, the reset condition occurs after SPI communication, otherwise it is set again.
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9 Pin function description
9.1 SPI/parallel selection mode (SEL2)
This pin allows the selection of the IC interfacing mode. The SPI interface is selected if
SEL2 = H, while the parallel interface is selected if SEL2 = L, according to :
Table 13: Pin function description
Pin
SEL2 = Ha
SPI operation
SEL2 = L
parallel operation
SDO/IN8
SDO
Serial data output
IN8
Input to channel 8
SS /IN7
SS
Slave select
IN7
Input to channel 7
CLK/IN6
CLK
Serial clock
IN6
Input to channel 6
SDI/IN5
SDI
Serial data input
IN5
Input to channel 5
WD/IN4
WD
Watchdog input
IN4
Input to channel 4
OUT_EN/IN3
OUT_EN
IC OUTPUT enable / disable
IN3
Input to channel 3
WD_EN/IN2
WD_EN
Watchdog enable / disable and timing preset
IN2
Input to channel 2
SEL1/IN1
SEL1
8/16-bit SPI selection mode
IN1
Input to channel 1
9.2 Serial data in (SDI)
If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges
and, therefore, the microcontroller must change SDI state during the CLK falling edges.
After the SS falling edge, the SDI is equal to the most significant bit of the control frame
(Figure 5: "SPI mode diagram").
9.3 Serial data out (SDO)
If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling
edges and, therefore, the microcontroller must read SDO state during the CLK rising
edges.
The SDO pin is tri-stated when SS signal is high and it is equal to the most significant bit
of the fault frame after the SS falling edge (Figure 5: "SPI mode diagram").
9.4 Serial data clock (CLK)
If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the
SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller.
On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from
the most to the less significant one (see Figure 5: "SPI mode diagram"). When the SS
a
SEL2 has an internal weak pull-down.
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signal is high, slave not selected, the microcontroller should drive the CLK low (the settings
for the MCU SPI port are CPHA = 0 and CPOL = 0).
9.5 Slave select
If SEL2 = H, the slave select ( SS ) signal is used to enable the VNI8200XP-32 serial
communication shift register; data is flushed-in through the SDI pin and flushed-out from
the SDO pin only when the SS pin is low. On the SS pin falling edge the shift register
(containing the fault conditions) is frozen, so any change on the power switches status is
latched until the next SS falling edge event and the SDO output is enabled. On the SS
pin rising edge event the 8/16 bits present on the SPI shift register are evaluated and the
outputs are driven according to this frame. If more than 8/16 bits (depending on the SPI
settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from
the SDO pin after fault condition bits; in this way a proper communication is possible also in
a daisy chain configuration.
Figure 5: SPI mode diagram
9.6 8/16-bit selection (SEL1)
If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI
mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described
below.
9.7 Output enable (OUT_EN)
If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously.
When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault
conditions in the SPI register are latched. To enable the outputs, the OUT_EN pin should
be raised and the IC should be re-programmed through the SPI interface. As fault
conditions are latched inside the IC and SPI interface also works while the OUT_EN pin is
driven low, the SPI can be used to detect if a fault condition occurred before than the reset
event.
Pin function description
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The device is ready to operate normally after a TSU period. The OUT_EN pin is the fastest
way to disable all outputs when a fault occurs.
Figure 6: Output channel enable/disable behavior
9.8 IC warning case temperature detection
The TWARN pin is an active low open drain output. This pin is active if the IC case
temperature exceeds TCSD. According to the PCB thermal design and RthJC value, this
function allows a warning about a PCB overheating condition to be given.
The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin
is low only while the case overtemperature condition is active (TC > TCSD) and is released
when this condition is removed (TC < TCR).
9.9 Fault indication
The FAULT pin is an open drain active low fault indication pin. This pin is activated by
one or more of the following conditions:
Channel overtemperature (OVT)
This pin is activated when at least one of the channels is in junction overtemperature.
Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only
when the fault condition is active and is released if the input driving signal is OFF or after
the OVT protection condition has been removed. This last event occurs if the channel
temperature decreases below the threshold level and the case temperature has not
exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the
junction overtemperature is active (TJ > TTSD) and is released after this condition has
been removed (TJ < TR and TC < TCR).
Parity check fail
When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is
detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is
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kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the
FAULT pin is kept high.
9.10 Power Good ( PG )
The PG terminal is an open drain, which indicates the status of the supply voltage. When
VCC supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It
goes into a low impedance state when VCC falls below the Vsth2 threshold.
In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good
diagnostic is active, it is otherwise cleared.
Figure 7: Power Good diagnostic
9.11 Programmable watchdog counter reset (WD)
If SEL2 = H, the VNI8200XP-32 embeds a watchdog counter that must be erased, with a
negative pulse on the WD pin, before it expires. If the WD counter elapses, the
VNI8200XP-32 goes into an internal reset state where all the outputs are disabled; to
restart normal operation a negative pulse must be applied to the WD pin.
The watchdog enable/disable pin should be connected through an external divider to VREG.
The watchdog time is fixed in the following table:
Table 14: Programmable watchdog time
VWD_EN
tWM
0.25 VREG > VWD_EN
Disable
0.25 VREG ≤ VWD_EN < 0.5 VREG
40 ± 25% ms
0.25 VREG ≤ VWD_EN < 0.75 VREG
80 ± 25% ms
0.75 VREG ≤ VWD_EN = VREG
160 ± 25% ms
Vcc
PG
VPGH2 VPGH1
GIPG030420151221LM
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Figure 8: Watchdog reset
VNI8200XP-32
SPI operation (SEL2 = H)
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10 SPI operation (SEL2 = H)
10.1 8-bit SPI mode (SEL1 = L)
If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the
microcontroller to the IC; each bit directly drives the corresponding output where LSB
drives output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the
corresponding output.
At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller.
These fault conditions are latched at the occurrence and cleared after each communication
(each time the SS signal has a positive transition). Each bit, set to ‘1’, indicates an OVT
condition for the corresponding channel.
Table 15: Command 8-bit frame (master-to-slave)
MSB
LSB
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
Table 16: Fault 8-bit frame (slave-to-master)
MSB
LSB
F7
F6
F5
F4
F3
F2
F1
F0
10.2 16-bit SPI mode (SEL1 = H)
The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to
the IC; the first 8 bits directly drive the output channels (each bit, set to ‘1’, activates the
corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit
(the inversion of the previous one) is used to detect a communication error condition
(providing at least a transition in each frame):
P0 = IN0 +IN1+ IN2 +IN3 +IN4+ IN5+ IN6 +IN7
P1 = IN1 + IN3 + IN5 + IN7
P2 = IN0 + IN2 + IN4 + IN6
nP0 = not P0
Table 17: Command 16-bit frame (master-to-slave)
MSB
LSB
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
P2
P1
P0
nP0
At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first
8 bits indicate a channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event),
the following 4 bits provide general fault condition information. FB_OK: this bit is related to
the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB
rises above 90% of the nominal VFB voltage and a correct SPI communication occurred. If
the FB voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC
warning case temperature), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the
length is not a multiple of 8) and PG (Power Good, see Section 9.10: "Power Good
SPI operation (SEL2 = H)
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(PG)"). The last 4 bits are used as parity check bits and communication error condition (see
command 16-bit frame):
P0 = F0+ F1+ F2 + F3 + F4 + F5 + F6 + F7
P1 = PC+ FB_OK + F1 + F3 + F5 + F7
P2 = PG + TWARN + F0 + F2 + F4 + F6
nP0 = not P0
Table 18: Fault 16-bit frame (slave-to-master)
MSB
LSB
F7
F6
F5
F4
F3
F2
F1
F0
FB_OK
TWARN
PC
PG
P2
P1
P0
nP0
Channel indications are latched and cleared after a communication only.
VNI8200XP-32
LED driving array
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11 LED driving array
The LED driving array carries out the status of the output channels (ON or OFF).
Figure 9: LED driving array
The following equation is an indication how to choose the Rext resistor value:
Rext= (VCOLmin.) - (VROWmax.)- VF(LED) / IF(LED)
where IF(LED) ≤ 7 mA and (VCOL min.) and (VROW max.) can be found in Table 11: "LED
driving array" and VF(LED) and IF(LED) depend on the electrical characteristics of the LEDs.
Step-down switching regulator
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12 Step-down switching regulator
The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The
regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current
limit regulation is obtained in normal operation through a current loop control.
A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage
ripple; a low ESR (less than 10 mΩ) capacitor is preferable. The control loop pin FB allows
3.3 V to be regulated, connecting it directly to VREG, or 5 V connecting it through a voltage
divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to
the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage
externally or, in the case of two or more VNI8200XP-32 inside the same board, it's possible
to configure the DC-DC converter on only one device and also supply the other ICs.
if the DC-DC converter is adjusted to provide 3.3 V regulation and the VDC_out is used to
power an external load and not the device, a 33 kΩ resistor has to be connected on VDC_out
pin.
VNI8200XP-32
Typical circuits and conventions
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13 Typical circuits and conventions
Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V
Typical circuits and conventions
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Figure 11: Typical circuit for switching regulation VDC-out = 5 V
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Typical circuits and conventions
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Figure 12: SPI directional logic convention
SDI
SS
CLK
SDO
WD
OUT_EN
WD_EN
SEL1
SEL2
PG
FAULT
TWARN
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
VREG
TAB=Vcc
GIPG030420151337LM
Thermal management
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14 Thermal management
The power dissipation in the IC is the main factor that sets the safe operating condition of
the device in the application. Therefore, it must be taken into account very carefully.
Heatsinking can be achieved using copper on the PCB with proper area and thickness. The
following image shows the junction-to-ambient thermal impedance values for the
PowerSSO-36 package.
Figure 13: PowerSSO-36 thermal impedance vs. time
For instance, three cases have been considered using a PowerSSO-36 packaged with
copper slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper
thickness of 70 µm):
single layer PCB with just IC footprint dissipating area
double layer PCB with footprint dissipating area on the top side and a 2 cm2
dissipating layer on the bottom side through 15 via holes
double layer PCB with footprint dissipating area on the top side and an 8 cm2
dissipating layer on the bottom side through 15 via holes
VNI8200XP-32
Thermal management
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14.1 Thermal behavior
Figure 14: Thermal behavior
1 Thermal shutdown
2 Junction hysteresis
3 Restore to idle condition
4 Case hysteresis
Interface timing diagram
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15 Interface timing diagram
Figure 15: Serial timing
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Switching parameter test conditions
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16 Switching parameter test conditions
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions
Figure 17: td(ON) and td(OFF) time diagram test conditions
Package information
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17 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
17.1 PowerSSO-36 package information
Figure 18: PowerSSO-36 package outline
7587131 rev9
VNI8200XP-32
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Figure 19: PowerSSO-36 package outline details
Figure 20: PowerSSO-36 package outline details (section B-B)
Not in scale (section A-A)
Not in scale (section B-B)
Package information
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Table 19: PowerSSO-36 mechanical data
Dim.
mm
Min.
Typ.
Max.
ɵ
0°
8°
ɵ1
5°
10°
ɵ2
0°
A
2.15
2.45
A1
0.00
0.10
A2
2.15
2.35
b
0.18
0.32
b1
0.13
0.25
0.30
c
0.23
0.32
c1
0.20
0.20
0.30
D
10.30 BSC
D1
7.00
7.40
D2
3.65
4.200
D3
4.30
e
0.50 BSC
E
10.30 BSC
E1
7.50 BSC
E2
4.20
4.60
E3
2.30
E4
2.90
G1
1.20
G2
1.00
G3
0.80
h
0.30
0.40
L
0.60
0.70
0.85
L1
1.40 REF
L2
0.25 BSC
N
36
R
0.30
R1
0.20
S
0.25
VNI8200XP-32
Package information
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17.2 Packing information
Figure 21: PowerSSO-36 tube shipment outline
Table 20: PowerSSO-36 tube shipment mechanical data
Description
Value
Base quantity
49
Bulk quantity
1225
Tube lenght (± 0.5)
532
A
3.5
B
13.8
C (± 0.1)
0.6
All dimensions are in mm
Package information
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Figure 22: PowerSSO-36 tape dimension outline
Table 21: PowerSSO-36 tape dimension mechanical data
Description
Dimensions
Value
Tape width
W
24
Tape hole spacing
P0 (± 0.1)
4
Component spacing
P
12
Hole diameter
D (± 0.05)
1.55
Hole diameter
D1 (min.)
1.5
Hole position
F (± 0.1)
11.5
Compartment depth
K (max.)
2.85
Hole spacing
P1 (± 0.1)
2
According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb
1986
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Figure 23: PowerSSO-36 reel shipment outline
Table 22: PowerSSO-36 reel dimension mechanical data
Description
Value
Base quantity
1000
Bulk quantity
1000
A max.
330
B min.
1.5
C (± 0.2)
13
F
20.2
G (2 ± 0)
24.4
N min.
100
T min.
30.4
Revision history
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18 Revision history
Table 23: Document revision history
Date
Revision
Changes
08-May-2015
1
Initial release.
09-Jun-2015
2
Updated VCC supply current parameter in table 5 and
updated VPGH1, VPGH2, VUSD, IPEAK, ILIM and Hyst
parameters in table 9.
24-Aug-2015
3
Updated programmable watchdog time table.
Datasheet status promoted from preliminary data to
production data.
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