Freescale Semiconductor
Data Sheet: Technical Data Document Number: MPC5602D
Rev. 6, 01/2013
© Freescale Semiconductor, Inc., 2009–2013. All rights reserved.
This document contains information on a new product. S pecifications and information herein
are subject to change without notice.
MPC5602D
100 LQFP
14 mm x 14 mm 64 LQFP
10 mm x 10 mm
• Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture®
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. W ith the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
• Up to 256 KB on-chip Code Flash supported wi th
Flash controller and ECC
• 64 KB on-chip Data Flash with ECC
• Up to 16 KB on-chip SRAM with ECC
• Interrupt controller (INTC) with multiple interrupt
vectors, including 20 external interrupt sources and
18 external interrupt/wak eup sources
• Frequency modulated phase-locked lo op (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, Flash, or SRAM from multiple bus
masters
• Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulati on fu nctions (eMIOS-lite)
• Up to 33 channel 12-bit analog-to-digital converter
(ADC)
• 2 serial peripheral interface (DSPI) modules
• 3 serial communication interface (LINFlex) modules
— LINFlex 1 and 2: Master capable
— LINFlex 0: Master capable and slave capable;
connected to eDMA
• 1 enhanced full CAN (FlexCAN) module with
configurable buffers
• Up to 79 configurable general purpose pins
supporting input and output operations (package
dependent)
• Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
• Up to 4 periodic interrupt timers (PIT) with 32-b it
counter resolution
• 1 System Timer Module (STM)
• Nexus development interface (NDI) per IEEE-IST O
5001-2003 Class 1 standard
• Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
• On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
MPC5602D Microcontroller
Data Sheet
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor2
Table of Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Pad configuration during reset phases . . . . . . . . . . . . . .9
3.3 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .22
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.3 NVUSRO[WATCHDOG_EN] field description . .22
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
4.5 Recommended operating conditions . . . . . . . . . . . . . .23
4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .26
4.6.1 Package thermal characteristics . . . . . . . . . . . .26
4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . .26
4.7 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .27
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.7.2 I/O input DC characteristics. . . . . . . . . . . . . . . .27
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .28
4.7.4 Output pin transition times. . . . . . . . . . . . . . . . .31
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .31
4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .35
4.9 Power management electrical characteristics. . . . . . . .37
4.9.1 Voltage regulator electrical characteristics . . . .37
4.9.2 Low voltage detector electrical characteristics .40
4.10 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11 Flash memory electrical characteristics. . . . . . . . . . . . 42
4.11.1 Program/Erase characteristics. . . . . . . . . . . . . 42
4.11.2 Flash power supply DC characteristics . . . . . . 44
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 45
4.12 Electromagnetic compatibility (EMC) characteristics. . 45
4.12.1 Designing hardened software to avoid
noise problems. . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 46
4.12.3 Absolute maximum ratings (electrical sensitivity)46
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 51
4.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 54
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.17.2 Input impedance and ADC accuracy . . . . . . . . 55
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 60
4.18 On-chip peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 62
4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 63
4.18.3 JTAG characteristics . . . . . . . . . . . . . . . . . . . . 70
5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 70
5.1.1 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.2 64 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Introduction
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 3
1 Introduction
1.1 Document overview
This document describes the device features and highlights the important electrical and physical characteristics.
1.2 Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the
development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body , door control
and seat control applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power
Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing
improved code density . It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with softwa re drivers, oper a ting systems and config uration code to assist with the user’s implementations.
The device platform has a single level of m e mory hierarchy and can support a wide range of on-chip static random access
memory (SRAM) and internal flash memory.
Table 1. MPC5602D device comparison
Feature Device
MPC5601DxLH MPC5601DxLL MPC5602DxLH MPC5602DxLL
CPU e200z0h
Execution speed Static – up to 48 MHz
Code flash memory 128 KB 256 KB
Data flash memory 64 KB (4 × 16 KB)
SRAM 12 KB 16 KB
eDMA 16 ch
ADC (12-bit) 16 ch 33 ch 16 ch 33 ch
CTU 16 ch
Tot al timer I/O1
eMIOS 14 ch, 16-b it 28 ch, 16-bit 14 ch, 16-bit 28 ch, 16-bit
• Type X22ch 5ch 2ch 5ch
• Type Y3—9ch—9ch
• Type G47ch 7ch 7ch 7ch
• Type H54ch 7ch 4ch 7ch
SCI (LINFlex) 3
SPI (DSPI) 2
CAN (FlexCAN) 1
GPIO645 79 45 79
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Block di agram
Freescale Semiconductor4
2 Block diagram
Figure 1 shows a top-level block diagram of the MPC5602D device series.
Debug JTAG
Package 64 LQFP 100 LQFP 64 LQFP 100 LQFP
1Refer to eMIOS chapter of device reference manual for information on the channel confi guration and functions.
2Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC
3Type Y = OPWMT + OPWMB + SAIC + SAOC
4Type G = MCB + IPW M + I P M + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC
5Type H = IPW M + I P M + DAOC + OPWMT + OPWMB + SAIC + SAOC
6I/O count based on multiplexing with peripherals
Table 1. MPC5602D device comparison (continued)
Feature Device
MPC5601DxLH MPC5601DxLL MPC5602DxLH MPC5602DxLL
Block diagram
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 5
Figure 1. MPC5602D series block diagra m
Table 2 summarizes the functions of all blocks present in the MPC 5602D series of microcontrollers. Please note that the
presence and number of blocks varies by device and package.
2 x
DSPI
FMPLL
Nexus 1
SRAM
SIUL
Reset Control
16 KB
External
IMUX
GPIO &
JTAG
Pad Control
JTAG Port
e200z0h
Interrupt requests
64-bit 3 x 3 Crossbar Switch
1 x
FlexCAN
Peripheral Bridge
Interrupt
Request
Interrupt
Request
I/O
Clocks
Instructions
Data
Voltage
Regulator
NMI
SWT PITSTM
NMI
SIUL
. . . . . . . . .
. . .
INTC
3 x
LINFlex
1 x
eMIOS
33 ch.
ADC
CMU
SRAM Flash
Code Flash
256 KB Data Flash
64 KB
MC_PCUMC_MEMC_CGMMC_RGM BAM
CTU
RTC SSCM
(Master)
(Master)
(Slave)
(Slave)
(Slave)
Controller
Controller
Legend:
ADC Analog-to-Digital Converter
BAM Boot Assist Module
CMU Clock Monitor Unit
CTU Cross Triggering Unit
DSPI Deserial Serial Peripheral Interface
ECSM Error Correction Status Module
eDMA Enhanced Direct Memory Access
eMIOS Enhanced Modular Input Output System
Flash Flash memory
FlexCAN Controller Area Network (FlexCAN )
FMPLL Frequency-Modulated Phase-Locked Loop
IMUX Internal Multiple xe r
INTC Interrupt Cont r oller
JTAG JTAG controller
LINFlex Serial Communication Interface (LIN support)
MC_CGM Clock Generation Module
MC_ME Mode Entry Module
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
NMI Non-Maskable Interrupt
PIT Periodic Interrupt Timer
RTC Real-Time Clock
SIUL System Integration Unit Lite
SRAM Static Random-Access Memory
SSCM System Status Configuration Modu le
STM System Timer Module
SWT Software Watchdog Timer
WKPU Wakeup Unit
XBAR Crossbar switch
eDMA
ECSM
from peripheral
blocks
WKPU
Request
Interrupt
Request
(Master)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Block di agram
Freescale Semiconductor6
Table 2. MPC5602D series block summary
Block Function
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM) Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU) Monitors clock source (internal and external) integrity
Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR) Supports sim ultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral interface
(DSPI) Provides a synchronous serial interface for communication with external devices
Enhanced direct memory access
(eDMA) Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels.
Enhanced modular inpu t output
system (eMIOS) Provides the functiona lity to generate or measure events
Error correction status module
(ECSM) Pro vides a myriad of miscellaneous control functions for the device includi ng
program-visible information about configuration an d revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional featu res
such as information on memory errors reported by error-correcting codes
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock Allows flexible mapping of peripheral interface on the different pins of the device
Interrupt controller (INTC) Provides priority-based preemptive scheduli ng of interrupt requests
JTAG controller (JTAGC) Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Mode entry module (MC_ME) Provides a mechanism for co ntrolling the device oper ational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-maskable interrupt (NMI) H andles external events that must produce an immediate response, such as
power down detection
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Power control unit (MC_PCU) Reduces the overall power consumption by disconnectin g parts of the device
from the power supply via a power switching device; de vice components are
grouped into sections called “power domains” which are controlled by the PCU
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 7
3 Package pinouts and signal descriptions
3.1 Package pinouts
The available LQFP pinouts are provided in the followin g figures. For pin signal descrip tions, please refer to Table 5.
Real-time counter (RTC) Provides a free-running counter and interrupt generation capability that can be
used for timekeeping applications
Reset generation module
(MC_RGM) Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM) Pro vi des storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM) Provides system configuration and status dat a (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM) Provides a set of output compare events to support AUTOSAR (Automotive
Open System Architecture) and operating system tasks
Software watchdog timer (SWT) Provides protection from runaway code
Wakeup unit (WKPU) Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup events.
Table 2. MPC5602D series block summary (continued)
Block Function
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor8
Figure 2 shows the MPC5602D in the 100 LQFP package.
Figure 2. 100 LQFP pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
100 LQFP
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 9
Figure 3 shows the MPC5602D in the 64 LQFP package.
Figure 3. 64 LQFP pin configuration (top view)
3.2 Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
• PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
• PA[8] (ABS[0]) is pull-up.
• RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
• JTAG pads (TCK, TMS and TDI) are pull-up while TDO remains tristate.
• Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
• Main oscillator pads (EXTAL, XTAL) are tristate.
3.3 Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PB[1]
PC[6]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[3]
PB[15]
PB[14]
PB[13]
PB[12]
PB[11]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PB[4]
PB[2]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
64 LQFP
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor10
3.4 Pad types
In the device the following types of pads are availabl e for system pins and functi onal port pins:
S = Slow1
M = Medium1 2
F = Fast1 2
I = Input only with analog feature1
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
3.5 System pins
The system pins are listed in Table 4.
Table 3. Voltage supply pin descriptions
Port pin Function Pin number
64 LQFP 100 LQFP
VDD_HV Digital supply voltage 7, 28, 34, 56 15, 37, 52, 70, 84
VSS_HV Digital ground 6, 8, 26, 33, 55 14, 16, 35, 51, 69, 83
VDD_LV 1.2V decoupling pi ns. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV pin.1
1A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the devi ce datasheet fo r details).
11, 23, 57 19, 32, 85
VSS_LV 1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV pin.110, 24, 58 18, 33, 86
VDD_BV Internal regulator supply voltage 12 20
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by defaul t at reset and can be configured as fast or medium (see the
PCR[SRC] description in the device reference manual).
Table 4. System pin descriptions
Port pin Function I/O
direction Pad type RESET
configuration
Pin number
64 LQFP 100 LQFP
RESET Bidirectional reset with Schmitt-T rigger
characteristics an d noise filter. I/O M Input, weak
pull-up only
after PHASE2
917
EXT AL Analog output of the oscillator amplifier circuit,
when the oscillator is not in bypass mode.
Analog input for the clock generator when the
oscillator is in bypass mode.1
1Refer to the relevant section of the device datasheet.
I/O X Tristate 27 36
XTAL Analog input of the oscillator amplifier circuit.
Needs to be grounded if oscillator is used in
bypass mode.1
I X Tristate 25 34
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 11
3.6 Functional ports
The functional port pins are listed in Table 5.
Table 5. Functional port pin descriptions
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Port A
PA[0] PCR[0] AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]3
SIUL
eMIOS_0
CGL
eMIOS_0
WKPU
I/O
I/O
O
I/O
I
MTristate 5 12
PA[1] PCR[1] AF0
AF1
AF2
AF3
—
—
GPIO[1]
E0UC[1]
—
—
NMI4
WKPU[2]3
SIUL
eMIOS_0
—
—
WKPU
WKPU
I/O
I/O
—
—
I
I
S Tristate 4 7
PA[2] PCR[2] AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3]3
SIUL
eMIOS_0
—
ADC
WKPU
I/O
I/O
—
O
I
S Tristate 3 5
PA[3] PCR[3] AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
—
CS4_0
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
—
DSPI_0
SIUL
ADC
I/O
I/O
—
I/O
I
I
S Tristate 43 68
PA[4] PCR[4] AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
CS0_1
WKPU[9]3
SIUL
eMIOS_0
—
DSPI_1
WKPU
I/O
I/O
—
I/O
I
S Tristate 20 29
PA[5] PCR[5] AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M Tristate 51 79
PA[6] PCR[6] AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
SIUL
I/O
I/O
—
I/O
I
S Tristate 52 80
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor12
PA[7] PCR[7] AF0
AF1
AF2
AF3
—
—
GPIO[7]
E0UC[7]
—
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
—
—
SIUL
ADC
I/O
I/O
—
—
I
I
S Tristate 44 71
PA[8] PCR[8] AF0
AF1
AF2
AF3
—
N/A5
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
I/O
I/O
—
—
I
I
S Input, weak
pull-up 45 72
PA[9] PCR[9] AF0
AF1
AF2
AF3
N/A5
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
I/O
I
S Pull-down 46 73
PA[10] PCR[10] AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
—
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
—
LINFlex_2
ADC
I/O
I/O
—
O
I
S Tristate 47 74
PA[11] PCR[11] AF0
AF1
AF2
AF3
—
—
—
GPIO[11]
E0UC[11]
—
—
EIRQ[16]
ADC1_S[3]
LIN2RX
SIUL
eMIOS_0
—
—
SIUL
ADC
LINFlex_2
I/O
I/O
—
—
I
I
I
S Tristate 48 75
PA[12] PCR[12] AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
—
—
EIRQ[17]
SIN_0
SIUL
—
—
—
SIUL
DSPI_0
I/O
—
—
—
I
I
S Tristate 22 31
PA[13] PCR[13] AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
—
CS3_1
SIUL
DSPI_0
—
DSPI_1
I/O
O
—
I/O
M Tristate 21 30
PA[14] PCR[14] AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M Tristate 19 28
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 13
PA[15] PCR[15] AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10]3
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
I/O
I/O
I
M Tristate 18 27
Port B
PB[0] PCR[16] AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
—
LIN2TX
SIUL
FlexCAN_0
—
LINFlex_2
I/O
O
—
O
M Tristate 14 23
PB[1] PCR[17] AF0
AF1
AF2
AF3
—
—
GPIO[17]
—
—
LIN0RX
WKPU[4]3
CAN0RX
SIUL
—
—
LINFlex_0
WKPU
FlexCAN_0
I/O
—
—
I
I
I
S Tristate 15 24
PB[2] PCR[18] AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
—
—
SIUL
LINFlex_0
—
—
I/O
O
—
—
M Tristate 64 100
PB[3] PCR[19] AF0
AF1
AF2
AF3
—
—
GPIO[19]
—
—
—
WKPU[11]3
LIN0RX
SIUL
—
—
—
WKPU
LINFlex_0
I/O
—
—
—
I
I
S Tristate 1 1
PB[4] PCR[20] AF0
AF1
AF2
AF3
—
GPIO[20]
—
—
—
ADC1_P[0]
SIUL
—
—
—
ADC
I
—
—
—
I
I Tristate 32 50
PB[5] PCR[21] AF0
AF1
AF2
AF3
—
GPIO[21]
—
—
—
ADC1_P[1]
SIUL
—
—
—
ADC
I
—
—
—
I
I Tristate 35 53
PB[6] PCR[22] AF0
AF1
AF2
AF3
—
GPIO[22]
—
—
—
ADC1_P[2]
SIUL
—
—
—
ADC
I
—
—
—
I
I Tristate 36 54
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor14
PB[7] PCR[23] AF0
AF1
AF2
AF3
—
GPIO[23]
—
—
—
ADC1_P[3]
SIUL
—
—
—
ADC
I
—
—
—
I
I Tristate 37 55
PB[8] PCR[24] AF0
AF1
AF2
AF3
—
—
GPIO[24]
—
—
—
ADC1_S[4]
WKPU[25]3
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I Tristate 30 39
PB[9] PCR[25] AF0
AF1
AF2
AF3
—
—
GPIO[25]
—
—
—
ADC1_S[5]
WKPU[26]3
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I Tristate 29 38
PB[10] PCR[26] AF0
AF1
AF2
AF3
—
—
GPIO[26]
—
—
—
ADC1_S[6]
WKPU[8]3
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
I
J Tristate 31 40
PB[11] PCR[27] AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC1_S[12]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
I/O
I
J Tristate 38 59
PB[12] PCR[28] AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC1_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J Tristate 39 61
PB[13] PCR[29] AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC1_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J Tristate 40 63
PB[14] PCR[30] AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC1_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J Tristate 41 65
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 15
PB[15] PCR[31] AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC1_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J Tristate 42 67
Port C
PC[0]6PCR[32] AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M Input, weak
pull-up 59 87
PC[1]6PCR[33] AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F Tristate 54 82
PC[2] PCR[34] AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
—
—
EIRQ[5]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
M Tristate 50 78
PC[3] PCR[35] AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
—
EIRQ[6]
SIUL
DSPI_1
ADC
—
SIUL
I/O
I/O
O
—
I
S Tristate 49 77
PC[4] PCR[36] AF0
AF1
AF2
AF3
—
—
GPIO[36]
—
—
—
SIN_1
EIRQ[18]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
M Tristate 62 92
PC[5] PCR[37] AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
M Tristate 61 91
PC[6] PCR[38] AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
—
—
SIUL
LINFlex_1
—
—
I/O
O
—
—
S Tristate 16 25
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor16
PC[7] PCR[39] AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
—
—
LIN1RX
WKPU[12]3
SIUL
—
—
—
LINFlex_1
WKPU
I/O
—
—
—
I
I
S Tristate 17 26
PC[8] PCR[40] AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlex_2
eMIOS_0
—
I/O
O
I/O
—
S Tristate 63 99
PC[9] PCR[41] AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
E0UC[7]
—
LIN2RX
WKPU[13]3
SIUL
—
eMIOS_0
—
LINFlex_2
WKPU
I/O
—
I/O
—
I
I
S Tristate 2 2
PC[10] PCR[42] AF0
AF1
AF2
AF3
GPIO[42]
—
—
MA[1]
SIUL
—
—
ADC
I/O
—
—
O
M Tristate 13 22
PC[11] PCR[43] AF0
AF1
AF2
AF3
—
GPIO[43]
—
—
MA[2]
WKPU[5]3
SIUL
—
—
ADC
WKPU
I/O
—
—
O
I
STristate — 21
PC[12] PCR[44] AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
MTristate — 97
PC[13] PCR[45] AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
STristate — 98
PC[14] PCR[46] AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
—
—
EIRQ[8]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
S Tristate — 3
PC[15] PCR[47] AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
—
—
EIRQ[20]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M Tristate — 4
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 17
Port D
PD[0] PCR[48] AF0
AF1
AF2
AF3
—
—
GPIO[48]
—
—
—
WKPU[27]3
ADC1_P[4]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
ITristate — 41
PD[1] PCR[49] AF0
AF1
AF2
AF3
—
—
GPIO[49]
—
—
—
WKPU[28]3
ADC1_P[5]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
ITristate — 42
PD[2] PCR[50] AF0
AF1
AF2
AF3
—
GPIO[50]
—
—
—
ADC1_P[6]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 43
PD[3] PCR[51] AF0
AF1
AF2
AF3
—
GPIO[51]
—
—
—
ADC1_P[7]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 44
PD[4] PCR[52] AF0
AF1
AF2
AF3
—
GPIO[52]
—
—
—
ADC1_P[8]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 45
PD[5] PCR[53] AF0
AF1
AF2
AF3
—
GPIO[53]
—
—
—
ADC1_P[9]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 46
PD[6] PCR[54] AF0
AF1
AF2
AF3
—
GPIO[54]
—
—
—
ADC1_P[10]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 47
PD[7] PCR[55] AF0
AF1
AF2
AF3
—
GPIO[55]
—
—
—
ADC1_P[11]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 48
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor18
PD[8] PCR[56] AF0
AF1
AF2
AF3
—
GPIO[56]
—
—
—
ADC1_P[12]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 49
PD[9] PCR[57] AF0
AF1
AF2
AF3
—
GPIO[57]
—
—
—
ADC1_P[13]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 56
PD[10] PCR[58] AF0
AF1
AF2
AF3
—
GPIO[58]
—
—
—
ADC1_P[14]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 57
PD[11] PCR[59] AF0
AF1
AF2
AF3
—
GPIO[59]
—
—
—
ADC1_P[15]
SIUL
—
—
—
ADC
I
—
—
—
I
ITristate — 58
PD[12] PCR[60] AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC1_S[8]
SIUL
DSPI_0
eMIOS_0
—
ADC
I/O
O
I/O
—
I
JTristate — 60
PD[13] PCR[61] AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC1_S[9]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
I/O
I/O
—
I
JTristate — 62
PD[14] PCR[62] AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ADC1_S[10]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
JTristate — 64
PD[15] PCR[63] AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ADC1_S[11]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
JTristate — 66
Port E
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Package pinouts and signal descriptions
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 19
PE[0] PCR[64] AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
—
WKPU[6]3
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S Tristate — 6
PE[1] PCR[65] AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M Tristate — 8
PE[2] PCR[66] AF0
AF1
AF2
AF3
—
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
—
I
I
MTristate — 89
PE[3] PCR[67] AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
MTristate — 90
PE[4] PCR[68] AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
MTristate — 93
PE[5] PCR[69] AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC
I/O
I/O
I/O
O
MTristate — 94
PE[6] PCR[70] AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
MTristate — 95
PE[7] PCR[71] AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
MTristate — 96
PE[8] PCR[72] AF0
AF1
AF2
AF3
GPIO[72]
—
E0UC[22]
—
SIUL
—
eMIOS_0
—
I/O
—
I/O
—
M Tristate — 9
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package pinouts and signal descriptions
Freescale Semiconductor20
PE[9] PCR[73] AF0
AF1
AF2
AF3
—
GPIO[73]
—
E0UC[23]
—
WKPU[7]3
SIUL
—
eMIOS_0
—
WKPU
I/O
—
I/O
—
I
STristate — 10
PE[10] PCR[74] AF0
AF1
AF2
AF3
—
GPIO[74]
—
CS3_1
—
EIRQ[10]
SIUL
—
DSPI_1
—
SIUL
I/O
—
O
—
I
STristate — 11
PE[11] PCR[75] AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
—
WKPU[14]3
SIUL
eMIOS_0
DSPI_1
—
WKPU
I/O
I/O
O
—
I
STristate — 13
PE[12] PCR[76] AF0
AF1
AF2
AF3
—
—
GPIO[76]
—
—
—
ADC1_S[7]
EIRQ[11]
SIUL
—
—
—
ADC
SIUL
I/O
—
—
—
I
I
STristate — 76
Port H
PH[9]6PCR[121] AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S Input, weak
pull-up 60 88
PH[10]6PCR[122] AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
S Input, weak
pull-up 53 81
1Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 AF0; PCR.P A = 01 AF1; PCR.PA = 10 AF2; PCR.P A = 1 1 AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3All WKPU pins also support external interrupt capability . See “wakeup unit” chapter of the device reference manual
for further details.
4NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
5“Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of
the device reference manual for details.
Table 5. Functional port pin descriptions (continued)
Port pin PCR Alternate
function1Function Peripheral I/O
direction2Pad
type
RESET
configuration
Pin numbe r
64 LQFP 100 LQFP
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 21
4 Electrical characteristics
4.1 Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However , it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the
internal pull-up or pull-down, which is provided by the product for m ost general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.2 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the custom er a better
understanding, the classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables where
appropriate.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3 NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical
parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after
reset).
For a detailed desc ri ption of the NVUSRO register, please refer to the device reference manual.
6Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1 2001.
Tab le 6. Parameter cl as si fic a ti on s
Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design charac terization by measuring a statistically
relevant sample size across process variations.
T Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D Those parameters are derived mainly from simulations.
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor22
4.3.1 NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the P AD3V5V bit value. Table 7 shows how NVUSRO[PAD3V5V] controls
the device configuration.
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 8 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
4.3.3 NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 8 shows how
NVUSRO[WATC HDOG_EN] controls the device configuration.
4.4 Absolute maximum ratings
Table 7. PAD3V5V field description
Value1
1Default manufacturing value is ‘1’. Value c an be programmed by customer in Shadow Flash.
Description
0 High voltage supply is 5.0 V
1 High voltage supply is 3.3 V
Table 8. OSCILLATOR_MARGIN field description
Value1
1Default manufacturing value is ‘1’. Value c an be programmed by customer in Shadow Flash.
Description
0 Low consumption configuration (4 MHz/8 MHz)
1 High margin configuration (4 MHz/16 MHz)
Table 9. WATCHDOG_EN field description
Value1
1Default manufacturing value is ‘1’. Value c an be programmed by customer in Shadow Flash.
Description
0 D isa b l e after reset)
1 Ena ble after reset
Table 10. Absolute maximum ratings
Symbol Parameter Conditions Value Unit
Min Max
VSS SR Digital ground on VSS_HV pins — 0 0 V
VDD SR Voltage on VDD_HV pins with respect to
ground (VSS)—0.3 6.0 V
VSS_LV SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)—V
SS 0.1 VSS +0.1 V
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 23
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maxi mum rating conditions fo r
extended periods may affect device reliability. During overload conditions (VIN >V
DD or
VIN <V
SS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
4.5 Recommended operating conditions
VDD_BV SR V olt age on VDD_BV (regulator supply) pin
with respect to ground (VSS)—0.3 6.0 V
Relative to VDD VDD 0.3 VDD +0.3
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground (VSS)—V
SS 0.1 VSS +0.1 V
VDD_ADC SR Voltage on VDD_HV_A DC (ADC
reference) pin with respect to ground (VSS)—0.3 6.0 V
Relative to VDD VDD 0.3 VDD +0.3
VIN SR Voltage on any GPIO pin with respect to
ground (VSS)—0.3 6.0 V
Relative to VDD VDD 0.3 VDD +0.3
IINJPAD SR Injected input current on any pin during
overload condition —10 10 mA
IINJSUM SR Absolute sum of all injected input current s
during overlo ad condition —50 50 mA
IAVGSEG SR Sum of all the static I/O current within a
supply segment1VDD = 5.0 V ± 10%, PAD3V5V = 0 — 70 mA
VDD = 3.3 V ± 10%, PAD3V5V = 1 — 64
ICORELV SR Low voltage static current sink through
VDD_BV ——150mA
TSTORAGE SR Storage temperature — 55 150 °C
1Supply segments are described in Section 4.7.5, I/O pad current specification.
Table 11. Recommended operating condit ions (3.3 V)
Symbol C Parameter Conditions Value Unit
Min Max
VSS SR — Digital ground on VSS_HV pins — 0 0 V
VDD1SR — Voltage on VDD_HV pins with respect to ground
(VSS)—3.03.6V
VSS_LV2SR — Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)—V
SS 0.1 VSS +0.1 V
Table 10. Absolute maximum ratings (continued)
Symbol Parameter Conditions Value Unit
Min Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor24
VDD_BV3SR — Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)—3.03.6V
Relative to VDD VDD 0.1 VDD +0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)—V
SS 0.1 VSS +0.1 V
VDD_ADC4SR — Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)—3.0
53.6 V
Relative to VDD VDD 0.1 VDD +0.1
VIN SR — Voltage on any GPIO pin with respect to ground
(VSS)—V
SS 0.1 — V
Relative to VDD —V
DD +0.1
IINJPAD SR — Injected input current on any pin during overload
condition —55mA
IINJSUM SR — Absolute sum of all injected input currents during
overload condition —50 50 mA
TVDD SR — VDD slope to ensure correct power up6— — 0.25 V/µs
TA C-Grade
Part
SR — Ambient temperature under bias fCPU 48 MHz 40 85 °C
TJ C-Grade
Part
SR — Junction temperature under bias 40 110
TA V -Grade
Part
SR — Ambient temperature under bias 40 105
TJ V -Grade
Part
SR — Junction temperature under bias 40 130
TA M-Grade
Part
SR — Ambient temperature under bias 40 125
TJ M-Grade
Part
SR — Junction temperature under bias 40 150
1100 nF capacitance needs to be provided between each VDD/VSS pair.
2330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
3470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
5Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
6Guaranteed by device validation
Table 12. Recommended operating conditions (5.0 V)
Symbol C Parameter Conditions Value Unit
Min Max
VSS SR — Digital ground on VSS_HV pins — 0 0 V
Table 11. Recommended operating conditions (3 .3 V) (continued)
Symbol C Parameter Conditions Value Unit
Min Max
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 25
VDD1SR — Voltage on VDD_HV pins with respect to ground
(VSS)—4.55.5V
Voltage drop23.0 5.5
VSS_LV3SR — V oltage on VSS_L V (low voltage digital supply) pins
with respect to ground (VSS)—V
SS 0.1 VSS +0.1 V
VDD_BV4SR — Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)—4.55.5V
Voltage drop(2) 3.0 5.5
Relative to VDD VDD 0.1 VDD +0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with
respect to ground (VSS
—V
SS 0.1 VSS +0.1 V
VDD_ADC5SR — Voltage on VDD_HV_ADC pin (ADC reference) with
respect to ground (VSS)—4.55.5V
Voltage drop(2) 3.0 5.5
Relative to VDD VDD 0.1 VDD +0.1
VIN SR — Voltage on any GPIO pin with respect to ground
(VSS)—V
SS 0.1 — V
Relative to VDD —V
DD +0.1
IINJPAD SR — Injected input current on any pin during overload
condition —55mA
IINJSUM SR — Absolute sum of all injected input currents during
overload condition —50 50 mA
TVDD SR — VDD slope to ensure co rrect power up6— — 0.25 V/µs
TA C-Grade
Part
SR — Ambient temperature under bias fCPU 48 MHz 40 85 °C
TJ C-Grade
Part
SR — Junction temperature und er bias 40 110
TA V -Grade
Part
SR — Ambient temperature under bias 40 105
TJ V-Grade
Part
SR — Junction temperature und er bias 40 130
TA M-Grade
Part
SR — Ambient temperature under bias 40 125
TJ M-Grade
Part
SR — Junction temperature und er bias 40 150
1100 nF capacitance needs to be provided between each VDD/VSS pa ir.
2Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However , certain
analog electrical characteristi cs wil l not be guaranteed to stay within the stated limits.
3330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6Guaranteed by device validation
Table 12. Recommended operating conditions (5.0 V) (continued)
Symbol C Parameter Conditions Value Unit
Min Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor26
NOTE
SRAM data retention is guaranteed wit h VDD_LV not below 1.08 V.
4.6 Thermal characteristics
4.6.1 Package thermal characteristics
4.6.2 Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
Table 13. LQFP thermal characteristics1
1Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Symbol C Parameter Conditions2
2VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = –40 to 125 °C
Value Unit
RJA CC D Thermal resistance, junction-to-ambient natural
convection3
3Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-7. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA.
Single-layer board —1s LQFP64 72.1 °C/W
LQFP100 65.2
Four-layer board — 2s2p LQFP64 57.3
LQFP100 51.8
RJB CC D Thermal resistance, junction-to-board4
4Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB.
Four-layer board — 2s2p LQFP64 44.1 °C/W
LQFP100 41.3
RJC CC D Thermal resistance, junction-to-case5
5Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
When Greek letters are not available, the symbols are typed as RthJC.
Single-layer board — 1s LQFP64 26.5 °C/W
LQFP100 23.9
Four-layer board — 2s2p LQFP64 26.2
LQFP100 23.7
JB CC D Junction-to-board thermal chara c terization
parameter, natural convection Single-layer board — 1s LQFP64 41 °C/W
LQFP100 41.6
Four-layer board — 2s2p LQFP64 43
LQFP100 43.4
JC CC D Junction-to-case thermal characterization
parameter, natural convection Single-layer board — 1s LQFP64 11.5 °C/W
LQFP100 10.4
Four-layer board — 2s2p LQFP64 11.1
LQFP100 10.2
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 27
TJ = TA + (PD x RJA)Eqn. 1
Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O< PINT and may be neglected. On the other hand, PI/O may be significant, if the device
is configured to continuously drive external mo dules and/ or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C) Eqn. 2
Therefore, solving equations 1 and 2:
K = PD x (TA + 273 °C) + RJA x PD2Eqn. 3
Where:
K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equ a tions 1 and 2
iteratively for any value of TA.
4.7 I/O pad electrical characteristics
4.7.1 I/O pad types
The device provides four main I/O pad types depending on the associated alternate functions:
• Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
• Medium pads—These pads provide transiti on fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
• Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing low input leakage.
Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only , at the cost
of reducing AC performance.
4.7.2 I/O input DC characteristics
Table 14 provides input DC electrical characteristics as described in Figure 4.
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor28
Figure 4. Input DC electrical characteristics definition
4.7.3 I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•Table 15 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 14. I/O input DC electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
VIH SR P Input high level CMOS (Schmitt
Trigger) —0.65V
DD —V
DD+0.4 V
VIL SR P Input low level CMOS (Schmitt
Trigger) —0.4 — 0.35VDD V
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger) —0.1V
DD ——V
ILKG CC D Digital input leakage No injection
on adjac en t
pin
TA=40 °C — 2 200 nA
DT
A=25 °C — 2 200
DT
A=85 °C — 5 300
DT
A= 105 °C — 12 500
PT
A= 125 °C — 70 1000
WFI2
2In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
SR P Digital input filtered pulse — — — 40 ns
WNFI(2) SR P Digital input not filtered pulse — 1000 — — ns
VIL
VIN
VIH
PDIx = ‘1’
VDD
VHYS
(GPDI register of SIUL)
PDIx = ‘0’
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 29
•Table 16 provides output driver characteristics for I/O pads when in SLOW configuration.
•Table 17 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 15. I/O pull-up/pull-down DC electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
Value Unit
Min Typ Max
|IWPU| CC P Weak pull -up current
absolute value VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0 10 — 150 µA
C PAD3V5V = 12
2The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
10 — 250
PV
IN = VIL, VDD = 3.3 V ± 10% PAD 3V5V = 1 10 — 150
|IWPD| CC P We ak pull-down current
absolute value VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0 10 — 150 µA
C PAD3V5V = 1(2) 10 — 250
PV
IN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
Table 16. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
VOH CC P Output high level
SLOW configuration Push Pull IOH = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD —— V
CI
OH = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
2The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
0.8VDD ——
CI
OH = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD 0.8 — —
VOL CC P Output low level
SLOW configuration Push Pull IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
— — 0.1VDD V
CI
OL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD
CI
OL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——0.5
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor30
Table 17. MEDIUM configuration output buffer electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 ° C, unless otherwise specified
Value Unit
Min Typ Max
VOH CC C O utput high level
MEDIUM configuration Push Pull IOH = 3.8 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD —— V
PI
OH = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD ——
CI
OH = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
2The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configurat ion during power-up. All pads but
RESET are configured in input or in high impedance state.
0.8VDD ——
CI
OH = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD 0.8 — —
CI
OH = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD ——
VOL CC C Output low level
MEDIUM configuration Push Pull IOL = 3.8 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD V
PI
OL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
— — 0.1VDD
CI
OL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD
CI
OL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——0.5
CI
OL = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 31
4.7.4 Output pin transition times
4.7.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 19.
Table 20 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment sh ould remain below the IAVGSEG
maximum value.
Table 18. Output pin transition times
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
ttr CC D Output transition time output pi n 2
SLOW configuration
2CL includes device and package capacitances (CPKG < 5 pF).
CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 50 ns
TC
L = 50 pF — — 100
DC
L = 100 pF — — 125
DC
L = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 50
TC
L = 50 pF — — 100
DC
L = 100 pF — — 125
ttr CC D Output transition time output
pin(2)
MEDIUM configuration
CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0
SIUL.PCRx.SRC = 1 — — 10 ns
TC
L = 50 pF — — 20
DC
L = 100 pF — — 40
DC
L = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1
SIUL.PCRx.SRC = 1 ——12
TC
L = 50 pF — — 25
DC
L = 100 pF — — 40
Table 19. I/O supply segment
Package Supply segment
1234
100 LQFP pin 16 – pin 35 pin 37 – pin 69 pin 70 – pin 83 pi n 84 – pin 15
64 LQFP pin 8 – pin 26 pin 28 – pin 55 pin 56 – pin 7 —
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor32
Table 21 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below 100%.
Table 20. I/O consumption
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
ISWTSLW,2
2Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
CC D Dynamic I/O current
for SLOW
configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——20mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——16
ISWTMED(2) CC D Dynamic I/O current
for MEDIUM
configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——29mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——17
IRMSSLW CC D Root mean square
I/O current for SLOW
configuration
CL = 25 pF, 2 MHz VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——2.3mA
CL = 25 pF, 4 MHz — — 3.2
CL = 100 pF, 2 MHz — — 6.6
CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1 ——1.6
CL = 25 pF, 4 MHz — — 2.3
CL = 100 pF, 2 MHz — — 4.7
IRMSMED CC D Root mean square
I/O current for
MEDIUM
configuration
CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,
PAD3V5V = 0 ——6.6mA
CL = 25 pF, 40 MHz — — 13.4
CL = 100 pF, 13 MHz — — 18.3
CL = 25 pF, 13 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1 —— 5
CL = 25 pF, 40 MHz — — 8.5
CL = 100 pF, 13 MHz — — 11
IAVGSEG SR D Sum of all the static
I/O current within a
supply segment
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 mA
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 33
Table 21. I/O weight1
Pad
100 LQFP/64 LQFP
Weight 5V Weight 3.3V
SRC2= 0 SRC = 1 SRC = 0 SRC = 1
PB[3] 9% 9% 10% 10%
PC[9] 8% 8% 10% 10%
PC[14] 8% 8% 10% 10%
PC[15] 8% 11% 9% 10%
PA[2]8%8%9%9%
PE[0] 7% 7% 9% 9%
PA[1]7%7%8%8%
PE[1] 7% 10% 8% 8%
PE[8] 6% 9% 8% 8%
PE[9] 6% 6% 7% 7%
PE[10] 6% 6% 7% 7%
PA[0]5%7%6%7%
PE[11] 5% 5% 6% 6%
PC[11] 7% 7% 9% 9%
PC[10] 8% 11% 9% 10%
PB[0] 8% 11% 9% 10%
PB[1] 8% 8% 10% 10%
PC[6] 8% 8% 10% 10%
PC[7] 8% 8% 10% 10%
PA[15] 8% 11% 9% 10%
PA[14] 7% 11% 9% 9%
PA[4]7%7%8%8%
PA[13] 7% 10% 8% 9%
PA[12] 7% 7% 8% 8%
PB[9] 1% 1% 1% 1%
PB[8] 1% 1% 1% 1%
PB[10] 5% 5% 6% 6%
PD[0]1%1%1%1%
PD[1]1%1%1%1%
PD[2]1%1%1%1%
PD[3]1%1%1%1%
PD[4]1%1%1%1%
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor34
PD[5]1%1%1%1%
PD[6]1%1%1%1%
PD[7]1%1%1%1%
PD[8]1%1%1%1%
PB[4] 1% 1% 1% 1%
PB[5] 1% 1% 1% 1%
PB[6] 1% 1% 1% 1%
PB[7] 1% 1% 1% 1%
PD[9]1%1%1%1%
PD[10] 1% 1% 1% 1%
PD[11] 1% 1% 1% 1%
PB[11] 9% 9% 11% 11%
PD[12] 8% 8% 10% 10%
PB[12] 8% 8% 10% 10%
PD[13] 8% 8% 9% 9%
PB[13] 8% 8% 9% 9%
PD[14] 7% 7% 9% 9%
PB[14] 7% 7% 8% 8%
PD[15] 7% 7% 8% 8%
PB[15] 6% 6% 7% 7%
PA[3]6%6%7%7%
PA[7]4%4%5%5%
PA[8]4%4%5%5%
PA[9]4%4%5%5%
PA[10] 5% 5% 6% 6%
PA[11] 5% 5% 6% 6%
PE[12] 5% 5% 6% 6%
PC[3]5%5%6%6%
PC[2]5%7%6%6%
PA[5]5%6%5%6%
PA[6]4%4%5%5%
PC[1] 5% 17% 4% 12%
Table 21. I/O weight1 (continued)
Pad
100 LQFP/64 LQFP
Weight 5V Weight 3.3V
SRC2= 0 SRC = 1 SRC = 0 SRC = 1
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 35
4.8 RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 5. Start-up reset requirements
PC[0]6%9%7%8%
PE[2] 7% 10% 8% 9%
PE[3] 7% 10% 9% 9%
PC[5] 8% 11% 9% 10%
PC[4] 8% 11% 9% 10%
PE[4] 8% 12% 10% 10%
PE[5] 8% 12% 10% 11%
PE[6] 9% 12% 10% 11%
PE[7] 9% 12% 10% 11%
PC[12] 9% 13% 11% 11%
PC[13] 9% 9% 11% 11%
PC[8] 9% 9% 11% 11%
PB[2] 9% 13% 11% 12%
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2SRC: “Slew Rate Control” bit in SIU_PCR
Table 21. I/O weight1 (continued)
Pad
100 LQFP/64 LQFP
Weight 5V Weight 3.3V
SRC2= 0 SRC = 1 SRC = 0 SRC = 1
VIL
VDD
device reset forced by RESET
VDDMIN
RESET
VIH
device start-up phase
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor36
Figure 6. Noise filtering on reset signal
Table 22. Reset electrical characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
VIH SR P Input High Level CMOS
(Schmitt Trigger) —0.65V
DD —V
DD +0.4 V
VIL SR P Input low Level CMOS
(Schmitt Trigger) —0.4 — 0.35VDD V
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger) —0.1V
DD ——V
VOL CC P Output low leve l Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
— — 0.1VDD V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12— — 0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——0.5
VRESET
VIL
VIH
VDD
filtered by
hysteresis filtered by
lowpass filter
WFRST WNFRST
hw_rst
‘1’
‘0’
filtered by
lowpass filter
WFRST
unknown reset
state device under hardware reset
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 37
4.9 Power management electrical characteristics
4.9.1 Voltage regulator electrical characteristics
The device implements an internal volt age regulator to generate the low volt age core supply VDD_LV from the high volta ge
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply V DD. The followi ng supplies are involved:
• HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
• BV : High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
• LV: Low voltage internal pow er supply for core, FMPLL and flash digital logic. Th is is generated by the internal
voltage regulator but provided outside to connect stability capacitor . It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
ttr CC D Output transition time
output pin3
MEDIUM configuration
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 10 ns
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 ——20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0 ——40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1 ——40
WFRST SR P RESET input filtered
pulse ———40ns
WNFRST SR P RESET input not filtered
pulse — 1000 — — ns
|IWPU| CC P Weak pull-up current
absolute value VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 µA
VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150
VDD = 5.0 V ± 10%, PAD3V5V = 1410 — 250
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
2This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
3CL includes device and package capacitance (CPKG <5pF).
4The configuration P AD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
are configured in input or in high impedance state.
Table 22. Reset electrical characteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor38
— LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bo nding.
— LV_DFLA: Low voltage supply for data flash modu le. It is supplied wit h dedicat ed ballast and shorted to
LV_COR through double bo nding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through doub le bonding.
Figure 7. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Section 4.5, Recommended operatin g condi tions).
Tabl e 23. Voltage regulator electrical chara ct e ristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
CREGn SR — Internal voltage regulator external
capacitance — 200 — 500 nF
RREG SR — Stability capacitor equivalent serial
resistance Range:
10 kHz to 20 MHz ——0.2
CREG1 (LV_COR/LV_DFLA)
DEVICE
VSS_LV
VDD_BV
VDD_LV
CDEC1 (Ballast decoupling)
VSS_LV VDD_LV VDD
VSS_LV VDD_LV
CREG2 (LV_COR/LV_CFLA)
CREG3 CDEC2
DEVICE
VDD_BV
I
VDD_LVn
VREF
VDD
Voltage Regulator
VSS
VSS_LVn
(supply/IO decoupling)(LV_COR/LV_PLL)
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 39
CDEC1 SR — Decoupling capacitance2 ballast VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to 5.5 V 10034704—nF
VDD_BV/VSS_LV pair:
VDD_BV = 3V to 3.6V 400 —
CDEC2 SR — Decoupling capacitance regulator
supply VDD/VSS pair 10 100 — nF
VMREG CC TMain regulator output voltage Before exiting from reset — 1.32 — V
PAfter trimming 1.16 1.28 —
IMREG SR —Main regulator current provided to
VDD_LV domain ———150 mA
IMREGINT CC DMain regulator module current
consumption IMREG = 200 mA — — 2mA
IMREG = 0 mA — — 1
VLPREG CC PLow-power regulator output voltage After trimming 1.16 1.28 — V
ILPREG SR —Low power regulator current provided
to VDD_LV domain ———15 mA
ILPREGINT CC DLow-power regulator module current
consumption ILPREG = 15 mA;
TA = 55 °C ——
600 µA
— ILPREG = 0 mA;
TA = 55 °C — 5 —
VULPREG CC PUltra low power regulator output
voltage After trimming 1.16 1.28 — V
IULPREG SR —Ultra low power regulator current
provided to VDD_LV domain ———5mA
IULPREGINT CC DUltra low power regulator module
current consumption IULPREG = 5 mA;
TA = 55 °C ——100 µA
IULPREG = 0 mA;
TA = 55 °C — 2 —
IDD_BV CC DIn-rush average current on VDD_BV
during power-up5———3006mA
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
2This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
3This value is acceptable to guarantee operation from 4.5 V to 5.5 V.
4External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
5In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs,
depending on external capacitances to be loaded).
6The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
Table 23. Volta ge regulator electrical characteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor40
4.9.2 Low voltage detector electrical characteristics
The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as five low voltage
detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
• POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM
Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)
• LVDHV3 monitors VDD to ensure device reset belo w minimum functional supply (refer to RGM Destructive Event
Status (RGM_DES) Register flag F_LVD27 in device reference manual)
• LVDHV3B monitors VDD_BV to ensure device reset below min imum functional supply (refer to RGM Destructive
Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference manual)
• L VDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status
(RGM_FES) Register flag F_LVD45 in device reference manual)
• LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD1 in device referen ce manual)
• LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD0 in device referen ce manual)
Figure 8. Low voltage detector vs reset
VDD
VLVDHVxH
RESET
VLVDHVxL
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 41
4.10 Power consumption
Table 25 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 24. Low voltage detector electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
VPORUP SR P Supply for functional POR module TA = 25 °C,
after trimming 1.0 — 5.5 V
VPORH CC P Power-on reset threshold 1.5 — 2.6 V
VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — 2.95 V
VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.6 — 2.9 V
VLVDHV3BH CC P LVDHV3B low voltage detector high threshold — — 2.95 V
VLVDHV3BL CC P LVDHV3B low voltage detector low threshold 2.6 — 2.9 V
VLVDHV5H CC T LVDHV5 low voltage detector high threshold — — 4.5 V
VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4 V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16 V
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16 V
Table 25. Power consumption on VDD_BV and VDD_HV
Symbol C Parameter Conditions1Value Unit
Min Typ Max
IDDMAX2CC D RUN mode maximum
average current ——90130
3mA
IDDRUN4CC T RUN mode typical
average current5fCPU = 8 MHz — 7 — mA
Tf
CPU = 16 MHz — 18 —
Tf
CPU = 32 MHz — 29 —
Pf
CPU = 48 MHz — 40 100
IDDHALT CC C HALT mode current6Slow internal RC oscillator
(128 kHz) running TA=25°C — 8 15 mA
PT
A= 125 °C — 14 25
IDDSTOP CC P STOP mode current7Slow internal RC oscillator
(128 kHz) running TA=25°C — 180 700
8µA
DT
A=55°C — 500 —
DT
A=85°C — 1 6
(8) mA
DT
A= 105 °C — 2 9(8)
PT
A= 125 °C — 4.5 12(8)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor42
4.11 Flash memory electrical characteristics
The data flash operation depends strongly on the code flash operation. If code flash is sw itched-off, the data flash is disabled.
4.11.1 Program/Erase characteristics
Table 26 shows the program and erase characteristics.
IDDSTDBY CC P STANDBY mode current9Slow internal RC oscillator
(128 kHz) running TA= 25 °C — 30 100 µA
DT
A=55°C — 75 —
DT
A= 85 °C — 180 700
DT
A= 105 °C — 315 1000
PT
A= 125 °C — 560 1700
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
2Running consumption does not include I/Os toggling which is highly dependent on th e application. The given value
is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify
operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used
peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions,
use low power mode when possible.
3Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush averag e current
on Table 23.
4RUN current measured with typical application with accesses on both flash memory and SRAM.
5Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master,
PLL as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency , periodic
SW/WDG timer reset enabled.
6Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception
or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on P A[0]–P A[11] and PC[12]–PC[15])
with PWM 20 kHz, instance: 1 clock gated. DSPI: inst ance: 0 (clocked but no communication). RTC/API ON.PIT ON.
STM ON. ADC ON but no conversion except 2 analog watchdogs.
7Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
8When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regu lator will be automatically switched off when the load current is below 6 mA.
9Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum
consumption, all possible modules switched off.
Table 25. Power consumption on VDD_BV and VDD_HV (continued) (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 43
Table 26. Program and erase specifications (code flash)
Symbol C Parameter
Value
Unit
Min Typ1
1Typical program and erase times assume nominal supply values and opera ti on at 25 °C. All times are subject to
change pending device characterization.
Initial
max2
2Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
Max3
3The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characteri zed but not guaranteed.
tdwprogram CC C Double word (64 bits) program time4
4Actual hardware programming times. This does not include software overhead.
—2250500µs
t16Kpperase CC C 16 KB block preprogram and erase time — 300 500 5000 ms
t32Kpperase CC C 32 KB block preprogram and erase time — 400 600 5000 ms
t128Kpperase CC C 128 KB block preprogra m an d erase time — 800 1300 7500 ms
tesus CC C Erase suspend latency — — 30 30 µs
Table 27. Program and erase specifications (data flash)
Symbol C Parameter
Value
Unit
Min Typ1
1Typical program and erase times assume nominal supp ly values and operation at 25 °C. All times are subject to
change pending device characterization.
Initial
max2
2Initial factory condition: < 100 program/er ase cycles, 25 °C, typical supply voltage.
Max3
3The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
tswprogram CC C Single word (32 bits) program time4
4Actual hardware programming times. This does not include software overhead.
—3070300µs
t16Kpperase CC C 16 KB block preprogram and erase time — 700 800 1500 ms
tBank_D CC C 64 KB bloc k preprogram and erase time — 1900 2300 4800 ms
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor44
ECC circuitry provides correction of single bit faults and is used to improve further aut om otive reliability results. Some units
will experience single bit corrections throughout the life of the product with no imp act to product reliability.
4.11.2 Flash power supply DC characteristics
Table 30 shows the power supply DC characteristics on external supply.
NOTE
Power supply for data flash is actually prov ided by code flash; this means that data flash
cannot work if code flash is not powered.
Table 28. Flash module life
Symbol C Parameter Conditions Value Unit
Min Typ Max
P/E CC C Number of program/erase
cycles per block over the
operating temperature range
(TJ)
16 KB blocks 100,000 — — cycles
32 KB blocks 10,000 100,000 — cycles
128 KB blocks 1,000 100,000 — cycles
Retention CC C Minimum data retention at 85 °C
average ambient temperature1
1Ambient temperature averaged over application duration. It is recommended not to exceed the product ope rating
temperature range.
Blocks with
0–1,000 P/E cycles 20 — — years
Blocks with
1,001–10,000 P/E cycles 10 — —
Blocks with
10,001–100,000 P/E cycles 5——
Table 29. Flash memory read access timing
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Max Unit
fCFREAD CC P Maximum working frequency for reading code flash memory at given
number of wait states in worst conditions 2 wait states 48 MHz
C0 wait states 20
fDFREAD CC P Maximum working frequency for reading data flash memory at given
number of wait states in worst conditions 6 wait states 48 MHz
Table 30. Flash power supply DC electrical characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
ICFREAD CC D Sum of the current consumption on
VDDHV and VDDBV on read access Fla s h module read
fCPU = 48 MHz Code flash — — 33 mA
IDFREAD CC D Data flash — — 4 mA
ICFMOD CC D Sum of the current consumption on
VDDHV and VDDBV on matrix
modification (program/erase)
Program/Er ase on -g oi n g
while reading flash registers,
fCPU = 48 MHz
Code flash — — 33 mA
IDFMOD CC D Data flash — — 6 mA
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 45
4.11.3 Start-up/Switch-off timings
4.12 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
• Software recommendations The software flowchart must include the management of runaway conditions such as:
IFLPW CC D Sum of the current consumption on
VDDHV and VDDBV during
flash low-power mode
— Code flash — — 910 µA
ICFPWD CC D Sum of the current consumption on
VDDHV and VDDBV during
flash power-down mode
— Code flash — — 125 µA
IDFPWD CC D Data flash — — 25 µA
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Table 31. Start-up time/Switch-off time
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
tFLARSTEXIT CC T Delay for flash mo dule to exit reset mode Code flash — — 125 µs
Data flash — — 150 µs
tFLALPEXIT CC T Delay for flash module to exit low-power
mode2
2Data flash does not support low-power mode
Code flash — — 0.5 µs
tFLAPDEXIT CC T Delay for flash module to exit power-down
mode Code flash — — 30 µs
Data flash — — 303
3If code flash is already switched-on.
µs
tFLALPENTRY CC T Delay for flash module to enter low-power
mode Code flash — — 0.5 µs
tFLAPDENTRY CC T Delay for flash modul e to enter
power-down mode Code flash — — 1.5 µs
Data flash — — 4(3) µs
Table 30. Flash power supply DC electrical characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor46
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
• Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
4.12.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
4.12.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
Table 32. EMI radiated emission measurement1 2
1EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
Symbol C Parameter Conditions Value Unit
Min Typ Max
— SR — Scan range — 0.150 — 1000 MHz
fCPU SR — Operating frequency — — 48 — MHz
VDD_LV SR — LV operating voltages — — 1.28 — V
SEMI CC T Peak level VDD = 5V, T
A=25°C,
100 LQFP package
Test conforming to IEC 61967-2,
fOSC = 8 MHz/fCPU = 48 MHz
No PLL frequency
modulation — — 18 dBµ
V
± 2% PLL frequency
modulation — — 14 dBµ
V
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 47
4.12.3.2 Static latch-up (LU)
Two com pl ementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 33. ESD absolute maximum ratings1 2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Symbol C Ratings Conditions Class Max value Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model) TA = 25 °C
conforming to AEC-Q100-002 H1C 2000 V
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model) TA = 25 °C
conforming to AEC-Q100-003 M2 200 V
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model) TA = 25 °C
conforming to AEC-Q100-011 C3A 500 V
750 (corners) V
Table 34. Latch-up results
Symbol C Parameter Conditions Class
LU CC T St a tic latch-up class TA = 125 °C
conforming to JESD 78 II level A
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor48
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 35 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
Figure 9. Crystal oscillator and resonator connection scheme
C2
C1
Crystal
XTAL
EXTAL
Resonator
XTAL
EXTAL
DEVICE
DEVICE
DEVICE XTAL
EXTAL
I
R
VDD
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
1. XTAL /EXTAL must not be directly used to drive external circuits
Notes:
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 49
Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram
Table 35. Crystal description
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
(ESR)
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1=C
2 (pF)1
1The values specified for C1 and C2 are the same as used in simulatio ns. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
Shunt
capacitance
between xtalout
and xtalin
C02 (pF)
2The value of C0 specified here includ es 2 p F additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
4 NX8045GB 300 2.68 591.0 21 2.93
8 NX5032GA 300 2.46 160.7 17 3.01
10 150 2.93 86.6 15 2.91
12 120 3.11 56.5 15 2.93
16 120 3.90 25.3 10 3.00
VFXOSCOP
TFXOSCSU
VXTAL
VFXOSC
valid internal clock
90%
10%
1/fFXOSC
S_MTRANS bit (ME_GS register)
‘1’
‘0’
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor50
Table 36. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified
Value Unit
Min Typ Max
fFXOSC SR — Fast external crystal
oscillator frequency — 4.0 — 16.0 MHz
gmFXOSC CC C Fast external crystal
oscillator transconductance VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2 — 8.2 mA/V
CC P VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0 — 7.4
CC C VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
2.7 — 9.7
CC C VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5 — 9.2
VFXOSC CC T Oscillation amplitude at
EXTAL fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0 1.3 — — V
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1 1.3 — —
VFXOSCOP CC P Oscillation operating point — — 0.95 V
IFXOSC2
2Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
CC T Fast external crystal
oscillator consumption ——23mA
tFXOSCSU CC T Fast external crystal
oscillator start-up time fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0 —— 6ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1 ——1.8
VIH SR P Input high level CMOS
(Schmitt Trigger) Oscillator bypass mode 0.65VDD —V
DD+0.4 V
VIL SR P Input low level CMOS
(Schmitt Trigger) Oscillator bypass mode 0.4 — 0.35VDD V
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 51
4.14 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
4.15 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.
Table 37. FMPLL electrical characteristics
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
Value Unit
Min Typ Max
fPLLIN SR — FMPLL reference clock2
2PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock shou ld verify fPLLIN and PLLIN.
—4—48MHz
PLLIN SR — FMPLL reference clock duty
cycle(2) —40—60%
fPLLOUT CC D FMPLL output clock frequency — 16 — 48 MHz
fVCO3
3Frequency modulation is considered ±4%.
CC P VCO frequency without
frequency modu l a ti on — 256 — 512 MHz
VCO frequency with frequency
modulation — 245 — 533
fCPU SR — System clock frequency — — — 48 MHz
fFREE CC P Free-running freque ncy — 20 — 150 MHz
tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) — 40 100 µs
tLTJIT CC — FMPLL long term jitter fPLLIN = 16 MHz (resonator),
fPLLCLK at 48 MHz, 4,000 cycles — — 10 ns
IPLL CC C FMPLL consumption TA = 25 °C — — 4 mA
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
fFIRC CC P Fast internal RC oscillator high
frequency TA = 25 °C, trimmed — 16 — MHz
SR — — 12 20
IFIRCRUN2, CC T Fast internal RC oscillator high
frequency current in running
mode
TA = 25 °C, trimmed — — 200 µA
IFIRCPWD CC D Fast internal RC oscillator high
frequency current in power
down mode
TA = 25 °C — — 10 µA
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor52
4.16 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator (SIRC). This can be used as the reference clock for the R TC module.
IFIRCSTOP CC T Fast internal RC oscillator high
frequency and system clock
current in stop mode
TA = 25 °C sysclk = off — 500 — µA
sysclk = 2 MHz — 600 —
sysclk = 4 MHz — 700 —
sysclk = 8 MHz — 900 —
sysclk = 16 MHz — 1250 —
tFIRCSU CC C Fast internal RC oscillator
start-up time VDD = 5.0 V ± 10% — 1.1 2.0 µs
FIRCPRE CC C Fast internal RC oscillator
precision after software
trimming of fFIRC
TA = 25 °C 1— 1%
FIRCTRIM CC C Fast internal RC oscillator
trimming step TA = 25 °C — 1.6 %
FIRCVAR CC C Fast internal RC oscillator
variation in temperature and
supply with respect to fFIRC at
TA= 55 °C in high-frequency
configuration
—5— 5%
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
2This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
fSIRC CC P Slow internal RC oscillato r low
frequency TA = 25 °C, trimmed — 128 — kHz
SR — — 100 — 150
ISIRC2, CC C Slow internal RC oscillator low
frequency current TA = 25 °C, trimmed — — 5 µA
tSIRCSU CC P Slow internal RC oscillator start-up
time TA = 25 °C, VDD = 5.0 V ± 1 0% — 8 12 µs
SIRCPRE CC C Slow internal RC oscillator precision
after software trimming of fSIRC
TA = 25 °C 2— 2%
SIRCTRIM CC C Slow internal RC oscillator trimming
step ——2.7—
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 53
SIRCVAR CC P Slow internal RC oscillator variation
in temperature and supply with
respect to fSIRC at TA= 55 °C in high
frequency configuration
High frequency configuration 10 — 10 %
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
2This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
Table 39. Slow internal RC oscillator (128 kHz) electrical cha r acteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor54
4.17 ADC electrical characteristics
4.17.1 Introduction
The device provides a 12-bit Successive Approximation Register (SAR) analog-to-dig ital convert er.
Figure 11. ADC characteristics and error definitions
(2)
(1)
(3)
(4)
(5)
Offset Error (EO)
Offset Error (EO)
Gain Error (EG)
1 LSB (ideal)
1023
1022
1021
1020
1019
1018
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential no n-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
1 LSB ideal = VDD_ADC / 1024
Vin(A) (LSBideal)
code out
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 55
4.17.2 Input impedance and ADC accuracy
In the following analysis, th e input circuit corres ponding to the precise channels is considered.
T o preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalen t input impedance of the ADC itsel f.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being CS and Cp2
substantially two switched capacitances, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive
path to ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a resistance of 330 k is
obtained (REQ = 1 / (fc×(C
S+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error
induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF, the external
circuit must be designed to respect the Equation 4:
Eqn. 4
Equation 4 generates a constraint for external network de si gn, in particular on a resistive path.
VA
RSRF
+
REQ
---------------------
1
2
---LSB
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor56
Figure 12. Input equivalent circuit (precise channels)
RF
CF
RSRLRSW1
CP2 CS
VDD Sampling
Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
CP1
RAD
Channel
Selection
VA
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 57
Figure 13. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit in Figure 13): A charge sharing phenomenon is installed
when the sampling phase is started (A/D switch close).
Figure 14. Transient behavior during sampling phase
R
F
C
F
R
S
R
L
R
SW1
C
P3
C
S
V
DD
Sampling
Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
C
P1
R
AD
Channel
Selection
V
A
C
P2
Extended
R
SW2
Switch
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
VA
VA1
VA2
t
ts
VCS Voltage transient on CS
V <0.5 LSB
12
1 < (RSW + RAD) CS << ts
2
= R
L
(C
S
+ C
P1
+ C
P2
)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor58
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster , but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time ts
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transi en t is completed
well before the end of sampling time ts, a constraints on RL sizing is obtained:
Eqn. 9
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal so urce VA; the time constant RFCF of
the filter is very high with respect to the sampling time (ts). The filter is typically designed to act as anti-aliasing.
1RSW RAD
+=CPCS
CPCS
+
---------------------
1RSW RAD
+CSts
«
VA1 CSCP1 CP2
++VACP1 CP2
+=
2RL
CSCP1 CP2
++
10 2
10 RLCSCP1 CP2
++=ts
VA2 CSCP1 CP2 CF
+++VACF
VA1
+C
P1 CP2
+C
S
+=
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 59
Figure 15. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (tc). Again the conversion period tc is longer than the sampling time ts,
which is just a portion of it, even when fixed channel continuous conversion mode is sel ected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time ts, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling
switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
Eqn. 11
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
f0f
Analog source bandwidth (VA)
f0f
Sampled signal spectrum (fC = conversion rate)
fC
f
Anti-aliasing filter (fF = RC filter pole)
fF
2 f0<fC (Nyquist)
fF = f0 (anti-aliasing filtering condition)
tc<2 RFCF (conversion rate vs. filter pole)
Noise
VA2
VA
------------CP1 CP2
+C
F
+
CP1 CP2
+C
FCS
++
--------------------------------------------------------=
CF2048 CS
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor60
4.17.3 ADC electrical characteristics
Table 40. ADC input leakage current
Symbol C Parameter Conditions Value Unit
Min Typ Max
ILKG CC C Input leakage current TA=40 °C No current injection on adjacent pin — 1 — nA
CT
A=25 °C — 1 —
CT
A= 105 °C — 8 200
PT
A= 125 °C — 45 400
Table 41. ADC conversion characteristics
Symbol C Parameter Conditions1Value Unit
Min Typ Max
VSS_ADC SR — Voltage on
VSS_HV_ADC (ADC
reference) pin with
respect to ground
(VSS)2
—0.1 — 0.1 V
VDD_ADC SR — Voltage on
VDD_HV_ADC pin
(ADC reference) with
respect to ground
(VSS)
—V
DD 0.1 — VDD +0.1 V
VAINx SR — Analog input voltage3—V
SS_ADC 0.1 — VDD_ADC +0.1 V
fADC SR —ADC analog frequency VDD =5.0V 3.33 —32 + 4% MHz
VDD =3.3V 3.33 —20 + 4%
ADC_SYS SR —ADC clock duty cycle
(ipg_clk) ADCLKSEL = 1445 —55%
tADC_PU SR —ADC power up delay ———1.5 µs
tsCC T Sampling time5
VDD = 3.3 V fADC = 20 MHz,
INPSAMP = 12 600 — — ns
fADC = 3.33 MHz,
INPSAMP = 255 — — 76.2 µs
T Sampling time(5)
VDD = 5.0 V fADC = 24 MHz,
INPSAMP = 13 500 — — ns
fADC = 3.33 MHz,
INPSAMP = 255 — — 76.2 µs
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 61
tcCC P Conversion time6
VDD = 3.3 V fADC = 20 MHz,
INPCMP = 0 2.4 — — µs
fADC = 13.33 MHz,
INPCMP = 0 ——3.6
P Conversion time(6)
VDD = 5.0 V fADC = 32 MHz,
INPCMP = 0 1.5 — — µs
fADC = 13.33 MHz,
INPCMP = 0 ——3.6
CSCC DADC input sampling
capacitance — 5 pF
CP1 CC DADC input pin
capacitance 1 — 3 pF
CP2 CC DADC input pin
capacitance 2 — 1 pF
CP3 CC DADC input pin
capacitance 3 —1.5 pF
RSW1 CC DInternal resistance of
analog source ———1 k
RSW2 CC DInternal resistance of
analog source ———2 k
RAD CC DInternal resistance of
analog source ———0.3 k
IINJ SR —Input current Injection Current
injection on
one ADC input,
different from
the converted
one
VDD =
3.3 V ± 10% 5— 5mA
VDD =
5.0 V ± 10% 5 — 5
INLP CC TAbsolute Integral
non-linearity-precise
channels
No overload —1 3LSB
INLX CC TAbsolute Integral
non-linearity-extended
channels
No overload —1.5 5LSB
DNL CC TAbsolute Differential
non-linearity No overload —0.5 1LSB
EO CC TAbsolute Offset error ——2—LSB
EGCC TAbsolute Gain error — —2—LSB
TUEP7CC PTotal unadjusted error
for precise channels,
input only pins
Without current injection –6 6LSB
TWith current injection –8 8
Table 41. ADC conversion characteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor62
4.18 On-chip peripherals
4.18.1 Current consumption
TUEX(7) CC TTotal unadjusted error
for extended channel Without current injection –10 10 LSB
TWith current injection –12 12
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125 °C, unless otherwise specified.
2Analog and digital VSS must be common (to be tied together externally).
3VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
5During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of
the sampling time tS, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
6This parameter does not include the sampling time tS, but only the ti me for determining the digital result and the
time to load the result’s register with the conversion result.
7Tota l Unadjusted Error: The maximum erro r that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 42. On-chip peripherals current cons umption1
Symbol C Parameter Conditions Typical value2Unit
IDD_BV(CAN) CC T CAN (FlexCAN) supply
current on VDD_BV
500 Kbyte/s Total (static + dynamic)
consumption:
• FlexCAN in loop-back
mode
• XTAL at 8 MHz used as
CAN engine clock source
• Message sending period
is 580 µs
8×f
periph + 85 µA
125 Kbyte/s 8 × fperiph + 27 µA
IDD_BV(eMIOS) CC T eMIOS supply current
on VDD_BV
Static consumption:
• eMIOS channel OFF
• Global prescaler enabled
29 × fperiph µA
Dynamic consumption:
• It doe s not change varying the
frequency (0.003 mA)
3µA
IDD_BV(SCI) CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynami c) consumption:
•LIN mode
• B audrate: 20 Kbyte/s
5×f
periph + 31 µA
Table 41. ADC conversion characteristics (continued)
Symbol C Parameter Conditions1Value Unit
Min Typ Max
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 63
4.18.2 DSPI characteristics
IDD_BV(SPI) CC T SPI (DSPI) supply
current on VDD_BV
Ballast static consumption (only clocked) 1 µA
Ballast dynamic consumption (continuous
communication):
• Baudrate: 2 Mbit /s
• Transmission every 8 µs
• Frame: 16 bits
16 × fperiph µA
IDD_BV(ADC) CC T ADC supply current on
VDD_BV
VDD = 5.5 V Ballast static consumption
(no conversion) 41 × fperiph µA
Ballast dynamic
consumption (continuous
conversion)3
5×f
periph µA
IDD_HV_ADC(ADC) CC T ADC supp ly current on
VDD_HV_ADC
VDD = 5.5 V Analog static consumption
(no conversion) 2×f
periph µA
Analog dynamic
consumption (continuous
conversion)
75 × fperiph + 32 µA
IDD_HV(FLASH) CC T CFlash + DFlash supply
current on VDD_HV
VDD = 5.5 V — 8.21 mA
IDD_HV(PLL) CC T PLL supply current on
VDD_HV
VDD = 5.5 V — 30 × fperiph µA
1Operating conditions: TA = 25 °C, fperiph = 8 MHz to 48 MHz
2fperiph is an absolute value.
3During the conversion, the total current consumption is given from the sum of the static and dynamic consumption,
i.e., (41 + 5) × fperiph.
Table 43. DSPI characteristics1
No. Symbol C Parameter DSPI0/DSPI1 Unit
Min Typ Max
1t
SCK SR D SCK cycle time Master mode
(MTFE = 0) 125 — — ns
D Slave mode
(MTFE = 0) 125 — —
D Master mode
(MTFE = 1) 83 — —
D Slave mode
(MTFE = 1) 83 — —
—f
DSPI SR D DSPI digital controller frequency — — fCPU MHz
Table 42. On-chip peripherals current consumption1 (continued)
Symbol C Parameter Conditions Typical value2Unit
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor64
—tCSC CC D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode
Master mode — — 1302ns
—tASC CC D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode for CSn11
Master mode — — 130(2) ns
2t
CSCext3SR D CS to SCK delay Slave mode 32 — — ns
3t
ASCext4SR D After SCK delay Slave mode 1/fDSPI + 5 — — ns
4t
SDC CC D SCK duty cycle Master mode — tSCK/2 — ns
SR D Slave mode tSCK/2 — —
5t
ASR D Slave access time — 1/fDSPI +70 — — ns
6t
DI SR D Slave SOUT disable time — 7 — — ns
7t
PCSC SR D PCSx to PCSS time — 0 — — ns
8t
PASC SR D PCSS to PCSx time — 0 — — ns
9t
SUI SR D Data setup time for inputs Master mode 43 — — ns
Slave mode 5 — —
10 tHI SR D Data hold time for inputs Master mode 0 — — ns
Slave mode 25——
11 tSUO6CC D Data valid after SCK edge Master mode — — 32 ns
Slave mode — — 52
12 tHO(6) CC D Data hold time for outputs Master mode 0 — — ns
Slave mode 8 — —
1Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns
2Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad
3The tCSC delay value is configurable through a register . When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure
positive tCSCext.
4The tASC delay value is configurable through a register. When configuring t ASC (using PASC and ASC fields in
DSPI_CT ARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive
tASCext.
5This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR.
6SCK and SOUT configured as MEDIUM pad
Table 43. DSPI characteristics1 (continued)
No. Symbol C Parameter DSPI0/DSPI1 Unit
Min Typ Max
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 65
Figure 16. DSPI classic SPI timing – master, CPHA = 0
Data Last Data
First Data
First Data Da ta Last Data
SIN
SOUT
PCSx
SCK Output 4
9
12
1
11
10
4
SCK Output
(CPOL = 0)
(CPOL = 1)
3
2
Note: Numbers shown reference Table 43.
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor66
Figure 17. DSPI classic SPI timing – master, CPHA = 1
Figure 18. DSPI classic SPI timing – slave, CPHA = 0
Data Last Data
First Data
SIN
SOUT
12 11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 67
Figure 19. DSPI classic SPI timing – slave, CPHA = 1
Figure 20. DSPI modified transfer format timing – master, CPHA = 0
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
PCSx 3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor68
Figure 21. DSPI modified transfer format timing – master, CPHA = 1
Figure 22. DSPI modified transfer format timing – slave, CPHA = 0
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
12
Note: Numb er s sh own referen c e Table 43.
Electrical characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 69
Figure 23. DSPI modified transfer format timing – slave, CPHA = 1
Figure 24. DSPI PCS strobe (PCSS) timing
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
Note: Numbers shown reference Table 43.
PCSx
78
PCSS
Note: Numbers shown refer ence Table 43.
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package characteristics
Freescale Semiconductor70
4.18.3 JTAG characteristics
Figure 25. Timing diagram – JTAG boundary scan
5 Package characteristics
5.1 Package mechanical data
5.1.1 100 LQFP
Table 44. JTAG characteristics
No. Symbol C Parameter Value Unit
Min Typ Max
1t
JCYC CC D TCK cycle time 83.33 — — ns
2t
TDIS CC D TDI setup time 15 — — ns
3t
TDIH CC D TDI hold time 5 — — ns
4t
TMSS CC D TMS setup ti me 15 — — ns
5t
TMSH CC D TMS hold time 5 — — ns
6t
TDOV CC D TCK low to TDO valid — — 49 ns
7t
TDOI CC D TCK low to TDO invalid 6 — — ns
INPUT DATA VALID
OUTPUT DATA VALID
DATA INPUTS
DATA OUTPUTS
DATA OUTPUTS
TCK
Note: Numbers shown reference Table 44.
3/5
2/4
7
6
Package characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 71
Figure 26. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package characteristics
Freescale Semiconductor72
Figure 27. 100 LQFP package mechanical drawing (Part 2 of 3)
Package characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 73
Figure 28. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package characteristics
Freescale Semiconductor74
5.1.2 64 LQFP
Figure 29. 64 LQFP mechanical drawing (part 1 of 3)
Package characteristics
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 75
Figure 30. 64 LQFP mechanical drawing (part 2 of 3)
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Package characteristics
Freescale Semiconductor76
Figure 31. 64 LQFP mechanical drawing (part 3 of 3)
Ordering information
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 77
6 Ordering information
Figure 32. Commercial product code structure
Qualification Status
Power Architecture Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
MPC56 DF1MLL
Example code: 02
Temperature spec.
Package Code
Qualification Status
M = MC status
S = Auto qualified
P = PC status
Automotive Platform
56 = Power Architecture in 90 nm
Core Version
0 = e200z0h
Flash Size (z0 core)
1= 128 KB
2 = 256 KB
Product
D = Access family
Optional fields
F = ATMC
1 = Maskset revision
R = Tape & Reel (blank if Tray)
R
Temperature spec.
C = –40 to 85 °C
V = –40 to 105 °C
M = –40 to 125 °C
Package Code
LH = 64 LQFP
LL = 100 LQFP
Frequency
4 = Up to 48 MHz
3 = Up to 32 MHz
4
Frequency
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Document revision history
Freescale Semiconductor78
7 Document revision history
Table 45 summarizes revisions to this docume nt.
Table 45. Revision history
Revision Date Description of Changes
1 30 Sep 2009 Initial release
2 18 Feb 2010 Updated the following tables:
- Absolute maximum ratings
- Low voltage power domain electrical characteristics;
- On-chip peripherals current consu m ption
- DSPI characteristics;
- JTAG characteristics;
- ADC conversion characteristics;
Inserted a note on “Flash power supply DC characteristics” section.
3 10 Aug 2010 “Features” section: Updated information concerning eMIOS, ADC, LINFlex, Nexus and
low power capabilities
“MPC5602D device comparison” table: updated the “Execution speed” row
“MPC5602D series block diagram” figure:
• updated max number of Crossbar Switches
• updated Legend
“MPC5602D series block summary” table: added contents concernig the eDMA block
“100 LQFP pin configuration (top view)” figure:
• removed alternate functions
• up dated supply pins
“64 LQFP pin configuration (top view)” figure: removed alternate functions
Added “Pin muxing” section
“NVUSRO register” section: Deleted “NVUSRO[WATCHDOG_EN] field description“
section
“Recommended operating conditions (3.3 V)” table:
•TV
DD: deleted min value
• I n footnote No. 3, changed capacitance value between VDD_BV and VSS_LV
“Recommended operating conditions (5.0 V)” table: deleted TVDD min value
“LQFP thermal characteristics” table: changed RJC values
“I/O input DC electrical characteristics” table:
•W
FI: updated max value
•W
NFI: updated min value
“I/O consumption” table: removed IDYNSEG row
Added “I/O weight” table
“Program and erase specifications (Code Flash)” table: deleted TBank_C row
Updated the following tables:
• “Voltage regulator el ectrical characteristics”
• “Low voltage monitor electrical characteristics”
• “Low voltage power domain electrical characteristics”
• “Start-up time/Switch-off time”
• “F ast externa l crystal oscillator (4 to 16 MHz) electrical characteristics”
• “FMPLL electrical characteristics”
• “Fast internal RC oscillator (16 MHz) electrical characteristics”
• “ADC conversion characteristics”
• “On-chip peripherals current consumption”
• “DSPI characteristics”
“DSPI characteristics” section: removed “DSPI PCS strobe (PCSS) timing” figure
3
(continued) 10 Aug 2010 “Ordering information” section: removed “Orderable part number summary“ table
Document revision history
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 79
3.1 23 Feb 2011 Deleted the “Freescale Confidential Proprietary” label (the document is public)
Table 45. Revision history (continued)
Revision Date Description of Changes
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Document revision history
Freescale Semiconductor80
4 14 Jul 2011 Formatting and editorial changes throughout
Device comparison table: for the “Total timer I/O eMIOS”, changed “13 ch” to “14 ch”
Features: Replaced “e200z0“ with “e200z0h”; added an explanation of which LINFlex
modules support master mode and slave
MPC5601D/MPC5602D series block summary:
• ad ded definition for “AUTOSAR” acronym
changed “System watchdog timer” to “Software watchdog timer”64 LQFP pin
configuration (top view): changed pin 6 from VPP_TEST to VSS_HV
Added section “Pad configuration during reset phases”
Added section “Voltage supply pins”
Added section “Pad types”
Added section “System pins”
Renamed and updated section “Functional ports” (was previously section “Pin muxing”);
update includes replacing all instances of WKUP with WKPU (WKPU is the correct
abbreviation for Wakeup Unit)
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality
Added section “NVUSRO[WATCHDOG_EN] field description”
Absolute maximum ratings: Removed “C” column from table
Replaced “TBD” with “—” in TVDD min value cell of 3.3 V and 5 V recommended
operating conditions tables
LQFP thermal characteristics: removed RJB single layer board conditions; updated
footnote 4
I/O input DC electrical characteristics: removed footn ote “All values need to be
confirmed during device validation”; updated ILKG characteristics
MEDIUM configuration output buffer electrical characte ristics: changed “IOH = 100 µA”
to “IOL = 100 µA” in VOL conditions
I/O consumption: replaced instances of “Root medium square” with “Root mean square”
Updated section “Voltage regulator electrical characteristics”
Section “Low voltage detector electrical ch aracteristics”: changed title (was “Voltage
monitor electrical characteristics”); added a fifth L VD (L VDHV3B); added event status
flag names found in RGM chapter of device reference manu al to POR module and
LVD descriptions; replaced instances of “Low voltage monitor” with “Low voltage
detector”; deleted note referencin g power domain No. 2 (this domain is not present
on the device); updated electrical characteristics table
Updated and renamed section “Power consumption” (was previously section “Low
voltage domain power consumption”)
Program and erase specifications (code flash): updated symbols; updated tesus values
Updated Flash memory read access timing
EMI radiated emission measurement: upda ted SEMI values
Updated FMPLL electrical characteristics
Crystal oscillator and resonator connection scheme: inserted footnote about possibly
requiring a series resistor
Fast internal RC oscillator (16 MHz) electrical ch aracteristics: updated tFIRCSU values
Section “Input impedance and ADC accuracy”: change d “VA/VA2” to “VA2/VA” in
Equation 13
ADC conversion characteristics:
• updated conditions for sampling time VDD = 5.0 V
• up dated conditions for conversion time VDD = 5.0 V
Commercial product code structure: added character for frequency; updated optional
fields character and description
Restored the revision history table and added an entry for Rev. 3.1
Updated Abbreviations
Table 45. Revision history (continued)
Revision Date Description of Changes
Abbreviations
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Freescale Semiconductor 81
Appendix A Abbreviations
Table A-1 lists abbreviation s used in this document.
5 — Rev. 5 not published.
6 29 Jan 2013 Removed all instances of table footnote “All values need to be confirmed during device
validation”
Section 4.1, “Introduction, removed Caution note.
In Table 42, On-chip peripherals current consumption, replaced “TBD” with “8.21 mA” in
IDD_HV(FLASH) cell.
Updated Section 4.17.2, “Input impedance and ADC accuracy
In Table 24, changed VLVDHV3L, VLVDHV3BL from 2.7 V to 2.6 V.
Revised the Table 28 (Flash module life)
Updated Table 43, DSPI characteristics, to add specifications 7 and 8, tPCSC and tPASC.
Inserted Figure 24, DSPI PCS strobe (PCSS) timing.
Tabl e A-1. Abbreviat ion s
Abbreviation Meaning
APU Auxilliary processing unit
CMOS Complementary metal–oxide–semiconductor
CPHA Clock phase
CPOL Clock polarity
CS Peripheral chip select
DAOC Double action output compare
ECC Error code correction
EVTO Event out
GPIO General purpose input/output
IPM Input period measurement
IPWM Input pulse width measurement
MB Message buffer
MC Modulus counter
MCB Modulus counter buffered (up / down)
MCKO Message clock out
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format en able
NVUSRO Non-volatile user options register
OPWFMB Outp ut pulse width and frequency modulation buffered
OPWMB Output pulse widt h mo du lation buf fered
Table 45. Revision history (continued)
Revision Date Description of Changes
MPC5602D Microcontroller Dat a Sheet, Rev. 6
Abbreviations
Freescale Semiconductor82
OPWMCB Center aligned outpu t pulse width modulation buffered with dead time
OPWMT Output pulse width modulation trigger
PWM Pulse width modulation
SAIC Single action input capture
SAOC Single action output compare
SCK S erial communications clock
SOUT Serial data out
TBD To be defined
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select
Table A-1. Abbreviations (continued)
Abbreviation Meaning
Document Number: MPC5602D
Rev. 6
01/2013
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