Philips ComponentsSignetics Document No. | 353-1496 74AC/ACT1 1 286 | ore 9-bit odd/even parity generator/ checker with bus drive I/O port Date of Issue | October 17, 1990 Status Product Specification ACL Products FEATURES QUICK REFERENCE DATA * Generates either odd or even parity CONDITIONS TYPICAL for nine data lines SYMBOL PARAMETER Tamb = 25C; GND = OV; UNIT * Word length easily expanded by cas- Voo = .0V AC | ACT cading cue Seen ee oR C, = 50pF 59 | 7.3 ns * Direct bus connection for parity gen- n eration or for checking by using the f = 1MHz; Enabled 53 56 i Power dissipation parity I/O port Cpp capacitanes' pF * Glitch-free bus during power up/down C, = 50pF Disabled 46 50 * Output capability: t24mA Cw Input capacitance V,= OV or Veg 35 | 35 pF . CMOS (AC) and TTL (ACT) voltage Cyva VO capacitance Vyo = OV or Veg: Disabled 8.5 8.5 pF level inputs Per Jad wo st e JG40.2 * 50Q incident wave switching lLatcH ; Latch-up current Standard 17 500 | 500 } mA * Center-pin Veg and ground configu- Note: ration to minimize high-speed switch- 1. Cop is used to determine the dynamic power dissipation (P,, in pW): ing noise 2 2 Poe Cop x Voc xf + {C, x Voc xf) where: * Icc category: MSI f, = input frequency in MHz, C, = output load capacitance in pF, f, = output frequency in MHz, V.... = supply voltage in V, DESCRIPTION F(C nt 2 "t } yum of out sits The 74AC/ACT1 1286 high-performance L* "ce lol = CMOS devices combine very high ORDERING INFORMATION speed and high output drive compa- PACKAGES TEMPERATURE RANGE ORDER CODE rable to the most advanced TTL fami- d4pin clastic DIP F4AC1 1286N ; -pin plastic 5 lies. (300mil-wide) 40C to +85C 74ACT11286N The T4AC/IACTI 1286 39-bit parity gen- 14-pin plastic so -40C to +85C 74AC 1 1286D erator or checker is commonly used to (150mil-wide) 74ACT11286D detect errors in high-speed data trans- mission or data retrieval systems. It fea- (continued) PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) N and D Packages 2 4 141312 109 9 7 2 aK Li Ett ; 'y hy Ip '5 "4 Js 1g y '5 14 ~ wo = rx} | 1 3 nL al PARITY PARITY = = r=) vO __ ERROR + | : 3 5 6 4 ot EN1 185Philips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port 74AC/ACT11286 tures a local output for parity checking and a bus-driving parity /O port for par- ity generation/checking. The XMIT control input is implemented specifically for cascading for expanding word length. When XMIT is held Low the parity tree is disabled and the Parity Error output remains at a High logic level regardless of the other inputs (Ig - lg). When XMIT is High the parity tree is enabled. Parity Error indicates a par- ity error when either an even number of inputs are High and Parity l/O is forced to Low, or when an odd number of in- puts are High and Parity I/O is forced High. The VO control circuitry is designed so that the I/O port will remain in the high- impedance state during power-up or power-down to prevent bus glitches. LOGIC DIAGRAM 1, 2 \, 14 1 32 \, 12 } i, 2 4 5. PARITY 1 8 ERROR i _) parity _3 | ao oN MM. - xmir 6 Pe. L-~ PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 2,1, 14, 13, : 12, 10,9,8.7 to- te Data inputs 3 PARITY I/O Parity VO 6 XMIT Transmit input (active Low) PARITY . 5 ERROR Parity error output 4 GND Ground (OV) 11 Voc Positive supply voltage FUNCTION TABLE Number of High Data xMiT PARITY PARITY Inputs (Ig - 1) vo ERROR 0,2,4,6,8 | H H 1,3,5,7,9 I L H h h H 0, 2,4,6,8 h I L h h L 1,3,5,7,9 h I H | = Low voltage level input h = High voltage level input H = High voltage level output L = Low voltage level output October 17, 1990 186Philips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port 7AACIACT11286 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER 74AC11286 74ACT11286 UNIT Min Nom Max Min Nom Max Vec DC supply voltage 3.0! 5.0 5.5 45 5.0 5.5 vy Input voltage 0 Voce 0 Veco Vo Output voltage 0 Veo 0 Veco Vv AvAv Input transition rise or fall rate 0 10 0 10 ns/V Tame Operating free-air temperature ra