CD4060BCNX - Fairchild Semiconductor

October 1987

Revised March 2002

CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary

Counters • 14-Stage Rippl e Carry Binary Counters

CD4020BC • CD4040BC • CD4060BC

14-Stage Ripple Carry Binary Counters •

12-Stage Ripple Carry Binary Counters •

14-Stage Ripple Carry Binary Counters

General Description

The CD4020BC, CD4060BC are 14-stage ripple carry

binary counters, and the CD4040BC is a 12-stage ripple

carry binary counter . The counters are advanced one count

on the negative transition of each clock pulse. The

counters ar e reset to the zero sta te by a logical “1” at the

reset input independent of clock.

Features

■Wide supply voltage range: 3.0V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility: Fan out of 2 driving 74L

or 1 driving 74LS

■Medium speed operation: 8 MHz typ. at VDD = 10V

■Schmitt trigger clock input

Ordering Code:

Devices also available in Tape and Reel. Specify by ap pending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP and SOIC

CD4020BC

Top View

Pin Assignments for DIP, SOIC and SOP

CD4040BC

Top Vie w

Order Number Package Number Package Description

CD4020BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4020BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4040BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4040BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4040BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4060BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4060BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD4020BC • CD4040BC • CD4060BC

Connection Diagrams (Continued)

Pin Assignm ents for DIP and SO IC

CD4060BC

Top View

Schematic D ia gr a ms

CD4020BC

CD4040BC

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CD4020BC • CD4040BC • CD4060BC

Schematic Diagrams (Continued) CD4060BC

CD4060B Typi cal Oscillator Connections

RC Oscillator

Crystal Oscillator

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CD4020BC • CD4040BC • CD4060BC

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the de vices sh ould be oper ated at thes e limits. T he tables of “Recom-

mend ed Oper ating C onditi ons” and “Electrical Characteristics” provid e c on-

ditions f or ac t ual dev ic e operation.

Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 2)

Note 3: Data does not appl y to oscillator points φ0 and φ0 of CD4060BC. IOH and IOL are tested one output at a time.

Supply Voltage (VDD)−0.5V to +18V

Input Voltage (VIN)−0.5V to VDD +0.5V

Storage Temperat ure Range (TS)−65°C to +150°C

Package Dissipation (PD)

Dual-In-Line 700 mW

Small Out lin e 500 mW

Lead Temperature (TL)

(Solder ing, 10 seco nds) 260°C

Supply Voltage (VDD)+3V to +15V

Input Voltage (VIN) 0V to VDD

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD = 5V, VIN = VDD or VSS 5 5 150 µAVDD = 10V, VIN = VDD or VSS 10 10 300

VDD = 15V, VIN = VDD or VSS 20 20 600

VOL LOW Level Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 VVDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0

VIH HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 VVDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0

IOL LOW Level Output Current VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mA(Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIGH Level Output Current VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mA(Note 3) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4020BC • CD4040BC • CD4060BC

AC Electrical Characteristics (Note 4)

CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted

Note 4: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Symbol Parameter Conditions Min Typ Max Units

tPHL1, tPLH1 Propagation Delay Time to Q1VDD = 5V 250 550 nsVDD = 10V 100 210

VDD = 15V 75 150

tPHL, tPLH Interstage Propagation Delay Ti me VDD = 5V 150 330 nsfrom Qn to Qn+1VDD = 10V 60 125

VDD = 15V 45 90

tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100

VDD = 15V 40 80

tWL, tWH Minimum Clock Pulse Width VDD = 5V 125 335 nsVDD = 10V 50 125

VDD = 15V 40 100

trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit nsVDD = 10V No Limit

VDD = 15V No Limit

fCL Maximum Clock Frequency VDD = 5V 1.5 4 MHzVDD = 10V 4 10

VDD = 15V 5 12

tPHL(R) Reset Propagation Delay VDD = 5V 200 450 nsVDD = 10V 100 210

VDD = 15V 80 170

tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 nsVDD = 10V 100 210

VDD = 15V 80 170

CIN Average Input Capacitance Any Input 5 7.5 pF

CPD Power Dissipation Capacitance 50 pF

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CD4020BC • CD4040BC • CD4060BC

AC Electrical Characteristics (Note 5)

CD4060BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted

Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.

RC Oscillator Notes:

Symbol Parameter Conditions Min Typ Max Units

tPHL4, tPLH4 Propagation Delay Time to Q4VDD = 5V 550 1300 nsVDD = 10V 250 525

VDD = 15V 200 400

tPHL, tPLH Interstage Propagation Delay Time VDD = 5V 150 330 nsfrom Qn to Qn+1VDD = 10V 60 125

VDD = 15V 45 90

tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100

VDD = 15V 40 80

tWL, tWH Minimum Clock Pulse Width VDD = 5V 170 500 nsVDD = 10V 65 170

VDD = 15V 50 125

trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit nsVDD = 10V No Limit

VDD = 15V No Limit

fCL Maximum Clock Frequency VDD = 5V 1 3 MHzVDD = 10V 3 8

VDD = 15V 4 10

tPHL(R) Reset Propagation Delay VDD = 5V 200 450 nsVDD = 10V 100 210

VDD = 15V 80 170

tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 nsVDD = 10V 100 210

VDD = 15V 80 170

CIN Average Input Capacitance Any Input 5 7.5 pF

CPD Power Dissipation Capacitance 50 pF

1. R2 = 2 R1 to 10 R1

2. RC Oscillator applications are not recommended at supply voltages below 7.0V for R1 < 50 kΩ

3. f ≈ 1at VCC = 10V

2.2 R1 CX

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CD4020BC • CD4040BC • CD4060BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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CD4020BC • CD4040BC • CD4060BC

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5 .3mm Wide

Package Number M16D

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CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary

Counters • 14-Stage Ripple Carry Binary Counters

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.