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FEATURES
SN54LVC646A . . . JT OR W PACKAGE
SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4 3 2 1 28
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
DIR
SAB
CLKAB
B8
B7
A8
GND
NC NC
CLKBA
SBA
V
A7
B6
17 18
27 26
CC
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
Operate From 1.65 V to 3.6 V I
off
Supports Partial-Power-Down ModeOperationInputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 250 mA PerMax t
pd
of 7.4 ns at 3.3 V
JESD 17Typical V
OLP
(Output Ground Bounce)
ESD Protection Exceeds JESD 22<0.8 at V
CC
= 3.3 V, T
A
= 25 °C
2000-V Human-Body Model (A114-A)Typical V
OHV
(Output V
OH
Undershoot)>2 V at V
CC
= 3.3 V, T
A
= 25 °C 200-V Machine Model (A115-A)Support Mixed-Mode Signal Operation on All 1000-V Charged-Device Model (C101)Ports (5-V Input/Output Voltage With xxxx
3.3-V V
CC
)
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V V
CC
operation, and theSN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V V
CC
operation.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 25 SN74LVC646ADWSOIC DW LVC646AReel of 2000 SN74LVC646ADWRSOP NS Reel of 2000 SN74LVC646ANSR LVC646A–40 °C to 85 °C SSOP DB Reel of 2000 SN74LVC646ADBR LC646ATube of 60 SN74LVC646APWTSSOP PW Reel of 2000 SN74LVC646APWR LC646AReel of 250 SN74LVC646APWTCDIP JT Tube of 15 SNJ54LVC646AJT SNJ54LVC646AJT–55 °C to 125 °C CFP W Tube of 85 SNJ54LVC646AW SNJ54LVC646AWLCCC FK Tube of 42 SNJ54LVC646AFK SNJ54LVC646AFK
(1) Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters areInstruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, productionnecessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexedtransmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clockedinto the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices.
Output-enable ( OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIRdetermines which bus receives data when OE is low. In the isolation mode ( OE high), A data is stored in oneregister and B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmitdata. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables theoutputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS DATA I/O
OPERATION ORFUNCTIONOE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
X X X X X Input Unspecified
(1)
Store A, B unspecified
(1)
XXXX X Unspecified
(1)
Input Store B, A unspecified
(1)
H X X X Input Input Store and B dataH X H or L H or L X X Input disabled Input disabled Isolation, hold storageL L X X X L Output Input Real-time B data to A busL L X H or L X H Output Input Stored B data to A busL H X X L X Input Output Real-time A data to B busL H H or L X H X Input Output Stored A data to B bus
(1) The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e.,data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
21
X
3
DIR
X
1
CLKAB 23
CLKBA
X
2
SAB
X
22
SBA
X
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
X
HX
XX X
XX
XL H H or L X H X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
REAL-TIME TRANSFER
BUS B TO BUS A REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
Figure 1. Bus-Management Functions
3
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A1 B1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
21
3
23
22
1
2
420
1D
C1
1D
C1
Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages.
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
4
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mADB package 63DW package 46θ
JA
Package thermal impedance
(4)
°C/WNS package 65PW package 88T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
SN54LVC646A SN74LVC646A
UNITMIN MAX MIN MAX
Operating 2 3.6 1.65 3.6V
CC
Supply voltage VData retention only 1.5 1.5V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8 0.8V
I
Input voltage 0 5.5 5.5 VHigh or low state 0 V
CC
V
CCV
O
Output voltage V3-state 0 5.5 5.5V
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current mAV
CC
= 2.7 V –12 –12V
CC
= 3 V –24 –24V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current mAV
CC
= 2.7 V 12 12V
CC
= 3 V 24 24t/ v Input transition rise or fall rate 10 10 ns/VT
A
Operating free-air temperature –55 125 –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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Electrical Characteristics
Timing Requirements
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC646A SN74LVC646APARAMETER TEST CONDITIONS V
CC
UNITMIN TYP
(1)
MAX MIN TYP
(1)
MAX
1.65 V to 3.6 V V
CC
0.2I
OH
= –100 µA
2.7 V to 3.6 V V
CC
0.2I
OH
= –4 mA 1.65 V 1.2V
OH
I
OH
= –8 mA 2.3 V 1.7 V2.7 V 2.2 2.2I
OH
= –12 mA
3 V 2.4 2.4I
OH
= –24 mA 3 V 2.2 2.21.65 V to 3.6 V 0.2I
OL
= 100 µA
2.7 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45V
OL
VI
OL
= 8 mA 2.3 V 0.7I
OL
= 12 mA 2.7 V 0.4 0.4I
OL
= 24 mA 3 V 0.55 0.55ControlI
I
V
I
= 0 to 5.5 V 3.6 V ±5±5µAinputsI
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
OZ
(2)
V
O
= 0 to 5.5 V 3.6 V ±15 ±10 µAV
I
= V
CC
or GND 10 10I
CC
I
O
= 0 3.6 V µA3.6 V V
I
5.5 V
(3)
10 10One input at V
CC
0.6 V,I
CC
2.7 V to 3.6 V 500 500 µAOther inputs at V
CC
or GNDControlC
i
V
I
= V
CC
or GND 3.3 V 4.5 4.5 pFinputs
A or BC
io
V
O
= V
CC
or GND 3.3 V 7.5 7.5 pFport
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) For I/O ports, the parameter I
OZ
includes the input leakage current.(3) This applies in the disabled state only.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )
SN54LVC646A
V
CC
= 3.3 VV
CC
= 2.7 V UNIT±0.3 V
MIN MAX MIN MAX
f
clock
Clock frequency 150 150 MHzt
w
Pulse duration 3.3 3.3 nst
su
Setup time, data before CLK 1.6 1.5 nst
h
Hold time, data after CLK 1.7 1.7 ns
6
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Timing Requirements
Switching Characteristics
Switching Characteristics
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )
SN74LVC646A
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 V UNIT±0.18 V ±0.2 V ±0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency
(1) (1)
150 150 MHzt
w
Pulse duration
(1) (1)
3.3 3.3 nst
su
Setup time, data before CLK
(1) (1)
1.6 1.5 nst
h
Hold time, data after CLK
(1) (1)
1.7 1.7 ns
(1) This information was not available at the time of publication.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )
SN54LVC646A
FROM TO V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ±0.3 V
MIN MAX MIN MAX
f
max
150 150 MHzA or B B or A 7.9 1 7.4t
pd
CLK 8.8 1 8.4 nsA or BSBA or SAB 9.9 1 8.6t
en
OE A 10.2 1 8.2 nst
dis
OE A 8.9 1 7.5 nst
en
DIR B 10.4 1 8.3 nst
dis
DIR B 8.7 1 7.9 ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )
SN74LVC646A
FROM TO V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ±0.15 V ±0.2 V ±0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
max
(1) (1)
150 150 MHzA or B B or A
(1) (1) (1) (1)
7.9 1 7.4t
pd
CLK
(1) (1) (1) (1)
8.8 1 8.4 nsA or BSBA or SAB
(1) (1) (1) (1)
9.9 1 8.6t
en
OE A
(1) (1) (1) (1)
10.2 1 8.2 nst
dis
OE A
(1) (1) (1) (1)
8.9 1 7.5 nst
en
DIR B
(1) (1) (1) (1)
10.4 1 8.3 nst
dis
DIR B
(1) (1) (1) (1)
8.7 1 7.9 ns
(1) This information was not available at the time of publication.
7
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Operating Characteristics
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
Outputs enabled
(1) (1)
75Power dissipation capacitanceCpd f = 10 MHz pFper transceiver
Outputs disabled
(1) (1)
9
(1) This information was not available at the time of publication.
8
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH − V0 V
VI
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
SN54LVC646A, SN74LVC646AOCTAL BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
SCAS302J JANUARY 1993 REVISED AUGUST 2005
Figure 2. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9762601Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9762601Q3A
SNJ54LVC
646AFK
5962-9762601QKA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9762601QK
A
SNJ54LVC646AW
5962-9762601QLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9762601QL
A
SNJ54LVC646AJT
SN74LVC646ADBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI -40 to 85
SN74LVC646ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646ADW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC646A
SN74LVC646ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC646A
SN74LVC646ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC646A
SN74LVC646APW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI -40 to 85
SN74LVC646APWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC646APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWT ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SN74LVC646APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC646A
SNJ54LVC646AFK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9762601Q3A
SNJ54LVC
646AFK
SNJ54LVC646AJT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9762601QL
A
SNJ54LVC646AJT
SNJ54LVC646AW ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9762601QK
A
SNJ54LVC646AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC646A, SN74LVC646A :
Catalog: SN74LVC646A
Military: SN54LVC646A
Space: SN54LVC646A-SP
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC646ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC646APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC646APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC646ADBR SSOP DB 24 2000 367.0 367.0 38.0
SN74LVC646APWR TSSOP PW 24 2000 367.0 367.0 38.0
SN74LVC646APWT TSSOP PW 24 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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