[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, CD4070B, CD4077B Data sheet acquired from Harris Semiconductor SCHS055E CMOS Quad Exclusive-OR and Exclusive-NOR Gate January 1998 - Revised September 2003 Features Ordering Information * High-Voltage Types (20V Rating) PART NUMBER * CD4070B - Quad Exclusive-OR Gate TEMP. RANGE (oC) PACKAGE * CD4077B - Quad Exclusive-NOR Gate CD4070BE -55 to 125 14 Ld PDIP * Medium Speed Operation - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF CD4070BF3A -55 to 125 14 Ld CERDIP * 100% Tested for Quiescent Current at 20V CD4070BM -55 to 125 14 Ld SOIC * Standardized Symmetrical Output Characteristics CD4070BMT -55 to 125 14 Ld SOIC * 5V, 10V and 15V Parametric Ratings CD4070BM96 -55 to 125 14 Ld SOIC * Maximum Input Current of 1A at 18V Over Full Package Temperature Range - 100nA at 18V and 25oC CD4070BNSR -55 to 125 14 Ld SOP CD4070BPW -55 to 125 14 Ld TSSOP * Noise Margin (Over Full Package Temperature Range) - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V CD4070BPWR -55 to 125 14 Ld TSSOP CD4077BE -55 to 125 14 Ld PDIP CD4077BF3A -55 to 125 14 Ld CERDIP CD4077BM -55 to 125 14 Ld SOIC CD4077BMT -55 to 125 14 Ld SOIC CD4077BM96 -55 to 125 14 Ld SOIC CD4077BNSR -55 to 125 14 Ld SOP CD4077BPW -55 to 125 14 Ld TSSOP CD4077BPWR -55 to 125 14 Ld TSSOP * Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices Applications * Logical Comparators * Adders/Subtractors * Parity Generators and Checkers Description The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates. NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2003, Texas Instruments Incorporated 1 CD4070B, CD4077B Pinouts CD4070B (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW CD4077B (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW A 1 14 VDD A 1 14 VDD B 2 13 H B 2 13 H J=AB 3 12 G J=AB 3 12 G K=CD 4 11 M = G H K=CD 4 11 M = G H C 5 10 L = E F C 5 10 L = E F D 6 9 F D 6 9 F VSS 7 8 E VSS 7 8 E Functional Diagrams CD4070B A J=AB K=CD M=G H L=EF VSS = 7 VDD = 14 B C D E F G H 1 CD4077B 3 2 5 9 12 13 B J =A 4 6 8 A J 10 11 K=C K L B D H =EF C D M=G E L F G M H 2 1 3 2 5 4 6 8 9 12 13 10 11 J K L M CD4070B, CD4077B VDD VDD VDD p VDD B p 2(5,9,12) n p 1(6,8,13) n p n J p n 3(4,10,11) n VDD n p p J VDD p VSS n VSS VDD A 2(5,9,12) n VSS p B p A p 1(6,8,13) n n VSS VSS INPUTS PROTECTED BY CMOS PROTECTION NETWORK 3(4,10,11) n VSS VDD INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES) FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B (1 OF 4 IDENTICAL GATES) CD4070B TRUTH TABLE (1 OF 4 GATES) CD4077B TRUTH TABLE (1 OF 4 GATES) A B J A B J 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 1 1 1 NOTE: 1 = High Level 0 = Low Level J=AB NOTE: 1 = High Level 0 = Low Level J=AB 3 CD4070B, CD4077B Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Package Thermal Impedance, JA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W Maximum Junction Temperature (Hermetic Package or Die) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS PARAMETER Quiescent Device Current IDD Max Output Low (Sink) Current IOL Min Output High (Source) Current IOH Min Output Voltage: Low Level, VOL Max Output Voltage: High Level, VOH Min Input Low Voltage, VIL Max Input High Voltage, VIH Min Input Current, IIN Max 25 VO (V) VIN (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 A - 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 A - 0, 15 15 1 1 30 30 - 0.01 1 A - 0, 20 20 5 5 150 150 - 0.02 5 A 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA 2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V - 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V - 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V 1, 9 - 10 3 3 3 3 - - 3 V 1.5, 13.5 - 15 4 4 4 4 - - 4 V 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V 1, 9 - 10 7 7 7 7 7 - - V 1.5, 13.5 - 15 11 11 11 11 11 - - V - 0, 18 18 0.1 0.1 1 1 - 10-5 0.1 A 4 CD4070B, CD4077B AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200k TEST CONDITIONS PARAMETER Propagation Delay Time Transition Time SYMBOL VDD (V) TYP MAX UNITS tPHL, tPLH 5 140 280 ns 10 65 130 ns 15 50 100 ns 5 100 200 ns 10 50 100 ns 15 40 80 ns Any Input 5 7.5 pF tTHL, tTLH Input Capacitance LIMITS ON ALL TYPES CIN TA = 25oC IOL, OUTPUT LOW (SINK) CURRENT (mA) GATE TO SOURCE VOLTAGE (VGS) = 15V 30 25 20 10V 15 10 5V 5 0 0 5 10 15 TA = 25oC 15 GATE TO SOURCE VOLTAGE (VGS) = 15V 12.5 10 10V 7.5 5 5V 2.5 0 0 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) -15 -10 -5 TA = 25oC GATE TO SOURCE VOLTAGE (VGS) = -5V 0 0 -5 -10 -15 -10V -20 -25 -15V -30 IOH, OUTPUT HIGH (SOURCE) CURRENT (mA) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -15 -10 -5 0 0 TA = 25oC GATE TO SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -10 -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 5 IOH, OUTPUT HIGH (SINK) CURRENT (mA) IOL, OUTPUT LOW (SINK) CURRENT (mA) Typical Performance Curves (Continued) tPHL, tPLH, PROPAGATION DELAY TIME (ns) tTHL, tTLH, TRANSITION TIME (ns) Typical Performance Curves TA = 25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 15V 0 0 20 40 60 80 100 TA = 25oC 300 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 0 0 110 20 105 TA = 25oC LOAD CAPACITANCE CL = 50pF 300 200 100 0 5 10 15 60 80 100 FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE PD, POWER DISSIPATION (W) tPHL, tPLH, PROPAGATION DELAY TIME (ns) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 0 40 CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) VDD, SUPPLY VOLTAGE (V) FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF SUPPLY VOLTAGE V 104 )= 15 D E AG LT O YV PL 103 102 (V D P SU 10 10V CL = 50pF 10V CL = 15pF 5V 1 10-1 10-1 20 TA = 25oC 1 102 103 10 fI, INPUT FREQUENCY (kHz) 104 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 6 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD4070BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD4070BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD4070BF ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type CD4070BF3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type CD4070BM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BM96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BMT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BMTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4070BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD4077BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) CD4077BF ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type CD4077BF3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type CD4077BM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BM96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BMT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BMTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD4077BNSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD4077BNSRE4 ACTIVE SO NS 14 CD4077BPW ACTIVE TSSOP PW 14 90 CD4077BPWE4 ACTIVE TSSOP PW 14 90 CD4077BPWR ACTIVE TSSOP PW CD4077BPWRE4 ACTIVE TSSOP JM38510/17203BCA ACTIVE CDIP Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM J 14 1 TBD Call TI N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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